Patent Application
20190337799
The present application claims priority to Chinese Patent Application No. 201810427943.0, filed on May 7, 2018, the content of which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of sensors and in particular, to a method for processing a conductive structure.
Sensors based on Micro-Electro-Mechanical System (MEMS) are widely applied in societies, industries and daily lives, including ultrasonic processing, ultrasonic positioning, ultrasonic probing, ultrasonic imaging and the like.
In order to provide electrical connectivity, when a MEMS sensor is manufactured, conductive terminals made of aluminum are provided at both sides of a silicon base. Further, a conductive via needs to be processed in the silicon base and a conductive material needs to be filled in the conductive via to provide electrical connectivity. The existing methods for processing the via mainly include mechanical drilling or wet chemical etching. However, the mechanical drilling is not convenient for industrial production and the wet chemical etching is only applicable to thin silicon bases having thicknesses smaller than 100 μm.
There is thus a need for a novel method for processing a conductive structure to solve the above problem.
In the following, the present disclosure will be further explained with reference to the figures and embodiments.
As shown in
In particular, the method includes the following steps.
At step S1, as shown in
At step S2, as shown in
At step S3, as shown in
At step S4, a conductive structure is processed within the via.
In particular, the step S1 may include the following steps.
At step S11, as shown in
At step S12, the groove concave from the first surface towards the second surface is formed on a portion where the protection layer 2 is not provided by means of dry etching. Due to the large distance between the first surface 11 and the second surface 12, the bottom of the groove 101 formed by means of etching is in the middle of the silicon base 1 and the distance between the bottom of the groove 101 and the first surface 11 is larger than a half of the thickness of the silicon base 1.
At step S13, an oxide layer 3 is formed by means of oxidation from two directions, i.e., from the first surface 11 and the second surface 12. The oxide layer 3 extends into the groove 101 with the first surface 11 to form a blocking layer 31 at the bottom of the groove 101.
At shown in
In the step S3, the via 10 can be cleaned by means of wet oxidation, so as to remove the residual oxide layer. It is to be noted that the steps S2 and S3 can be combined into one step. That is, the blocking layer 31 and the oxide layer on the inner wall of the via 10 can be removed at a time by means of wet oxidation.
Referring to
At step S41, doped polysilicon is deposited within the via. With the conductivity of the doped polysilicon, an electrical connectivity can be provided between the first surface 11 and the second surface 12. In particular, it includes the following steps. At step S411, doped polysilicon is deposited on the silicon base having the via provided therein. A doped polysilicon layer 4 so formed covers the entire first surface 11, the second surface 12 and the inner wall of the via 10. Then, at a step S412, the doped polysilicon deposited on the first surface 11 and the second surface 12 is removed by using a CMP mixed indicator, to form a doped polysilicon layer 4 that only covers the inner wall of the via 10.
At step S42, the oxide layer 3 on the first surface 11 and the second layer 12 is removed by means of wet oxidation, and a first aluminum conductive layer 5 and a second aluminum conductive layer 6 are provided on the first surface 11 and the second surface 12.
At step S43, a pattern on the first aluminum conductive layer and/or the second aluminum conductive layer is formed to form the conductive structure. In particular, it includes the following steps. At step S431, a pattern is formed on the first aluminum conductive layer 5 and/or the second aluminum conductive layer 6 and a protection layer is provided on a portion where the via is not provided. At step S432, the conductive structure is formed by wet etching the first aluminum conductive layer 5 and/or the second aluminum conductive layer 6. In particular, the conductive structure may be a conductive lead and a conductive terminal, which can provide the electrical connectivity together with the doped polysilicon layer 4 formed in the step S41.
It is to be noted that the steps S42 and S43 are not necessarily performed in any specific order. The first surface 11 can be processed first and then the second surface 12 can be processed, or they can be processed simultaneously. The conductive structure can be processed on one surface only and the aluminum conductive layer can be provided on the other surface only. In another example, the conductive structure can be processed on both surfaces as desired.
Compared with the related art, the present disclosure provides a method for processing a conductive structure. It can be applied to a silicon base having a thickness larger than 300 μm. It can effectively break the limit on thicknesses of silicon bases that can be processed in the related art, and can provide electrical connectivity on both sides of the silicon base. The method is simple and highly reliable, has high processing efficiency and is applicable to mechanized production.
While the embodiments of the present disclosure have been described above, the scope of the present disclosure is not limited thereto. Any equivalent structures or equivalent process alternatives made based on the present disclosure, directly or indirectly applied to any other related technical fields, are to be encompassed by the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201810427943.0 | May 2018 | CN | national |
