"Silicon Wafer Preparation for Low-Temperature Selective Epitaxial Growth," Galewski et al., IEEE Trans. on Semicon. Man., vol. 3, No. 3, Aug. 1990 (pp. 93-97). |
"Growth Condition Dependence of SEG Planarity and Electrical Characteristics," Stivers et al., Proc. of 19th Int. Cong. on CVD, Oct. 1987, pp. 389-397. |
"Selective Silicon Deposition for the Megabit Age," Borland et al., Solid State Techn., Jan. 1990, pp. 73-78. |
"Chemical Vapor Deposition of Selective Epitaxial Silicon Layers," Pai et al., J. Electrochem. Soc., vol. 137, No. 3, mar. 1990, pp. 971-976. |
"A Submicron Dual Buried Layer Twin Well CMOS SEG Process," Manoliu et al., IDEM Digest, 1987, pp. 20-23. |