Claims
- 1. A method of depositing a metal layer on a substrate comprising the following steps:
- providing said substrate having an electrically conductive layer on a first surface of said substrate;
- placing said substrate, first surface down, into a cup having an aperture defined by an inner perimeter, wherein a compliant seal is located adjacent said inner perimeter and a plurality of contacts are located adjacent said compliant seal;
- clamping said cup to a cone thereby establishing electrical connection between said plurality of contacts and said electrically conductive layer, thereby pressing a perimeter region of said first surface of said substrate against said compliant seal;
- pressurizing a gas on an outward side of said compliant seal;
- placing said cup into a plating solution thereby exposing a portion of said electrically conductive layer to said plating solution;
- rotating said cup and said substrate; and
- applying voltage to said plurality of contact thereby depositing said first layer on said exposed portion of said electrically conductive layer.
- 2. The method of claim 1 further comprising the steps of:
- turning off said voltage to said plurality of contacts;
- removing said cup including said substrate from said plating solution; and
- removing excess plating solution from said cup and said substrate.
- 3. The method of claim 2 wherein said step of removing comprises rotating said cup and said substrate at 1000 revolutions per minute or greater.
- 4. The method of claim 1 wherein said plurality of contacts are grouped into at least two banks of contacts, said method further comprising, after said step of clamping, the step of checking continuity in resistances between said at least two banks of contacts.
CROSS REFERENCE TO RELATED APPLICATION
This application is a divisional of application Ser. No. 08/969,984, filed Nov. 13, 1997, entitled "Clamshell Apparatus for Electrochemically Treating Semiconductor Wafers," or Evan E. Patton and Wayne Fetters, owned by the assignee of this application. This application is related to Contolini et al., Application Ser. No. 08/969/267filed on Nov. 13, 1997, now abandoned, and Reid et al., Application Ser. No. 08/969,196, filed on Nov. 13, 1997, now abandoned, all of which are incorporated herein by reference in their entirety.
US Referenced Citations (53)
Non-Patent Literature Citations (3)
Entry |
"Upside-Down Resist Coating of Semiconductor Wafers", IBM Technical Disclosure Bulletin, vol. 32, No. 1, Jun. 1989, pp. 311-313. |
Evan E. Patton, et al., "Automated Gold Plate-Up Bath Scope Document and Machine Specifications", Tektronix Confidential, dated Aug. 4, 1989, pp. 1-13. |
Tektronix Invention Disclosure Form (Company Confidential), not dated, 4 pages. |
Divisions (1)
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Number |
Date |
Country |
Parent |
969984 |
Nov 1997 |
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