The present invention is directed in general to a method for manufacturing a microelectronics device, and more specifically, to a method of inducing stress into a channel region of a microelectronics device.
There exists a continuing need to improve semiconductor device performance and further scale microelectronic devices. One characteristic that limits scalability and device performance is electron and hole mobility, also referred to as channel mobility, throughout the channel region of transistors. As devices continue to shrink in size, the channel region for transistors continues to also shrink in size, which can limit channel mobility.
One technique that may improve scaling limits and device performance is to introduce strain into the channel region, which can improve electron and hole mobility. Different types of strain, including expansive strain, tensile strain, and compressive strain, have been introduced into channel regions of various types of transistors in order to determine their affect on electron and/or hole mobility. Often, stress is introduced into the channel region by depositing a silicon nitride stress-inducing liner over the gate structures of the transistors. This liner is used to induce stress into the channel region of the transistor, and under preferred circumstances higher deposition temperatures are desirable to incorporate the desired amount of stress into the channel region. However, due to advances in technologies, the benefits obtained from the use of such liners as begun to encounter process limitations.
As device sizes have shrunk and performance requirements have increased, the industry has also sought ways in which to combat depletion within the reduced gate structures. To address this issue, the industry has found that it is highly advantageous to incorporate metal into polysilicon gates to form silicided gates. Because of the presence of the metal within the polysilicon gates, silicided gates suffer substantially less depletion effects and thereby meet the higher performance requirements of today's microelectronic devices. As such, silicided gates and fully silicided gates have gained in popularity.
Unfortunately, however, the amount of stress that can be incorporated into devices that include silicided gate structures by using the silicon nitride liner is limited due to thermal budgets. Typically, the amount of stress formed in the channel can be increased by increasing the deposition temperatures of the silicon nitride liner. However, these more desirable, higher temperatures, unfortunately, can lead to nickel piping defects within the silicided gate structures, which, in turn decreases transistor performance. Thus, when using silicon nitride materials as the liner, the maximum amount of stress cannot be incorporated into the channel region due to the required lower thermal budgets that are necessary to avoid nickel piping defects.
Accordingly, what is needed in the art is a process that avoids the deficiencies of the conventional processes discussed above.
To overcome the deficiencies in the prior art, the present invention, in one embodiment, provides a method of fabricating a microelectronics device. This embodiment comprises forming a liner over a substrate and a gate structure, subjecting the liner to an electron beam, and depositing a pre-metal dielectric layer over the liner.
Another embodiment provides a method of fabricating an integrated circuit. This method comprises forming transistors that comprise gate electrodes over a microelectronics substrate, forming a liner over the microelectronics substrate and the gate electrodes, subjecting the liner to an electron beam, depositing a pre-metal dielectric layer over the liner, forming interlevel dielectric layers over the pre-metal dielectric layer, and forming interconnects in the pre-metal and interlevel dielectric layers to electrically connect the transistors to form an operative integrated circuit.
The foregoing has outlined preferred and alternative features of the present invention so that those of ordinary skill in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the scope of the invention.
The invention is best understood from the following detailed description when read with the accompanying FIGUREs. It is emphasized that in accordance with the standard practice in the semiconductor industry, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Turning initially to
The gate structures 130, 132 illustrated in
The gate electrodes 150 may also include a dopant or combination of several types of dopants therein. The dopant, such as boron, phosphorous, arsenic or another similar dopants, based on whether the semiconductor device 100 is operating as a PMOS device or an NMOS device, is configured to tune the minimum energy required to bring an electron from the Fermi level to the vacuum level, or the so called work function.
The gate structures 130, 132 further include conventional gate sidewall spacers 160 flanking both sides of the gate electrodes 150 and gate oxide 140. As seen in the illustrated embodiment, the gate sidewall spacers 160 in the embodiment of
The microelectronics device 100 illustrated in
Located within the source/drains 170 are silicided source/drain contacts 180. The silicided source/drain contacts 180 in this embodiment comprise silicided nickel. Nonetheless, other metals could be used to form the silicided source/drains 180 and remain within the scope of the present invention. The silicided source/drain contacts 180 may have a depth into the source/drains 170 that ranges from about 10 nm to about 30 nm, among others. Contact plugs 185 are formed in a pre-metal dielectric layer 190 that overlies the gate structures 130, 132 and contact the silicided source/drain contacts 180. The pre-metal dielectric layer 190 is the layer in which the contact plugs 185 are formed and is the dielectric layer on which first metal interconnects are formed.
The microelectronics device 100 also includes a liner 182 that is located over the gate electrodes 150 and the substrate 110. As explained below, the liner 182 that overlies a targeted gate electrode is subjected to an electron beam such that it imparts a stress, indicated by the arrows 184, into the liner, and thus, into the NMOS channel region, which is located between source/drains regions 170. The stress increases electron mobility within the channel region, which in turn, increases the device speed. If the stress is being imparted into the NMOS channel region, the stress is preferably a tensile stress. As explained below, however, the type (tensile versus compressive) and amount of stress imparted can depend on the material from which the liner 182 is made and the duration and intensity of the liner's 182 subjection to the electron beam.
The method of using the electron beam provides advantages over other conventional methods of imparting stress into the channel region in that it can be conducted at much lower temperatures, even to room temperature (e.g. 22° C.). The use of such lower temperatures avoids nickel piping defects within the silicided portions of the microelectronics device 100 that can occur with conventional stress-inducing methods. The electron beam method is also of much shorter duration than other conventional methods, which reduces manufacturing time and thereby increases product output. Moreover, because the electron beam can be tightly controlled, the electron beam can be used without the need of masking the untargeted gate electrodes, which results in a “direct-write” method use of the electron beam. This not only saves times, but it also reduces manufacturing costs.
Turning now to
Located within the substrate 210 in the embodiment shown in
Located over the substrate 210 in the embodiment of
While the advantageous embodiment of
The gate electrodes 250 desirably have a thickness ranging from about 50 nm to about 150 nm, and in one embodiment, the thickness is about 80 nm. Conventional blanket deposition and patterning processes may be used to form the gate electrodes 250 and gate oxides 240.
As mentioned above, the gate electrodes 250 may be doped with one or more metals to form a silicided gate electrode. Conventional deposition processes may be used to locate a metal layer over an exposed surface of the gate electrodes 250. The thickness of the metal layer may vary and will depend, in some embodiments, on the thickness of the gate electrodes 250. For example, in one embodiment where the thicknesses of the gate electrodes 250 are about 80 nm thick, the thickness of the metal layer will be about 60 nm. Preferably, the metal layer is thick enough such that full silicidation of the gate electrodes 250 occurs. However, in other embodiments, full silicidation may not be necessary. In such cases, the metal layer may be thinner. The silicidation can be conducted until the desired work function of the respective gate electrodes 250 is achieved or the gate electrodes 250 are fully silicided.
The deposited metal layer may be nickel or cobalt or a combination thereof. In those embodiments where the metal layer is nickel, an exemplary silicide process comprises placing a blanket of nickel layer over the gate electrodes 250. As it takes approximately 1 nm of nickel to fully silicide approximately 1.8 nm of polysilicon, the thickness of the blanket layer of nickel should be at least 56% of the thickness of the gate electrode 250. To be comfortable, however, it is suggested that the thickness of the layer of nickel should be at least 60% of the thickness of the gate electrode 250. Thus, where the thickness of the gate electrode 250 ranges from about 50 nm to about 150 nm, as described above, the thickness of the blanket layer of nickel should range from approximately 30 nm to about 90 nm. It should also be noted that the blanket layer of metal layer may comprise a number of different metals or combinations of metals, such as nickel and cobalt, while staying within the scope of the present invention.
The nickel layer and the gate electrodes 250 are subjected to a thermal anneal having a temperature ranging from about 400 degrees centigrade to about 600 degrees centigrade and for a period of time ranging from about 10 seconds to about 100 seconds. It should be noted, however, that the silicidation process may vary depending on the amount of silicidation that is desired and the materials that are used to silicide the gate electrodes 250. For example, if the gate electrodes 250 are silicided with a combination of cobalt and nickel, then the silicidation process parameters and percentages of materials used will be different than those just stated above. Those who are skilled in the art will understand how to achieve the desired degree of silicidation when using such metal combinations.
The exemplary embodiment of
Following the patterning of the gate electrodes 250 and gate oxides 240 and formation of the sidewall spacers, the above-mentioned source/drains 270 are conventionally formed adjacent the gate electrodes 250. Generally the source/drain implant involves a high dopant concentration that has a peak dopant concentration ranging from about 1E18 atoms/cm3 to about 1E21 atoms/cm3. Also, the highly doped source/drain implant should typically have a dopant type opposite to that of the well region in which they are located. Following the source/drain implant, a standard source/drain anneal is conducted to activate the source/drains 270. It is believed that a source/drain anneal conducted at a temperature ranging from about 1000° C. to about 1100° C. and a time period ranging from about 1 second to about 5 seconds would be sufficient. It should be noted that other temperatures, times, and processes could be used to activate the source/drains 270, and such processes are known to those skilled in the art. Following the formation of the source/drains 270, silicided contact regions 280 are conventionally formed.
Turning now to
The types of materials used to construct the liner 310 may also vary. In one embodiment, the liner 310 may comprise silicon, nitrogen or carbon. Examples of materials that can be used to form the liner 310 include silicon nitride (SiN), silicon carbide (SiC), and silicon oxy-carbide (SiCO). The way in which the liner 310 is formed can control the magnitude and type of stress produced. For example, a compressive stress inducing silicon nitride based liner can be obtained by forming the silicon nitride in a chamber by a plasma enhanced chemical vapor deposition (PEVCD) process with a temperature ranging from about 300° C. to about 450° C., a pressure ranging from about 2.0 to 2.5 torr, a silane flow of about 20 sccm, an ammonia flow of about 500 sccm, a nitrogen gas flow of about 2000 sccm, a high frequency RF power of about 20 watts and a lower frequency RF power of about 50 watts. The deposition temperature, however, should not exceed about 450° C. to avoid the piping defects mentioned above. In conventional processes, these lower deposition temperatures would substantially inhibit the liner's ability to impart the desired amount of stress into the channel region. However, with the present invention, the reduced amount of stress due to deposition temperatures can be compensated for by use of the electron beam curing process.
As another example, a tensile stress inducing silicon nitride based liner can be obtained by forming the silicon nitride with a temperature ranging from about 300° C. to about 450° C., a pressure ranging from about 4.0 torr to about 6.0 torr, a silane flow of about 100 sccm, an ammonia flow of about 3000 sccm, a nitrogen gas flow of about 2000 sccm, a high frequency RF power of about 50 watts and a lower frequency RF power of about 15 watts. In advantageous embodiments, to improve the performance of a PMOS device, a compressive stress is preferred, and to improve the performance of an NMOS device, a tensile stress is preferred. It should be understood that the above examples are provided for illustrative purposes and that the present invention contemplates other formation parameters.
Silicon carbide based liners are generally formed as compressive strain inducing liners. An exemplary nitrogen doped silicon carbide based liner is obtained by forming the liner within a chamber with a temperature of about 350° C., a pressure of about 3.0 torr, a tri-methysilane flow of about 160 sccm, an ammonia flow f about 325 sccm, a helium flow of about 400 sccm, and a RF power of about 300 watts.
The liner 310 shown in
Turning now to
As also mentioned above, the present invention also advantageously provides a method wherein the time required to incorporate a substantial amount of stress is significantly reduced over conventional process. For example, ultra violet light curing process can require from about 10 to 20 minutes to conduct where as the present invention, in one embodiment, provides that the liner 310 is exposed to the electron beam for a period of time ranging from about 30 seconds to about 1 minute.
Turning now to
With continued reference to
Referring finally to
Although the present invention has been described in detail, one who is of ordinary skill in the art should understand that they can make various changes, substitutions, and alterations herein without departing from the scope of the invention.