Patent Application
20090149027
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating (or dielectric) layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.
A transistor is an element that is utilized extensively in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET). Complementary MOS (CMOS) devices, use both positive and negative channel devices, e.g., a positive channel metal oxide semiconductor (PMOS) transistor and a negative channel metal oxide semiconductor (NMOS) transistor, in complimentary configurations. An NMOS device negatively charges so that the transistor is turned on or off by the movement of electrons, whereas a PMOS device involves the movement of electron vacancies.
The gate dielectric for MOSFET devices has in the past typically comprised silicon dioxide, which has a dielectric constant of about 3.9. However, as devices are scaled down in size, using silicon dioxide for a gate dielectric becomes a problem because of gate leakage current, which can degrade device performance. Therefore, there is a trend in the industry towards the development of the use of high dielectric constant (k) materials for use as the gate dielectric in MOSFET devices. High k gate dielectric development has been identified as one of the future challenges in the 2002 edition of International Technology Roadmap for Semiconductors (ITRS), which identifies the technological challenges and needs facing the semiconductor industry over the next 15 years.
In the accompanying drawings:
Referring to
Layer 2 (further layer), which is arranged on layer 1, is configured to be a diffusion barrier that thwarts a diffusion out of high k layer 1. In an example, layer 2 comprises titanium nitride. In another embodiment of the invention layer 2 is configured to be a conductive layer (i.e., it comprises a conductive material), wherein it can (but does not necessarily have to) act as a diffusion barrier at the same time.
In an embodiment of the invention the layer stack comprising layers 1 and 2 is to be used for the fabrication of a transistor, wherein the high k layer 1 is to be used as a high k gate dielectric of the transistor and layer 2 comprises a conductive material and constitutes a diffusion barrier between the high k gate dielectric and another layer (not shown) of a gate electrode stack of the transistor. However, the invention is not restricted to the fabrication of transistors but can be used for the fabrication of any integrated circuit that includes a high k material in the form of a metal oxide composition; e.g., capacitors of a semiconductor device.
In a further example, the etching is performed using a plasma to decompose the silicon halogen composition of the etchant such that a plasma containing silicon and halogen components is created. The plasma is created in a plasma chamber, e.g., using inductive coupling (ICP) or any other method known for plasma creation.
For example, a flow of about 20 sccm of a silicon tetrachloride gas (SiCl4) is used. Further, the etchant can additionally comprise Cl2 gas (e.g., with a flow of about 30 sccm) and an additional percentage of N2 gas (e.g., with a flow of about 40 sccm). Exemplarily, a pressure of about 10 mTorr is used and a temperature in the region of an electrode of the plasma chamber (for plasma generation and on which the substrate can be arranged) is chosen to be approximately 50° C.
During the etching of high k layer 1 with the silicon halogen composition an intermediate composition in the form of a metal silicon oxide composition can be created. This intermediate composition, e.g., comprises hafnium silicide oxide in case layer 1 comprises hafnium oxide. A metal silicon oxide composition tends to have a higher etchability than its metal oxide counterpart such that the usage of a silicon halogen composition as etchant tends to provide higher etch rates.
The etchant that is used for etching layers 1 and 2 comprises a silicon halogen gas in the form of silicon tetrachloride, wherein a single silicon tetrachloride molecule (labelled SiC4) is illustrated in
As further illustrated in
Referring to
Similarly to
One reaction path leads to the generation of hafnium chloride (HfClx), wherein another reaction path results in the generation of hafnium silicide oxide chloride molecules (HfOSiClx). The latter can be generated via an intermediate composition comprising hafnium silicide oxide (not shown) that occurs when the silicon tetrachloride (and the SiClx+ ions, respectively) react with the hafnium oxide of the high k layer.
It is noted, that the etchant used to etch the high k layer can of course comprise a plurality of components, i.e., it can contain further materials (gases) such as nitrogen (e.g., for side wall passivation) or chlorine in addition to the silicon halogen composition.
