Claims
- 1. A method of fabricating a lightly doped drain semiconductor device comprising the steps of:
- forming a gate electrode comprising a gate insulating film and a polycrystalline silicon layer on a silicon substrate;
- forming a low concentration impurity region of a source/drain region by injecting low concentration impurity ions while using said gate electrode as a mask;
- forming an amorphous region by injecting inert gas ions into said low concentration impurity region to make said source/drain region amorphous while using said gate electrode as a mask;
- forming an insulating film on said silicon substrate and anisotropically etching said insulating film to remove said insulting film except a portion of said insulating film on a sidewall of said gate electrode;
- forming a high concentration impurity region of said source/drain region by injecting impurity ions having a different conductivity type from that of said silicon substrate while using said gate electrode and said portion of said insulating film on said gate electrode sidewall as a mask; and
- activating said source/drain region through a low temperature annealing process to thereby form a shallow junction.
- 2. A method of fabricating a lightly doped drain semiconductor device, comprising the steps of:
- forming a gate insulating film on a silicon substrate and a gate electrode of a polycrystalline silicon layer on said gate insulating film,
- forming a source/drain region having a low concentration of dopants by ion injection of impurity ions having a different conductivity type from that of said silicon substrate while using said gate electrode is a mask,
- making said source/drain region amorphous by injecting inert gas ions into said source/drain region having said low concentration of dopants while using said gate electrode as a mask,
- forming a spacer at a sidewall of said gate electrode by anisotropic etching,
- forming a high concentration impurity region of said source/drain region by injecting impurity ions having a different conductivity type from that of said silicon substrate while using said gate electrode and said spacer as a mask, and
- forming a shallow junction by activating said source/drain region through a low temperature annealing process or rapid thermal annealing process.
- 3. The method of fabricating a semiconductor device as claimed in claim 2, wherein said spacer is made of polycrystalline silicon.
- 4. The method of fabricating a semiconductor device as claimed in claim 2, wherein said spacer is made of silicon oxide.
Priority Claims (6)
Number |
Date |
Country |
Kind |
59-176076 |
Aug 1984 |
JPX |
|
60-43951 |
Mar 1985 |
JPX |
|
60-83134 |
Apr 1985 |
JPX |
|
60-119137 |
May 1985 |
JPX |
|
60-102968 |
May 1985 |
JPX |
|
60-120092 |
Jun 1985 |
JPX |
|
Parent Case Info
This is a continuation of application Ser. No. 07/594,919 filed Oct. 9, 1990, now abandoned, which is a divisional of application Ser. No. 07/358,491 filed May 30, 1989, now U.S. Pat. No. 4,971,922, which is a continuation application of pending prior application Ser. No. 07/120,444 filed on Nov. 13, 1987 now abandoned, which is a divisional of application Ser. No. 06/768,374 filed on Aug. 22, 1985 now U.S. Pat. No. 4,727,038.
US Referenced Citations (11)
Foreign Referenced Citations (7)
Number |
Date |
Country |
2578096 |
Aug 1986 |
FRX |
0220814 |
Apr 1985 |
DDX |
1966237 |
Jan 1972 |
DEX |
0055371 |
May 1979 |
JPX |
60-225473 |
Nov 1985 |
JPX |
0042960 |
Mar 1986 |
JPX |
0034937 |
Feb 1990 |
JPX |
Non-Patent Literature Citations (3)
Entry |
Tsang et al., "Fabrication of High Performance LDDFE's With Oxide Sidewall-Spacer Technology," IEEE Trans. on Electron Devices, vol. ED-29, No. 4, Apr. 1982, p. 590-596. |
Ghandhi, VLSI Fabrication Principles, John Wiley & Sons, Inc. 1983, p. 324. |
Wolf et al., Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, 1986, pp. 307-308. |
Divisions (2)
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Number |
Date |
Country |
Parent |
358491 |
May 1989 |
|
Parent |
768374 |
Aug 1985 |
|
Continuations (2)
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Number |
Date |
Country |
Parent |
594919 |
Oct 1990 |
|
Parent |
120444 |
Nov 1987 |
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