Patent Application
20060063336
This invention relates generally to semiconductors, and more specifically, to making semiconductor devices having very small dimensions.
Transistors have a dielectric layer that electrically isolates a gate electrode from a channel typically positioned in a substrate. The dielectric is desired to have low gate current leakage. A common dielectric layer material is silicon dioxide. Silicon dioxide has a dielectric constant of approximately 3.9. Future generation devices require reduction in the silicon dioxide gate dielectric thickness. Reducing the gate dielectric thickness typically increases the gate current leakage.
As silicon dioxide gate dielectric layers are made thinner, a problem with controlling the uniformity of the thickness of the layer and controlling the manufacturing reliability becomes more difficult. As a result, materials having a higher dielectric constant than silicon dioxide have been proposed as a replacement of the silicon dioxide. Others have recognized that a thin silicon dioxide based interface is required beneath a higher dielectric constant material to improve electron and hole mobility in the transistor channel. This silicon dioxide based interfacial layer between the substrate and the higher dielectric constant material can be formed by either: (1) a chemical oxide grown during a chemical cleaning of the substrate; (2) formation of a deposited or thermally grown silicon dioxide layer; or (3) formation during the deposition of the high dielectric constant material itself as a result of oxygen coming into contact with a silicon substrate.
The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
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An important characteristic of the high dielectric constant layer 16 is the thickness of the high dielectric constant layer 16. We have discovered that it is important to form the high dielectric constant layer 16 with a minimum thickness. For example, the high dielectric constant layer 16 should be formed having a depth of substantially from around 5 nanometers to 20 nanometers. Thermal treatment such as a Post Deposition Anneal (PDA) of the high dielectric constant layer 16 is required after the formation of the high dielectric constant layer 16 on the interfacial layer 13. The thermal processing or thermal treatment is necessary to densify or reduce imperfections such as charge traps in the high dielectric constant layer 16. Such charge traps result in electrical degradation of the semiconductor device 10. Therefore, by performing an anneal at a temperature having a value anywhere within a wide range from approximately two hundred up to or even above one thousand degrees Celsius, the composition of the high dielectric constant layer 16 is smoothed and the charge traps are minimized. However, if the depth of the high dielectric constant layer 16 is significantly less than 5 nanometers, annealing of the high dielectric constant layer 16 causes the silicon dioxide of the interfacial layer 14 to grow significantly. The increased thickness of the silicon dioxide therefore lowers the dielectric constant of the composite dielectric. We have discovered that the annealing has a minimal effect on the underlying silicon dioxide when the high dielectric constant layer 16 is formed with a thickness substantially in the range of 5 nanometers to 20 nanometers. Furthermore, the microstructure or crystallinity of some of the materials described herein as being used for the high dielectric constant layer 16 is thickness dependent and a thicker deposited layer is therefore advantageous. For example, the microstructure or crystallinity of hafnium oxide is thickness dependent. An additional advantage of forming the high dielectric constant layer 16 thicker is that a thicker high k gate dielectric film may have more desirable properties than an originally formed thinner film. In other words, there are preferred bulk film properties for thick films and the thick films can be isotropically etched to obtain thin films rather than to form thin films directly.
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Therefore, the interfacial layer 14 and the thin high dielectric constant layer 18 form a composite dielectric layer 19. By forming the composite dielectric layer 19 through a method wherein a much thicker high dielectric constant layer is initially created, an anneal to cure the high dielectric constant layer material may be performed without growing or modifying the underlying interfacial layer 14 substantially. After the annealing of the high dielectric constant layer 16 occurs, the high dielectric constant layer 16 is then etched to a desired depth to form a desired equivalent oxide thickness (EOT).
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By now it should be appreciated that there has been provided a semiconductor method for depositing a thin high dielectric constant layer while maintaining a thin interfacial layer in the form of interfacial layer 14. In one form there is provided herein a method for forming a semiconductor device. A semiconductor substrate is provided. An interfacial layer is formed over the semiconductor substrate. A dielectric layer is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. A gate electrode layer is formed over the thinned dielectric layer. In another form a thickness of the interfacial layer does not substantially change during the forming of the dielectric layer. In another form the forming of the dielectric layer uses at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), spin-on deposition, plating, electroless plating or oxidation of a metal or metal composites. In another form the interfacial layer has a thickness in a range of approximately 0.3 to 1.2 nanometers. In yet another form the thickness of the dielectric layer prior to thinning is at least approximately 5 nanometers. In yet another form the thickness of the dielectric layer prior to thinning is at least approximately 10 nanometers. In yet another form the thickness of the thinned dielectric layer is at most 3 nanometers. In yet another form the dielectric layer includes at least one of a metal oxide, a metal silicate, a metal aluminate, a metal oxynitride and a metal silicon oxynitride. In another form, during the forming of the dielectric layer, metal from the dielectric layer penetrates into at least a portion of the interfacial layer. In yet another form the thinned dielectric layer includes a polycrystalline metal oxide. In yet another form a thermal treatment is performed before or after the thinning the dielectric layer. In yet another form the interfacial layer is formed with at least one of a chemical oxide or a thermally grown oxide. In another form the interfacial layer is formed by thermally growing an oxide layer and etching the oxide layer to form the interfacial layer. In yet another form the interfacial layer includes an oxide of the substrate. In yet another form the interfacial layer includes the oxide of the substrate and a metal from the dielectric layer. In yet another form the thinning of the dielectric layer includes performing at least one of a wet etch or a dry etch. In yet another form the interfacial layer, the thinned dielectric layer, and the gate electrode layer are patterned to form a substantially completed semiconductor device.
In another form there is herein provided a method for forming a semiconductor device. A silicon substrate is provided. An interfacial layer is formed over the silicon substrate. A hafnium oxide layer is formed over the interfacial layer. The hafnium oxide layer is etched to thin the hafnium oxide layer. A gate electrode layer is formed over the thinned hafnium oxide layer. In another form a thickness of the interfacial layer does not substantially change during the forming the hafnium oxide. In another form prior to the forming of the hafnium oxide layer, the interfacial layer includes silicon dioxide and after the forming the hafnium oxide layer, the interfacial layer includes a metal silicate. In another form the hafnium oxide layer is a polycrystalline hafnium oxide layer. In another form the hafnium oxide layer is etched by using hydrochloric acid or phosphoric acid or can be removed by CMP. In another form prior to the etching of the hafnium oxide layer, the hafnium oxide layer has a thickness of at least approximately 5 nanometers, and after the etching the hafnium oxide layer, the thinned hafnium oxide layer has a thickness of at most approximately 3 nanometers. In yet another form the interfacial layer has a thickness of in a range of approximately 0.3 to 1.2 nanometers. In yet another form a thermal treatment is performed before or after the etching the dielectric layer. In another form the hafnium oxide layer is formed by using at least one of atomic layer deposition (ALD), Chemical Vapor Deposition (CVD), physical vapor deposition (PVD), spin-on and plating.
In yet another form there is provided a method for forming a semiconductor device by providing a semiconductor substrate and forming an interfacial layer over the semiconductor substrate. The interfacial layer has a thickness in a range of approximately 0.3 to 1.2 nanometers. A dielectric layer is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K) and a thickness of at least approximately 5 nanometers. The dielectric layer is thinned to a thickness of at most approximately 3 nanometers. A gate electrode layer is formed over the thinned dielectric layer. In one form the thickness of the dielectric layer prior to the thinning is at least approximately 10 nanometers. In another form the thickness of the dielectric layer prior to the thinning is at least approximately 20 nanometers. In yet another form a thickness of the interfacial layer does not substantially change during the forming of the dielectric layer. In yet another form the dielectric layer includes at least one of a metal oxide, a metal silicate, a metal oxynitride, a metal silicon oxynitride or a metal aluminate. In another form during the forming of the dielectric layer, metal from the dielectric layer penetrates into at least a portion of the interfacial layer. In yet another form the thinned dielectric layer is a polycrystalline metal oxide. In yet another form the interfacial layer is an oxide of the substrate. In another form after the formation of the dielectric layer, the interfacial layer includes the oxide of the substrate and a metal from the dielectric layer. In yet another form the thinning of the dielectric layer includes performing at least one of a wet etch or a dry etch.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the metal oxide layer may be implemented with hafnium doped with higher k materials such as titanium or lanthanum. Any multiple metal oxides may be used rather than a single metal oxide. Although a transistor structure is implemented in the illustrated form, other semiconductor structures such as a capacitor may be implemented. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms a or an, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
