Patent Application
20130037866
The present invention generally relates to a method of forming a semiconductor device and more particularly relates to a method of forming gates of a metal-oxide-semiconductor field-effect transistor (“MOSFET”).
In one common technique of MOSFET formation, a gate stack is deposited on a substrate. A dielectric spacer is then formed around a gate stack by first depositing a dielectric then selectively etching the dielectric using a reactive-ion etching (“RIE”) process. This process may then be repeated to add additional thickness of the spacer. This results in a spacer that is generally symmetrical about the gate. Furthermore, the process of depositing the dielectric may result in an uncontrolled, variable thickness of the gate spacer. Specifically, when numerous lines of gates are involved, an outer line of gates receives a spacer having a larger thickness than the other lines. This situation is typically undesirable, but could be advantageous if properly controlled. Lastly, the typical sequence of dielectric deposition and RIE process leads to a recess in the substrate. Said another way, the multiple RIE processes will consume silicon of the substrate in the active region of the MOSFET. This will lead to performance degradation of the MOSFET.
In some instances, it is desirable to form a transistor with a gate having an asymmetric dielectric gate spacer. In addition, it may be desirable to form multiple gates with different spacer thicknesses. It is further desirable to have minimal recessing of the silicon adjacent the spacers.
Moreover, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
In one aspect of the invention, a method is provided for forming a semiconductor device. The method includes providing a substrate and depositing a gate stack having a side periphery on the substrate. The method further includes depositing a first liner dielectric layer on the substrate and the gate stack. A first spacer dielectric layer is deposited on the first liner dielectric layer. The method also includes selectively etching the first spacer dielectric layer such that the first spacer dielectric layer remains adjacent at least a portion of the side periphery of the gate stack. A first resist mask is disposed on a first portion of the first spacer dielectric layer such that the first portion of the first spacer dielectric layer is protected by the resist mask and a second portion of the first spacer dielectric layer is not protected by the resist mask. The method further includes etching the first spacer dielectric layer such that the second portion is removed and the first portion remains.
In another aspect of the invention, a method is provided for forming a semiconductor device. The method includes providing a substrate and depositing first and second gate stacks on the substrate. Each gate stack has a side periphery. The method further includes depositing a first liner dielectric layer on the substrate and the gate stacks. A first spacer dielectric layer is deposited on the first liner dielectric layer. The method also includes selectively etching the first spacer dielectric layer such that the first spacer dielectric layer remains adjacent at least a portion of each of the side peripheries of the gate stacks. A first resist mask is disposed on the first spacer dielectric layer deposited on the first gate stack such that the first spacer dielectric layer adjacent the side periphery of the first gate stack is protected and the first spacer dielectric layer deposited on the second gate stack is not protected. The method further includes etching the first spacer dielectric layers such that the first spacer dielectric layer deposited on the second gate stack is removed.
The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and
The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention.
Referring to the Figures, wherein like numerals indicate like parts throughout the several views, a method of forming a semiconductor device 20 is shown and described herein. The semiconductor device 20 of the illustrated embodiment includes transistors 22, specifically metal-oxide-semiconductor field-effect transistors (MOSFETs). More specifically, the MOSFETs may be p-type and n-type MOSFETs as is typically found in a complementary metal-oxide-semiconductor (CMOS) device.
Referring to
Still referring to
The method also includes depositing a first liner dielectric layer 34 on the substrate 24 and the gate stack 26, as shown in
Referring now to
The method also includes selectively etching the first spacer dielectric layer 36. The etching is done with a high selectivity process, which prevents removal of the first liner dielectric layer 34. More specifically, in one embodiment, the selective etching of the first spacer dielectric layer 36 is performed with a reactive-ion etching (“RIE”) process. The etching results in the first spacer dielectric layer 36 remaining in place adjacent at least a portion of the side periphery 28 of the gate stack 26, as is shown in
Referring now to
To form an asymmetric gate, the first resist mask 38 covers only a portion of the gate stack 26. Said another way, the edge 40 of the first resist mask 38 is disposed atop the gate stack 26 such that part of the gate stack 26 is exposed by the void 42 and part of the gate stack 26 is protected by the first resist mask 38. As such, a first portion 44 of the first spacer dielectric layer 36 is protected by the first resist mask 38 and a second portion 46 of the first spacer dielectric layer 36 is not protected by the first resist mask 38.
The method also includes etching the first spacer dielectric layer 36 such that the second portion 46 is removed and the first portion 44 remains. In the illustrated embodiment, this etching is done with a wet etch process. That is, a chemical etchant is applied to device 20 which removes the first spacer dielectric layer 36 that is not protected by the first resist mask 38. As can be seen with reference to
The method may further include depositing a second liner dielectric layer 48, as shown in
Referring now to
The method may further include selectively etching the second spacer dielectric layer 50 such that the second spacer dielectric layer 50 remains adjacent at least a portion of the side periphery 28 of the gate stack 26, as shown in
Referring now to
The method may also include etching the second spacer dielectric layer 50 such that the second portion 60 is removed and the first portion 58 remains. In the illustrated embodiment, this etching is done with a wet etch process. That is, a chemical etchant is applied to device 20 which removes the second spacer dielectric layer 50 that is not protected by the second resist mask 52. As can be seen with reference to
The method also includes etching the liner dielectric layers 34, 48. If applying the second liner and spacer dielectric layers 48, 50 is not desired, this etching may occur after the etching of the first spacer dielectric layer 36 with the first resist mask 38. As such, only the first liner dielectric layer 24 would be etched, as the second liner dielectric layer 48 is not applied. Otherwise, this etching of both liner dielectric layers 34, 48 may occur after the etching of the second spacer dielectric layer 50 with the second resist mask 52, as is shown in
The methods described herein may be applied to form transistors 22 with gate stacks 26 having up to ten different dielectric thicknesses and configurations. Importantly, these transistors 22 may be formed in combination on a single device 20. Specifically, transistors 22 with four different symmetric dielectric thicknesses may be realized utilizing the methods described herein. These four different symmetric dielectric thicknesses include: (a) all four dielectric layers 34, 36, 48, 50 forming a sidewall spacer for the gate stack 26; (b) both liner dielectric layers 34, 48 and the first spacer dielectric layer 36 forming a sidewall spacer for the gate stack 26; (c) both liner dielectric layers 34, 48 and the second spacer dielectric layer 50 forming a sidewall spacer for the gate stack 26, and (d) both liner dielectric layers 34, 48 forming a sidewall spacer for the gate stack 26. Gate stacks 26 with symmetric dielectrics may be utilized in transistors 22 for standard logic circuits, low power logic circuits, dynamic random-access memory (“DRAM”) circuits, and high-voltage circuit applications. Particularly, these different types of circuits may be easily combined on one chip (not shown) with different spacer thicknesses.
Furthermore, transistors 22 with six different asymmetric spacer thicknesses may be realized utilizing the methods described herein in accordance with the following table:
The transistors 22 with asymmetric gate spacers may be utilized for coping with high voltages on the sources and drains. The transistors 22 with asymmetric gate spacers may also be used in conjunction with self-aligned contact etching processes. In these processes, enhanced protection against contact to gate 26 shorts is needed where standard thickness of gate spacers may result in such undesirable shorts.
While at least one exemplary embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.
