Patent Grant
8240031
The present invention pertains to high density decals and, more particularly, to a method of removably attaching a semiconductor chip to a printed wiring board using a high density decal.
Semiconductor devices (chips) are typically provided with a high density of electrical contacts on one surface, arranged in a patterned array with constant dimensions and small spacing or pitch between the centers of the contacts. The contacts may be pads or bumps.
Historically, in first level packaging the chips were mounted on a rigid carrier with matching electrical contacts, encapsulated and hermetically sealed in metal or plastic packages. The carrier redistributed the electrical contacts over a larger area and made it compatible for mounting on a printed circuit board (PCB) or printed wiring board (PWB) known as second level packaging. Conventionally the electrical connection between the chip and carrier in the first level package has been permanent by means of solder, wirebond and the like and not amenable to easy removal or reworking. The second level interconnection of the carrier to the PWB have similarly been permanent or at best difficult to rework via solder.
Conventional interconnection methods give rise to two problems. In the first instance, the mismatch in the thermal expansion coefficients of the chip substrate, usually silicon, and the carrier result in stress during the assembly process and also during operation of the device. Rigid carriers similarly acquire and retain residual stress during second level assembly. Such stress often leads to early failure of the electrical contacts either at the first or the second level interconnections.
One method of overcoming this deficiency has been to use additional reinforcing adhesive to provide mechanical support for the interconnections. A second method known in the art has been the use of flexible thin film carriers to accommodate the stress as disclosed in U.S. Pat. Nos. 5,207,585 to Byrnes et al. and 6,242,282 to Fillion et al. The '585 patent discloses a thin interface pellicle probe for making temporary or permanent interconnections to pads or bumps on a semiconductor device wherein the pads or bumps may be arranged in high density patterns incorporating an electrode for each pad or bump. The electrode has a raised portion thereon for penetrating the surface of the pad or bump to create sidewalls, providing a clean contact surface; and the electrode has a recessed surface to limit the penetration of the raised portion. The electrodes may be affixed to a thin flexible membrane to permit each contact to have independent movement over a limited distance and of a limited rotation.
The '282 patent discloses a method for packaging at least one circuit chip which includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on metallized portions of the second side and not on non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the circuit chip on the second side with at least one chip pad of the circuit chip being aligned with the chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the second side metallized portion and to the chip pad.
The second problem associated with rigid as well as flexible carriers is related to testing, burn-in, and removal/reworking of the interconnects. The devices require firm, reliable electrical/ohmic contacts with the carrier and PWB during testing and burn-in. However the process also demands easily detachable chip-to-carrier or carrier-to-PWB joints, should the device or the electrical interconnects be found defective. Conventional rework methods introduce additional thermal cycles on the assembly and often damage the device or the PWB.
Temporary interconnection techniques for test probes are the subject of U.S. Pat. Nos. 6,156,484 to Bassous et al. and 5,137,461 to Bindra et al. The '484 patent discloses a sculpted probe pad and a gray scale etching process for making arrays of such probe pads on a thin flexible interposer for testing the electrical integrity of microelectronic devices at terminal metallurgy. Also used in the etching process is a fixture for holding the substrate and a mask for one-step photolithographic exposure. The result is an array of test probes of preselected uniform topography, which make ohmic contact at all points to be tested simultaneously and nondestructively.
The '461 patent discloses a separable and reconnectable connection for electrical equipment that is suitable for miniaturization in which vertical interdigitating members integrally attached and protruding from a planar portion are accommodated to control damage in lateral displacement that occurs on mating with an opposite similar contact.
Although not disclosed in the aforementioned patents, test probes often require special jigs and fixtures to hold the joined pads at high pressures. As the density of the electrical contacts on devices progressively increases, the reliability of the ohmic contacts in the above cited probes decreases.
None of the cited references teaches a high density decal for removably attaching a device to a PWB which can optionally be removed and reworked, or permanently attached.
Accordingly it is one object of this invention to removably connect a chip to a printed wiring board using a high density decal wherein the decal redistributes the electrical contacts on the PWB.
It is another object of the invention to removably connect a chip to a printed wiring board using a high density decal wherein the removable interconnections are substantially stress-free.
It is yet another object of the invention to removably connect a chip to a printed wiring board using a high density decal wherein little or no force is employed in making the ohmic contact.
The term decal is used interchangeably with the terms pellicle, interposer, and carrier and is defined hereinbelow.
The terms removable and detachable are used interchangeably to mean easy separation by art-accepted means including mechanical, thermal, chemical and physical means, such as optical, acoustic and the like, with insignificant or no damage to the components being separated.
In accordance with the present invention, there is provided a chip attached to a high density decal and a method of detachably attaching the decal to a PWB. A flexible decal has fine-pitch pads on a first surface and pads of a wider pitch on a second surface, the fine pitch pads on the first surface designed to electrically connect to a semiconductor device, the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like, and the pads on the first surface being conductively wired to the pads on the second surface through one or more insulating levels in the flexible substrate.
A complete understanding of the present invention may be obtained by reference to the accompanying drawings, when considered in conjunction with the subsequent detailed description, in which:
Generally speaking, the present invention is directed to a method of removably forming an electrical interconnection between an integrated circuit chip and a PWB using a flexible decal.
As shown in
As shown in
In another conventional technique, pads 101 and 202 are joined together by a solder bump 301 (
The instant invention overcomes these shortcomings by forming a temporary detachable bond for testing and burn-in followed by a process of making a permanent bond.
In one embodiment the solder-bump 301 (
The ECA may comprise electrically conductive particles, preferably metal particles, disposed in a thermoplastic epoxy. Analogous to the soldering operations, the electrical interconnections are made using ECA bumps in the conventional manner. If initial testing indicates a defective die (chip) or decal, the decal can be removed without damage to the chip or the PWB by softening the epoxy. Generally speaking, these are low temperature operations compared to soldering and are relatively stress free.
In another embodiment, the epoxy of the ECA may be amenable to two-stage curing. For the initial testing phase, the epoxy may be B-cured, in which stage it is easily removable by dissolution in a solvent or via other known techniques.
Thermosetting resin blends in the ECA may permit low-temperature detachable thermoplastic connections made as described above with a second stage curing of the thermoset-resin at a higher temperature to obtain a permanent electrical interconnection.
In yet another embodiment, the two-stage curing may comprise UV-curing of one UV-curable resin in the blend in the first stage; this may be followed by thermal curing the resin to form a durable interconnection.
Significantly, the ECA as used in this embodiment includes a metal component including nano-particles. Metals which may form the nano-particles include copper, silver, gold, silver-coated copper, gold-coated copper, and alloys thereof. In one embodiment of the invention, an ECA having silver nano-particles may be used. ECA may include micro-particles of metal (including silver), micro-particles of solder, and, in some situations, the addition of a conducting polymer and, even further, the addition of an organic composition. An important aspect of this invention is that the ECA particles will not melt during B-curing, but will melt during the final, full curing process. Suitable additional metal, including solder, for use in the compositions taught herein may be referred to as low melting point (LMP) metallurgies, and are mixed with the primary metal particles (e.g., silver or a silver-copper mixture). These LMP metallurgies include tin-lead, bismuth-tin, bismuth-tin-iron, tin, tin-silver, tin-gold, tin-silver-zinc, tin-silver-zinc-copper, tin-bismuth-silver, tin-copper, tin-copper-silver, tin-indium-silver, tin-antimony, tin-zinc, tin-zinc-indium, copper-based solders, and alloys thereof.
With reference to
Still further, the compositions herein may include what is defined as mixture of solder where one solder will melt during at low temperature reflow but both solder will reflow melt only during final reflow process. One example is a mixture of tin-bismuth and tin-lead solder. At a low temperature reflow process, only tin-bismuth will melt and tin-lead will act as a conducting filler. But for the final joining process, high temperature reflow occurs where the tin-lead and tin-bismuth both will melt. It is also possible to use multiple low and high temperature solder in the mixture. One example is tin-bismuth as a low temperature solder and tin-lead or tin silver copper (SAC) as the high temperature solder.
In another variation of the above embodiment, as shown in
Since other modifications and changes varied to fit particular operating requirements and environments will be apparent to those skilled in the art, this invention is not considered limited to the example chosen for purposes of this disclosure, and covers all changes and modifications which does not constitute departures from the true spirit and scope of this invention.
Having thus described the invention, what is desired to be protected by Letters Patent is presented in the subsequently appended claims.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5137461 | Bindra et al. | Aug 1992 | A |
| 5207585 | Byrnes et al. | May 1993 | A |
| 5949654 | Fukuoka | Sep 1999 | A |
| 6156484 | Bassous et al. | Dec 2000 | A |
| 6242282 | Fillion et al. | Jun 2001 | B1 |
| 6370013 | Iino et al. | Apr 2002 | B1 |
| 7594317 | Nakamura | Sep 2009 | B2 |
| 20070025092 | Lee et al. | Feb 2007 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20120015532 A1 | Jan 2012 | US |
