Claims
- 1. A method of fabricating a semiconductor device having a multilayer interconnection structure, the method comprising:
- forming a first insulation layer on a semiconductor substrate;
- forming an etching prevention film on said first insulation layer;
- forming a first opening through the etching prevention film and through the first insulation layer;
- forming a first interconnection layer in said first opening;
- forming a second insulation layer on said etching prevention film and said first interconnection layer integrally without interposing any etching prevention film therein;
- forming a hole of a pattern identical with a second opening to be formed later in said second insulation layer from an upper surface of the second insulation layer to a depth by etching;
- forming said second opening for a via hole reaching the upper surface of said first interconnection layer and a third opening having a diameter larger than that of said second opening and being continuous with said second opening in said second insulation layer, by etching a region of said second insulation layer containing the pattern identical with said second opening so as to make the bottom of the hole of the pattern identical with said second opening reach the upper surface of said first interconnection layer; and
- forming a second interconnection layer in said second and third openings so that the bottom of said second interconnection layer directly contacts the upper surface of said first interconnection layer.
- 2. A method of fabricating a semiconductor device in accordance with claim 1, wherein
- said etching prevention film is a polyphenylsilsesquioxane film (PPSQ film).
- 3. A method of fabricating a semiconductor device in accordance with claim 1, wherein
- the second interconnection layer is formed on and in contact with said first interconnection layer and said etching prevention film.
- 4. The method of fabricating a semiconductor device according to claim 1, wherein the etching prevention film is in direct contact with a side surface of the first interconnection layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
4-166179 |
Jun 1992 |
JPX |
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Parent Case Info
This application is a division of application Ser. No. 08/575,842 filed Dec. 21, 1995, now U.S. Pat. No. 5,598,027, which is a continuation of application Ser. No. 08/037,133 filed Mar. 25, 1993, now abandoned.
US Referenced Citations (31)
Foreign Referenced Citations (7)
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Date |
Country |
21-818-A1 |
Jan 1981 |
EPX |
46-525-A2 |
Mar 1982 |
EPX |
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Feb 1984 |
DEX |
61-152040 |
Jul 1986 |
JPX |
62-112353 |
May 1987 |
JPX |
2-156537 |
Jun 1990 |
JPX |
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Sep 1991 |
JPX |
Non-Patent Literature Citations (2)
Entry |
"A Four-Level-Metal Fully Planarized Interconnect Technology for Dense High Performance Logic and SRAM Applications," Ronald R. Uttecht et al., VMIC Conference, Jun. 11-12, 1991, pp. 20-26. |
Kaanta et al., "Dual Damascene: A ULSI Wiring Technology," 1991 VMIC Conference, Jun. 11-12, 1991 pp. 144-152. |
Divisions (1)
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Number |
Date |
Country |
Parent |
575842 |
Dec 1995 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
037133 |
Mar 1993 |
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