Claims
- 1. A method for fabrication of a vertical field effect transistor, comprising the steps of:
- (a) providing a substrate of a first semiconductor material and first conductivity type with a first epitaxial layer of a second semiconductor material and said first conductivity type on said substrate, said second semiconductor material being different from said first semiconductor material;
- (b) forming a plurality of gate fingers of said second semiconductor material and of a second conductivity type on said first epitaxial layer; and
- (c) forming a second epitaxial layer on said gate fingers and said first epitaxial layer, said second epitaxial layer of said second semiconductor material and said first conductivity type and forming channels between adjacent ones of said gate fingers and a planar source over said gate fingers and said channels.
- 2. The method of claim 1, wherein:
- (a) said first semiconductor material is germanium; and
- (b) said second semiconductor material is gallium arsenide.
- 3. The method of claim 1, wherein:
- (a) said first epitaxial layer includes a first sublayer on said substrate and a second sublayer abutting said gate fingers, wherein said first sublayer is more heavily doped than said second sublayer.
- 4. The method of claim 3, wherein:
- (a) said source is more heavily doped than said first sublayer.
- 5. The method of claim 1, wherein:
- (a) said substrate has a crystal orientation of (100) .+-.0.5.degree..
- 6. The method of claim 1, wherein:
- (a) said step (b) of claim 1 includes removing portions of a third epitaxial layer on said first epitaxial layer.
CROSS-REFERENCE TO RELATED APPLICATIONS
This is a divisional of application Ser. No. 08/323,959, filed Oct. 17, 1994, now abandoned, which is a continuation-in-part of application Ser. No. 08/159,353, filed Nov. 29, 1993, now U.S. Pat. No. 5,554,561. The following applications contain subject matter related to the present application and are assigned to the assignee of the present application: application Ser. Nos. 07/876,252, filed Apr. 30, 1992; 08/036,584, filed Mar. 24, 1993; 08/056,682, filed Apr. 30, 1993; 08/055,421, filed Apr. 30, 1993; 08/056,681, filed Apr. 30, 1993; and 08/158,673, filed Nov. 29, 1993.
US Referenced Citations (9)
Non-Patent Literature Citations (2)
Entry |
Alferov et al., "Buried-gate gallium arsenide vertical field-effect transistor," Sov. Tech. Phys. Lett 12(2), Feb. 1986, pp. 77-78. |
Ghandi, "VLSI Fabrication Principles", J. Wiley & Sons, 1983, pp. 12-14, 213-217. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
323959 |
Oct 1994 |
|
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
159353 |
Nov 1993 |
|