Claims
- 1. A process for producing an integrated circuit structure comprising the steps of:
- (a) producing a conductive layer over a substrate and a first insulating layer over said conductive layer such that said conductive layer has a first lateral dimension and said insulating layer has a second lateral dimension less than said first lateral dimension;
- (b) producing a second insulating layer over said first insulating layer and said conductive layer; and
- (c) producing a planarizing layer over said second insulating layer.
- 2. A process as recited in claim 1 wherein step (a) includes the steps of:
- depositing said conductive layer over said substrate;
- depositing said first insulating layer over said conductive layer;
- masking at least one portion of said first insulating layer; and
- etching said first insulating layer and said conductive layer such that said second lateral dimension is less than said first lateral dimension.
- 3. A process as recited in claim 2 wherein said step of etching said first insulating layer and said conductive layer comprises the steps of:
- etching said first insulating layer with a plasma formed, at least in part, from SF.sub.6.
- 4. A process as recited in claim 3 wherein said plasma is further formed, at least in part, from CHF.sub.3.
- 5. A process as recited in claim 4 wherein said masking step includes masking with a resist material, and wherein said plasma is further formed, at least in part, from said resist material.
- 6. A process as recited in claim 4 wherein said etching of said first insulating layer forms sidewalls, and wherein the chemistry of the etching process causes a lateral build-up of a material derived from said plasma on said sidewalls.
- 7. A process as recited in claim 6 wherein said material is a polymer including carbon and sulfur derived from said plasma.
- 8. A process as recited in claim 7 wherein said step of etching said first insulating layer and said conductive layer comprises the step of removing said resist and said polymer after etching said conductive layer.
- 9. A process for making an integrated circuit structure comprising the steps of:
- providing a semiconductor substrate;
- forming a conductive layer over said substrate;
- forming an oxide layer over said conductive layer;
- masking said oxide layer with a resist material;
- etching said oxide layer with a plasma formed, at least in part, from SF.sub.6 and CHF.sub.3 such that, as said oxide layer is etched, sidewalls are formed on said oxide layer including a polymer deposited from said plasma;
- etching said conductive layer using said oxide layer and said sidewalls as a mask; and
- removing said resist and said polymer from said oxide layer,
- whereby a dimension of said etched oxide layer is less than a corresponding dimension of said etched conductive layer.
- 10. A process as recited in claim 9 further comprising the step of forming a blanket of an inter-layer dielectric over said etched oxide layer and said etched conductive layer.
- 11. A process as recited in claim 10 further comprising the step of forming a planarization layer over said inter-layer dielectric.
- 12. A process as recited in claim 11, wherein said inter-layer dielectric is an oxide layer, and said planarization layer is a spin-on-glass material.
- 13. A process as recited in claim 9 wherein the step of etching said oxide layer takes an amount of time in the range of about 30 to 300 seconds.
- 14. A process as recited in claim 13 wherein the step of etching said oxide layer takes an amount of time in the range of about 45 to 120 seconds.
- 15. A process as recited in claim 13 wherein the step of etching said oxide layer takes an amount of time in the range of about 65 to 75 seconds.
- 16. A process as recited in claim 15 wherein the step of etching said oxide layer includes the steps of:
- preparing an etching chamber with a chemistry required for said plasma, said preparing taking about 15 seconds;
- performing a bulk etching step for about 20 seconds; and
- performing an overetch step for about 10 seconds.
- 17. A process as recited in claim 9 wherein said CHF.sub.3 is provided by a gaseous flow of CHF.sub.3 into a chamber enclosing said substrate at a CHF.sub.3 flowrate in the range of about 80 to 800 standard cubic centimeters per minute and said SF.sub.6 is provided by a gaseous flow of SF.sub.6 into said chamber at a SF.sub.6 flowrate in the range of about 8 to 80 standard cubic centimeters per minute.
- 18. A process as recited in claim 17 wherein said CHF.sub.3 flowrate is in the range of about 180 to 190 standard cubic centimeters per minute and said SF.sub.6 flowrate is in the range of about 14 to 16 standard cubic centimeters per minute.
- 19. A process as recited in claim 18 wherein said CHF.sub.3 flowrate is about 185 standard cubic centimeters per minute and said SF.sub.6 flowrate is about 15 standard cubic centimeters per minute.
Parent Case Info
This is a divisional of application Ser. No. 08/561,768 filed on Nov. 22, 1995, now U.S. Pat. No. 5,640,038.
US Referenced Citations (16)
Foreign Referenced Citations (2)
Number |
Date |
Country |
3-171671 |
Jul 1991 |
JPX |
2251722A |
Jul 1992 |
GBX |
Non-Patent Literature Citations (1)
Entry |
Wolf et al., Silicon Processing For The VLSI era, vol. l, Lattice Press, 1986, pp. 545-557. |
Divisions (1)
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Number |
Date |
Country |
Parent |
561768 |
Nov 1995 |
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