Claims
- 1. A method of forming an interconnect structure in a semiconductor device having improved electromigration resistance, comprising:
- forming two conductive lines over a substrate, of the semiconductor device the two conductive lines being isolated from each other by a dielectric layer;
- forming a contact/via array within the dielectric layer to electrically connect the two conductive lines, wherein the contact/via array comprises a plurality of contact/via columns and a plurality of contact/via rows made up of a plurality of contacts/vias; and
- respectively forming parallel load resistors having various resistance within the two conductive lines corresponding to each of the contact/via columns and the contact/via rows to displace a part of each two conductive lines close to the contact/via array, so that the current paths from one conductive line to the other conductive line through the contact/vias and the load resistors corresponding to the two conductive lines have identical equivalent resistance.
- 2. The method according to claim 1, wherein the load resistors comprise a conductive layer and a plurality of slots with various lengths, the slots being filled with dielectric material in the conductive layer.
- 3. A method of forming an interconnect structure in a semiconductor device having improved electromigration resistance, comprising:
- forming a first and a second conductive line over a substrate, of the semiconductor device the two conductive lines being isolated by a dielectric layer;
- forming a contact/via array to electrically connect the first and the second conductive lines, wherein the contact/via array comprises a plurality of contact/via columns and a plurality of contact/via rows made up of a plurality of contacts/vias; and
- respectively inserting a first and parallel load resistors having various resistances into the first and second conductive lines close to the contact/via array corresponding to each of the contact/via columns and the contact/via rows, so that an equivalent resistance composed of the first conductive line, the second conductive line, each first load resistor, each contact/via corresponding to each first load resistor and each second load resistor corresponding to each contact/via is identical.
- 4. The method according to claim 1, wherein the load resistors comprise a conductive layer and a plurality of slots with various lengths, the slots being filled with dielectric material in the conductive layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
87107992 |
May 1998 |
TWX |
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CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation in part (CIP) of U.S. patent application Ser. No. 09/135,453, filed Aug. 17, 1998, which claimed the priority benefit of Taiwan application serial no. 87107992, filed May 22, 1998, the full disclosure of which is incorporated herein by reference.
US Referenced Citations (7)
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
135453 |
Aug 1998 |
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