Patent Application
20170338180
The present disclosure relates to semiconductor devices having electrically programmable fuses (e-fuse). In particular, the present disclosure relates to e-fuse designs for semiconductor devices in advanced technology nodes.
The e-fuse plays an important role in device programming. In computing, e-fuses are used as a means to allow for the dynamic, real-time reprogramming of computer chips. Speaking abstractly, computer logic is generally “etched” or “hard-coded” onto a silicon chip and cannot be changed after the chip has been manufactured. By utilizing an e-fuse, or a number of individual e-fuses, a chip manufacturer can change some aspects of the circuits on a chip. If a certain sub-system fails, or is taking too long to respond, or is consuming too much power, the chip can instantly change its behavior by blowing an e-fuse. Programming of an e-fuse is typically accomplished by forcing a large electrical current through the e-fuse. This high current is intended to break or rupture a portion of the e-fuse structure, which results in an “open” electrical path. In some applications, lasers are used to blow e-fuses. Fuses are frequently used in integrated circuits to program redundant elements or to replace identical defective elements. Further, e-fuses can be used to store die identification or other such information, or to adjust the speed of a circuit by adjusting the resistance of the current path. Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower power consumption relative to previous device generations. This drive applies to the manufacture and use of e-fuses as well.
The structure of an e-fuse utilizes electro-migration to change the resistance of a device. In particular, dynamic real-time reprogramming of computer chips is possible with e-fuses. By utilizing e-fuses, the circuits on a chip can change while in operation by blowing an e-fuse to change the chip's behavior. An e-fuse is typically narrow and thin film in design to facilitate blowing. With current designs it is difficult to achieve a programming window with good yield due to the narrow window blowing of fuse. A particular problem with a middle of the line (MOL) e-fuse is achieving a good yield at a low voltage operation.
A need therefore exists for methodology enabling manufacture of improved e-fuse design that provides enhanced performance and minimizes area design requirements and the resulting device.
An aspect of the present disclosure is to provide a MOL e-fuse in the smallest area design with source/drain contact (CA) and gate contact (CB) placement to improve yield. Another aspect of the present disclosure is to utilize existing integration schemes and photolithographic layers to enable efficient layout while providing low operation voltage designs.
Another aspect of the present disclosure is to provide an e-fuse that performs as a heat sink to provide contact and heat dissipation with underneath active devices. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the various embodiments of the e-fuses disclosed herein may be employed on any type of integrated circuit product, including, but not limited to, logic devices, memory devices, ASICs, so-called system-on-chip products, etc.
Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
According to the present disclosure, some technical effects may be achieved in part by a method including forming a gate electrode (PC); forming at least one CB over the PC; forming at least one CA; and forming an e-fuse including a resistor metal (RM) between at least one CB and an equal number of CAs to dissipate heat generated by the PC.
Aspects of the present disclosure include connecting the at least one CA to a metal 1 landing or via landing, wherein the e-fuse is a middle of the line (MOL) e-fuse. Other aspects include forming the PC in an anode region and the CA in a cathode region. Further aspects include forming the e-fuse with a line width that decreases in a direction towards the cathode region. Other aspects include forming a second PC on a side of the at least one CA remote from the first PC; forming at least one second CB on the second PC; and forming a second e-fuse including a RM between the at least one second CB and the CAs to dissipate heat generated by the PC. Additional aspects include forming the CA over a trench silicide contact (TS). Yet further aspects include forming the PC in a cathode region and the CA in an anode region. Other aspects include forming the e-fuse with a line width that decreases in a direction towards the cathode region. Further aspects include forming a second PC on a side of the at least one CA remote from the first PC; forming at least one second CB on the second PC; and forming a second e-fuse including a RM between the at least one second CB and the CAs to dissipate heat generated by the PC.
Another aspect of the present disclosure is a device including a PC; at least one CB formed over the PC; at least one CA; and an e-fuse including a RM formed between at least one CB and an equal number of CAs to dissipate heat generated by the PC.
Aspects include the at least one CA being connected to a metal 1 landing or via landing and wherein the e-fuse is a middle of the line (MOL) e-fuse. Other aspects include the PC being formed in an anode region and the CA in a cathode region. Further aspects include the e-fuse being formed with a line width that decreases in a direction towards the cathode region. Additional aspects include a second PC formed on a side of the at least one CA remote from the first PC; at least one second CB formed on the second PC; and a second e-fuse including a RM formed between the at least one second CB and the CAs to dissipate heat generated by the PC. Other aspects include the CA being formed over a TS. Yet further aspects include the PC being formed in a cathode region and the CA in an anode region. Other aspects include the e-fuse being formed with a line width that decreases in a direction towards the cathode region. Additional aspects include a second PC formed on a side of the at least one CA remote from the first PC; at least one second CB formed on the second PC; and a second e-fuse including a RM formed between the at least one second CB and the CAs to dissipate heat generated by the PC.
According to the present disclosure, some technical effects may be achieved in part by a method including forming a first PC and a second PC separated from the first PC; forming at least one first CB over the first PC; forming at least one second CB over the second PC; and forming an e-fuse including a RM between at least one first CB and an equal number of second CBs to dissipate heat generated by the first PC and second PC.
Aspects include forming the first PC in a cathode region; forming the second PC in an anode region; and forming the e-fuse with a line width that decreases in width in a direction towards the cathode region. Other aspects include forming a third PC on a side of the second PC remote from the first PC; forming at least one third CB over the third PC; and forming a second e-fuse including a RM between the at least one second CB and an equal number of third CBs to dissipate heat generated by the first PC and second PC.
Another aspect of the present disclosure is a device including a first PC and a second PC separated from the first PC; at least one first CB formed over the first PC; at least one second CB formed over the second PC; and an e-fuse including a RM formed between at least one first CB and an equal number of second CBs to dissipate heat generated by the first PC and second PC.
Aspects include the first PC being formed in a cathode region; the second PC being formed in an anode region; and the e-fuse being formed with a line width that decreases in width in a direction towards the cathode region. Other aspects include a third PC formed on a side of the second PC remote from the first PC; at least one third CB formed over the third PC; and a second e-fuse including a RM formed between the at least one second CB and an equal number of third CBs to dissipate heat generated by the first PC and second PC.
Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
The present disclosure addresses and solves the current problem of e-fuse designs having insufficient performance and unsatisfactory area requirements. In accordance with embodiments of the present disclosure, an e-fuse is provided that improves performance, meets area design requirements, and provides sufficient heat dissipation from active devices.
Methodology in accordance with embodiments of the present disclosure includes forming a PC; forming at least one CB over the PC; forming at least one CA; and forming an e-fuse including a RM between at least one CB and an equal number of CAs to dissipate heat generated by the PC.
Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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The e-fuse 107 is positioned closer to the PC 101 and supports smaller arrays and supports a low voltage operation (i.e., no voltage drop due to BEOL and VIA resistances). The vertically positioned e-fuse 107 eliminates BEOL interconnect congestion. A BEOL e-fuse in a 14 nm technology node can result in an e-fuse space reduction of 74 to 80%. A MOL e-fuse in a 14 nm technology node can result in an e-fuse space reduction of 85% to 89%.
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The bottom bias e-fuse design eliminates BEOL metallization interconnect to the e-fuse. The area above an e-fuse can be used for BEOL routing to other devices. The e-fuse can further enable placement of an e-fuse in locations other than the die periphery.
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The embodiments of the present disclosure can achieve several technical effects, including providing a heat dissipation through a PC wire. Other technical effects include enabling low-voltage e-fuse operation by eliminating voltage drop due to BEOL and via resistances. Additional technical effects include e-fuse placement closer to field effect transistors (FETs) and subsequently supporting usage in smaller arrays. The e-fuse can be used as a repair fuse to support product sort yield enhancement. Bottom bias/double bottom bias e-fuse designs can be used for die repair, to support improving product yields. Double e-fuse configuration increases the number of fuses available in a reduced area. Other technical effects include reducing BEOL interconnect congestion, enabling BEOL wiring designs over an e-fuse area. Existing integration schemes of 14 nm and 7 nm technology nodes, for example, can be leveraged. The present disclosure enjoys industrial applicability in any of various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, particularly for advanced technology nodes.
In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
