Claims
- 1. A method of manufacturing a semiconductor device having a single crystal pn junction formed in a Group II-VI compound semiconductor crystal, comprising:
- growing a Group II-VI compound semiconductor crystal substrate having n type conductivity from a melt of a crystal-constituting Group VI elemeht other than Te and a Group II element;
- forming a temperature difference in said melt by establishing a higher temperature zone in the upper region of the melt and a lower temperature zone in the lower region of the melt while holding the temperatures of the two zones constant and while constantly applying a vapor pressure of said Group VI element onto said melt throughout the growth of the crystal; and
- forming, on said n type Group II-VI compound semiconductor crystal substrate, a semiconductor region of p type conductivity by diffusing an acceptor impurity into said n type Group II-VI compound semiconductor crystal under a predetermined vapor pressure of the crystal-constituting Group VI element.
- 2. A method according to claim 1, wherein:
- said acceptor impurity is one having a diffusion coefficient greater than of vacancy produced in said crystal during doping of said impurity, by diffusion, into said crystal.
- 3. A method according to claim 1, wherein:
- said n type Group II-VI compound semiconductor crystal substrate is ZnSe;
- said melt is Se and serves as a solvent; and
- said vapor of the crystal-constituting Group VI element is that of Se.
- 4. A method according to claim 3, wherein: the diffusion is conducted at a temperature lower than 600.degree. C. under a vapor pressure of 0.1 Torr or more of Se, and said impurity is selected from gold and silver.
- 5. A method according to claim 1, wherein:
- said n type Group II-VI compound semiconductor crystal substrate is ZnSe;
- said melt is Se and serves as a solvent;
- said vapor of the crystal-constituting element is that of Se; and
- said acceptor impurity is gold.
- 6. A method according to claim 5, wherein:
- the diffusion of gold is conducted at a temperature ranging from 400.degree. C. to 300.degree. C.
- 7. A method according to claim 1, wherein:
- said temperature difference in said melt is about 40.degree. C., and the temperature of the vapor portion of said melt is about from 950.degree. C. to 990.degree. C.
- 8. A method of manufacturing a semiconductor device having a single crystal pn junction formed in a Group II-VI compound semiconductor crystal comprising:
- growing a Group II-VI compound semiconductor crystal substrate having n-type conductivity from the melt of the crystal-constituting Group VI element except Te, forming a temperature difference in said melt by establishing a higher temperature zone in the upper region of the melt and a lower temperature zone in the lower region of the melt while holding the temperature of the two zones constant and while constantly applying a vapor pressure of said Group VI element onto said melt throughout the growth of the crystal;
- forming, on said n-type Group II-VI compound semiconductor crystal substrate, a semiconductor region of p type conductivity by relying on liquid-phase epitaxial growth technique from the melt of the crystal-constituting Group VI element excepting Te; and
- forming a temperature difference in said melt while holding each portion of said melt at a constant temperature, and constantly applying a vapor pressure of said Group VI element onto said melt throughout the growth of the crystal.
- 9. A method according to claim 8, wherein:
- said Group II-VI compound semiconductor crystal is ZnSe and said melt is Se serving as the solvent, and said vapor of the crystal-constituting Group VI element is that of Se.
- 10. A method according to claim 9, wherein:
- said Group II-VI compound semiconductor crystal substrate is grown at a temperature of about 40.degree. C., and the upper portion of said melt is held at a temperature difference of about from 950.degree. C. to 990.degree. C.
Priority Claims (1)
Number |
Date |
Country |
Kind |
55-79805 |
May 1980 |
JPX |
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CROSS REFERENCE TO RELATED APPLICATION
This is a continuation-in-part of my copending application Ser. No. 628,974 filed July 10, 1984, which in turn is a continuation of my co-pending application Ser. No. 266,042 filed May 21, 1981 and now abandoned.
US Referenced Citations (10)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2107518 |
Apr 1983 |
GBX |
Non-Patent Literature Citations (2)
Entry |
Washiyama et al, Electronic Materials EFM-78-12, The Institute of Electrical Engineers of Japan, Tokyo, Japan, Nov. 29, 1978, pp. 1-9, (translated). |
Hamilton, P. M., SCP and Solid State Technology, "Advances in III-V and III-VI Semiconductor Compounds", Jun. 1964, pp. 15-19. |
Continuations (1)
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Number |
Date |
Country |
Parent |
266042 |
May 1981 |
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Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
628974 |
Jul 1984 |
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