METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

A method of manufacturing a semiconductor device is provided. The method includes: forming a first structure on a first wafer; forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process; bonding the first ones of the second chip regions with the first wafer; separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process; bonding the second ones of the second chip regions with the first wafer, and separating the bonded first and second wafers by a third dicing process.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No. 10-2022-0143540, filed on Nov. 1, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in their entirety.

BACKGROUND

1 Field

Example embodiments relate to a method of manufacturing a semiconductor device.

2. Related Art

An electronic system requiring data storage needs a high capacity semiconductor device that may store high capacity data. Methods of increasing the data storage capacity of the semiconductor device have been studied. For example, a semiconductor device including memory cells that may be three-dimensionally stacked has been suggested.

As the number of memory cells stacked in a vertical direction increases, a substrate on which the semiconductor device is formed may be bent, and the electric characteristics of the semiconductor device may be deteriorated.

SUMMARY

Example embodiments provide a method of manufacturing a semiconductor device having improved characteristics.

According to an aspect of an example embodiment, a method of manufacturing a semiconductor device includes: forming a first structure on a first wafer, forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process; bonding the first ones of the second chip regions with the first wafer, separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process; bonding the second ones of the second chip regions with the first wafer, and separating the bonded first and second wafers by a third dicing process.

According to an aspect of an example embodiment, a method of manufacturing a semiconductor device includes: forming a first structure on a first wafer including first chip regions, a first scribe lane region surrounding the first chip regions, and a first bonding pattern in each of the first chip regions, the first bonding pattern including a metal; forming a second structure on a second wafer including second chip regions, a second scribe lane region surrounding the second chip regions, and a second bonding pattern in each of the second chip regions, the second bonding pattern including a metal; after separating second ones of the second chip regions in a first portion of the second wafer, bonding the second ones of the second chip regions with corresponding first ones of the first chip regions of the first wafer such that the second bonding pattern contacts the first bonding pattern; after separating fourth ones of the second chip regions in a second portion of the second wafer, bonding the fourth ones of the second chip regions with corresponding third ones of the first chip regions of the first wafer such that the second bonding pattern contacts the first bonding pattern; and separating the bonded first and second wafers by a dicing process.

According to an aspect of an example embodiment, a method of manufacturing a semiconductor device includes: forming a first structure on a first wafer including first chip regions and a first scribe lane region surrounding the first chip regions; forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; forming a third structure on a third wafer including third chip regions and a third scribe lane region surrounding the third chip regions; after separating second ones of the second chip regions in a first portion of the second wafer, bonding the second ones of the second chip regions with corresponding first ones of the first chip regions of the first wafer, after separating fourth ones of the second chip regions in a second portion of the second wafer, bonding the fourth ones of the second chip regions with corresponding third ones of the first chip regions of the first wafer, after separating sixth ones of the third chip regions in a first portion of the third wafer, bonding the sixth ones of the third chip regions with corresponding fifth ones of the second chip regions of the second wafer; after separating eighth ones of the third chip regions in a second portion of the third wafer, bonding the eighth ones of the third chip regions with corresponding seventh ones of the second chip regions of the second wafer; and separating the bonded first, second and third wafers by a dicing process.

According to an aspect of an example embodiment, a method of manufacturing a semiconductor device includes: forming a memory channel structure on a first wafer including first chip regions and a first scribe lane region, the memory channel structure extending in a vertical direction substantially perpendicular to an upper surface of the first wafer; forming a gate electrode structure including gate electrodes spaced apart from each other in the vertical direction on the first wafer, each of the gate electrodes surrounding the memory channel structure; forming a transistor on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; forming a wiring on the second wafer that is electrically connected to the transistor; after separating first ones of the second chip regions in a first portion of the second wafer, bonding the first ones of the second chip regions with the first wafer, after separating second ones of the second chip regions in a second portion of the second wafer, bonding the second ones of the second chip regions with the first wafer; and separating the bonded first and second wafers by a dicing process.

According to an aspect of an example embodiment, a method of manufacturing a semiconductor device includes: forming a logic device on a first wafer including first chip regions and a first scribe lane region; forming elements on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions, the elements being configured to convert electronic signals into voltage signals; forming pixels of an image sensor on a third wafer including third chip regions and a third scribe lane region surrounding the third chip regions; bonding the third wafer with the second wafer; after separating first ones of the first chip regions in a first portion of the first wafer, bonding the first ones of the first chip regions with the second wafer; after separating second ones of the first chip regions in a second portion of the first wafer, bonding the second ones of the first chip regions with the second wafer, and separating the bonded first, second and third wafers by a dicing process.

In methods of manufacturing according to example embodiments misalignment may not occur between the structures, the semiconductor device may have enhanced electric characteristics.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1 to 28 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with example embodiments.

FIGS. 29A, 29B and 29C illustrate plan views illustrating a shape of the first portion 900 of the second substrate 700 separated from the second substrate 700 by the first dicing process in accordance with example embodiments.

FIGS. 30 to 32 includes plan views illustrating positions and layouts of the first portion 900 of the second substrate 700 separated from the second substrate 700 by the first dicing process in accordance with example embodiments.

FIGS. 33 to 52 are plan views and cross-sectional views illustrating a method of manufacturing a CMOS image sensor (CIS) in accordance with example embodiments.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device, a method for manufacturing the same, and a mass data storage system including the semiconductor device in accordance with example embodiments will be described in detail with reference to the accompanying drawings. It will be understood that, although the terms “first,” “second,” and/or “third” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Each example embodiment provided in the following description is not excluded from being associated with one or more features of another example or another example embodiment also provided herein or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. By contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression, “at least one of a, b, and c,” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It will be also understood that, even if a certain step or operation of manufacturing an apparatus or structure is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

As used herein, a vertical direction substantially perpendicular to an upper surface of a substrate may be referred to as a first direction D1, and two directions crossing each other among horizontal directions substantially parallel to the upper surface of the substrate may be referred to as second and third directions D2 and D3, respectively. In example embodiments, the second and third directions may be substantially perpendicular to each other.

FIGS. 1 to 28 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device, for example, a vertical channel NAND flash memory device in accordance with example embodiments.

Particularly, FIGS. 1-3, 6, 9, 14, 19-20, 23 and 26-28 are the plan views, FIGS. 4, 7, 10-13, 15, 17 and 24 are cross-sectional views taken along lines A-A′ of corresponding plan views, respectively, and FIGS. 5, 8, 16, 18 and 25 are cross-sectional views taken along lines B-B′ of corresponding plan views, respectively, and FIGS. 21 and 22 are cross-sectional views taken along lines C-C′ of corresponding plan views, respectively.

FIG. 2 is an enlarged plan view of region X of FIG. 1, and FIG. 20 is an enlarged plan view of region Z of FIG. 19. FIGS. 3 to 18 are drawings of region Y of FIG. 2, and FIGS. 21 and 22 are drawings of region W of FIG. 20.

Referring to FIG. 1, a first substrate 100 including a first chip region 10 and a first scribe lane region 20 may be prepared.

In example embodiments, the first substrate 100 may be a wafer including a semiconductor material, e.g., silicon, germanium, silicon-germanium, etc., and may have a circular shape in a plan view.

In example embodiments, n-type impurities, e.g., phosphorus, arsenic, etc., may be doped in the first substrate 100, and thus the first substrate 100 may serve as a common source plate (CSP). Alternatively, a metal silicide layer including, e.g., tungsten silicide may be formed on the first substrate 100, and the first substrate 100 may serve as the CSP.

In example embodiments, a plurality of first chip regions 10 may be spaced apart from each other in the second and third directions D2 and D3 on the first substrate 100. In an example embodiment, the first chip regions 10 may be arranged in a lattice pattern in a plan view, and the first scribe lane region 20 may be formed between the first chip regions 10 to surround the first chip regions 10. Thus, the first scribe lane region 20 may include extension portions extending in the second and third directions D2 and D3, respectively, and crossing each other.

Referring to FIG. 2, the first chip region 10 may include first and second regions I and II.

In example embodiments, the first region I may be a cell array region in which memory cells are formed, and the second region II may be a pad region or an extension region in which pads electrically connected to contact plugs for applying electric signals to the memory cells are formed. The second region II may at least partially surround the first region I.

Referring to FIGS. 3 to 5, a sacrificial layer structure 140 and a support layer 150 may be formed on the first substrate 100, the sacrificial layer structure 140 may be partially removed to form a first opening 145 exposing an upper surface of the first substrate 100, and a support layer 150 may be formed on an upper surface of the sacrificial layer structure 140 and the exposed upper surface of the first substrate 100.

The sacrificial layer structure 140 may include first, second and third sacrificial layers 110, 120 and 130 sequentially stacked in the first direction D1. Each of the first and third sacrificial layers 110 and 130 may include an oxide, e.g., silicon oxide, and the second sacrificial layer 120 may include a nitride, e.g., silicon nitride.

The first opening 145 may have various layouts in a plan view. For example, a plurality of first openings 145 may be spaced apart from each other in the second and third directions D2 and D3 on the first region I of the first substrate 100, the first opening 145 may extend in the second direction D2 or in the third direction D3 on an interface between the first and second regions I and II of the first substrate 100, and a plurality of first openings 145, each of which may extend in the second direction D2, may be spaced apart from each other in the third direction D3 on the second region II of the first substrate 100. FIG. 5 shows the first opening 145 extending in the third direction D3 on the interface between the first and second regions I and II of the first substrate 100.

The support layer 150 may include a material having an etching selectivity with respect to the first to third sacrificial layers 110, 120 and 130, e.g., polysilicon doped with n-type impurities. The support layer 150 may have a constant thickness, and thus a portion of the support layer 150 may form a first recess in the first opening 145. The portion of the support layer 150 in the first opening 145 may also be referred to as a support pattern.

An insulation layer 160 and a fourth sacrificial layer 170 may be alternately and repeatedly stacked on the support layer 150 in the first direction D1, and a mold layer including the insulation layers 160 and the fourth sacrificial layers 170 may be formed. The insulation layer 160 may include an oxide, e.g., silicon oxide, and the fourth sacrificial layer 170 may include a material having an etching selectivity with respect to the insulation layer 160, e.g., a nitride such as silicon nitride.

FIG. 5 shows that the first insulation layers 160 and the fourth sacrificial layers 170 are stacked at fourteen levels and thirteen levels, respectively, however, example embodiments are not limited thereto.

A photoresist layer may be formed on an uppermost one of the first insulation layers 160, may be patterned to form a photoresist pattern, and the uppermost one of the insulation layers 160 and an uppermost one of the fourth sacrificial layers 170 may be etched using the photoresist pattern as an etching mask. Thus, a portion of one of the insulation layers 160 directly under the uppermost one of the fourth sacrificial layers 170 may be exposed. After performing a trimming process for reducing an area of the photoresist pattern, the uppermost one of the insulation layers 160, the uppermost one of the fourth sacrificial layers 170, the exposed one of the insulation layers 160 and one of the fourth sacrificial layer 170 directly under the exposed one of the insulation layers 160 may be etched by an etching process using the reduced photoresist pattern as an etching mask.

The trimming process and the etching process may be repeatedly performed to form a mold having a staircase shape and including a plurality of step layers each of which may include one fourth sacrificial layer 170 and one insulation layer 160 sequentially stacked. Hereinafter, the “step layer” may refer to all portions of the fourth sacrificial layer 170 and the insulation layer 160 at the same level, which may include an unexposed portion as well as an exposed portion of the fourth sacrificial layer 170 and the insulation layer 160, and a “step” may refer to only the exposed portion of the “step layer.” In example embodiments, the steps may be arranged in the second direction D2. Alternatively, the steps may be arranged in the third direction D3. In some example embodiments, the steps may also be arranged in both the second direction D2 and the third direction D3.

An edge portion of the support layer 150 may not be covered by the mold, but may be exposed.

Referring to FIGS. 6 to 8, a first insulating interlayer 310 may be formed on the first substrate 100 to cover the mold, the support layer 150 and the sacrificial layer structure 140, and may be planarized until an upper surface of the uppermost one of the insulation layers 160 is exposed. Thus, a sidewall of the mold, an upper surface and a sidewall of the support layer 150 and a sidewall of the sacrificial layer structure 140 may be covered by the first insulating interlayer 310.

A channel hole 180 may be formed through the mold, the support layer 150 and the sacrificial layer structure 140 to expose the upper surface of the first substrate 100. In some example embodiments, the channel hole 180 may extend into the first substrate 100. A charge storage structure layer and a channel layer may be sequentially formed on a sidewall of the channel hole 180, the exposed upper surface of the first substrate 100, an upper surface of the uppermost one of the first insulation layers 160 of the mold and the first, and an upper surface of the first insulating interlayer 310, and a filling layer may be formed on the channel layer to fill the channel hole 180.

The channel layer may include, e.g., polysilicon, and the filling layer may include an oxide, e.g., silicon oxide. The charge storage structure layer may include a first blocking layer, a charge storage layer and a tunnel insulation layer sequentially stacked on an inner wall of the channel hole 180. The first blocking layer and the tunnel insulation layer may include an oxide, e.g., silicon oxide, and the charge storage layer may include a nitride, e.g., silicon nitride.

The filling layer, the channel layer and the charge storage structure layer may be planarized until the upper surface of the uppermost one of the insulation layers 160 is exposed. Thus, a filling pattern 280, a channel 270 and charge storage structure 260 may be formed in the channel hole 180. The charge storage structure 260 may include a first blocking pattern 230, a charge storage pattern 240 and a tunnel insulation pattern 250 sequentially stacked.

In example embodiments, the filling pattern 280 may have a shape of a pillar extending in the first direction D1, the channel 270 may have a shape of a cup covering a sidewall and a lower surface of the filling pattern 280, and the charge storage structure 260 may have a shape of a cup covering an outer sidewall and a lower surface of the channel 270.

Upper portions of the channel 270 and the filling pattern 280 may be removed to form a first trench, and a capping pattern 290 may be formed to fill the first trench. In example embodiments, the capping pattern 290 may include polysilicon doped with impurities or amorphous silicon doped with impurities, and if the capping pattern 290 includes amorphous silicon doped with impurities, a crystallization process may be further performed on the capping pattern 290.

The charge storage structure 260, the channel 270, the filling pattern 280 and the capping pattern 290 in the channel hole 180 may form a memory channel structure 490. In example embodiments, a plurality of memory channel structures 490 may be spaced apart from each other in the second and third directions D2 and D3 on the first region I of the first substrate 100. Each of the memory channel structures 490 may have a width gradually decreasing from a top toward a bottom thereof (i.e., toward the first substrate 100).

Referring to FIG. 9, the first insulating interlayer 310, ones of the insulation layers 160 and ones of the fourth sacrificial layers 170 may be etched to form a second opening extending in the second direction D2 through the first insulating interlayer 310, the ones of the insulation layers 160 and the ones of the fourth sacrificial layers 170, and a first division pattern 320 may be formed in the second opening.

In example embodiments, the first division pattern 320 may extend in the second direction D2 on the first and second regions I and II of the first substrate 100, and may extend through, e.g., two upper step layers of the mold. Thus, the fourth sacrificial layers 170 at the upper two levels, respectively, of the mold may be divided in the third direction D3 by the first division pattern 320. In an example embodiment, the first division pattern 320 may extend through some of the memory channel structures 490.

The first division pattern 320 may include an oxide, e.g., silicon oxide, or an insulating nitride, e.g., silicon nitride.

Referring to FIG. 10, a second insulating interlayer 330 may be formed on the first insulating interlayer 310 and the first division pattern 320, and a third opening 340 may be formed through the first and second insulating interlayers 310 and 330 and the mold on the first substrate 100 by, e.g., a dry etching process.

The dry etching process may be performed until an upper surface of the support layer 150 or the support pattern is exposed through the third opening 340, and further the third opening 340 may extend through an upper portion of the support layer 150 or the support pattern. In example embodiments, the third opening 340 may extend in the second direction D2 on the first and second regions I and II, and a plurality of third openings 340 may be spaced apart from each other in the third direction D3. As the third opening 340 is formed, the first insulation layer 160 of the mold may be divided into a plurality of first insulation patterns 165 each of which may extend in the second direction D2, and the fourth sacrificial layer 170 may be divided into a plurality of fourth sacrificial patterns 175 each of which may extend in the second direction D2.

A spacer layer may be formed on a sidewall of the third opening 340 and an upper surface of the second insulating interlayer 330, and an anisotropic etching process may be performed to remove a portion of the spacer layer on a bottom of the third opening 340 so that a spacer 350 may be formed. Accordingly, the upper surface of the support layer 150 or the support pattern may be partially exposed.

The exposed portion of the support layer 150 or the support pattern and a portion of the sacrificial layer structure 140 thereunder may be removed so that the third opening 340 may be enlarged downwardly. Thus, the third opening 340 may expose the upper surface of the first substrate 100, and further extend through an upper portion of the first substrate 100.

In example embodiments, the spacer 350 may include, e.g., undoped polysilicon or undoped amorphous silicon. If the spacer 350 includes undoped amorphous silicon, the spacer 350 may be crystallized by heat during formation of other layers so as to include undoped polysilicon.

When the sacrificial layer structure 140 is partially removed, the sidewall of the third opening 340 may be covered by the spacer 350, and thus the first insulation pattern 165 and the fourth sacrificial pattern 175 of the mold may not be removed with the sacrificial layer structure 140.

Referring to FIG. 11, the sacrificial layer structure 140 may be removed by, e.g., a wet etching process through the third opening 340, and thus a first gap 360 may be formed.

In example embodiments, the wet etching process may be performed using an etching solution, e.g., HF and/or H₃PO₄.

As the first gap 360 is formed, a lower surface of the support layer 150 and the upper surface of the first substrate 100 adjacent to the third opening 340 may be exposed. Additionally, a sidewall of the charge storage structure 260 may be exposed by the first gap 360, and a lateral portion of the charge storage structure 260 exposed by the first gap 360 may also be removed to expose an outer sidewall of the channel 270. Thus, the charge storage structure 260 may be divided into an upper portion covering most portion of the outer sidewall of the channel 270 and a lower portion covering a lower surface of the channel 270 on the first substrate 100.

When the first gap 360 is formed by the wet etching process, the support layer 150 and the support pattern may not be removed, and thus the mold may not collapse.

Referring to FIG. 12, the spacer 350 may be removed, a channel connection layer may be formed on the sidewall of the third opening 340 and in the first gap 360, and a portion of the channel connection layer in the third opening 340 may be removed by, e.g., an etch back process to form a channel connection pattern 370 in the first gap 360.

As the channel connection pattern 370 is formed, the channels 270 between the third openings 340 neighboring in the third direction D3 on the first region I of the first substrate 100 may be connected with each other.

The channel connection pattern 370 may include, e.g., amorphous silicon doped with n-type impurities, and may be crystallized during formation of other layers to include polysilicon doped with n-type impurities.

An air gap 380 may be formed in the channel connection pattern 370.

Referring to FIG. 13, the fourth sacrificial patterns 175 exposed by the third opening 340 may be removed to form a second gap between neighboring ones of the first insulation patterns 165 in the first direction D1, and a portion of an outer sidewall of the first blocking pattern 230 may be exposed by the second gap.

In example embodiments, a wet etching process may be performed using, e.g., phosphoric acid (H₃PO₄) or sulfuric acid (H₂SO₄) to remove the fourth sacrificial patterns 175.

A second blocking layer 390 may be formed on the outer sidewall of the first blocking pattern 230 exposed by the third opening 340, inner walls of the second gaps, surfaces of the first insulation patterns 165, a sidewall and a lower surface of the support layer 150, a sidewall of the support pattern, a sidewall of the channel connection pattern 370, the upper surface of the first substrate 100 and the upper surface of the second insulating interlayer 330, and a gate electrode layer may be formed on the second blocking layer 390.

In example embodiments, the second blocking layer 390 may include a metal oxide, e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc. The gate electrode layer may include a gate conductive layer and a gate barrier layer covering lower and upper surfaces and a sidewall of the gate conductive layer. The gate conductive layer may include a metal having a low resistance, e.g., tungsten, titanium, tantalum, etc., and the gate barrier layer may include a metal nitride, e.g., titanium nitride, tantalum nitride, etc.

The gate electrode layer may be partially removed to form a gate electrode in each of the second gaps. In example embodiments, the gate electrode layer may be partially removed by a wet etching process.

In example embodiments, the gate electrode may extend in the second direction D2, and a plurality of gate electrodes may be spaced apart from each other in the first direction D1 to form a gate electrode structure. The gate electrode structure may have a staircase shape in which lengths in the second direction D2 of the gate electrodes decrease from a lowermost level toward an uppermost level. An end portion of each of the gate electrodes in the second direction D2 that is not overlapped by ones of the gate electrodes overlying each of the gate electrodes may be referred to as a pad. In example embodiments, a plurality of gate electrode structures may be spaced apart from each other in the third direction D3 by the third opening 340.

The gate electrode structure may include first, second and third gate electrodes 402, 404 and 406 sequentially stacked in the first direction D1. Additionally, a fourth gate electrode serving as a GIDL gate electrode for operating body erase using GIDL phenomenon under the first gate electrode 402 and/or over the third gate electrode 406.

In example embodiments, the first gate electrode 402 may serve as a ground selection line (GSL), and the third gate electrode 406 may serve as a string selection line (SSL). FIG. 16 shows that the first gate electrode 402 is formed at a lowermost level, and the third gate electrodes 404 are formed at upper two levels, respectively, however, example embodiments are not limited thereto. The second gate electrodes 404 may be formed at a plurality of levels, respectively, between the first and third gate electrodes 402 and 406, and may serve as word lines, respectively.

Referring to FIGS. 14 to 16, a division layer may be formed on the second blocking layer 390 to fill the third opening 340, and may be planarized until the upper surface of the second insulating interlayer 330 is exposed to form a second division pattern 410. During the planarization process, a portion of the second blocking layer 390 on the upper surface of the second insulating interlayer 330 may be removed, and a remaining portion of the second blocking layer 390 may form a second blocking pattern 395.

The second division pattern 410 may extend in the second direction D2 on the first and second regions I and II of the first substrate 100, and a plurality of second division patterns 410 may be spaced apart from each other in the third direction D3. The second division pattern 410 may include an oxide, e.g., silicon oxide.

A third insulating interlayer 420 including an oxide, e.g., silicon oxide may be formed on the second insulating interlayer 330, the second division pattern 410 and the second blocking pattern 395, and first contact plugs 432 extending through the first to third insulating interlayers 310, 330 and 420, the first insulation pattern 165 and the second blocking pattern 395 to contact corresponding ones of the first to third gate electrodes 402, 404 and 406, respectively, a second contact plug 434 extending through the first to third insulating interlayers 310, 330 and 420 to contact the upper surface of the first substrate 100, and third contact plugs 436 extending through the second and third insulating interlayers 330 and 420 to contact a corresponding one of the capping patterns 290, respectively, may be formed. In example embodiments, each of the first to third contact plugs 432, 434 and 436 may have a width gradually decreasing from a top toward a bottom thereof (i.e., toward the first substrate 100).

A fourth insulating interlayer 440 including an oxide, e.g., silicon oxide may be formed on the third insulating interlayer 420, and first to third wirings 452, 454 and 456 may be formed through the fourth insulating interlayer 440 to contact upper surfaces of the first to third contact plugs 432, 434 and 436, respectively. The first to third contact plugs 432, 434 and 436 and the first to third wirings 452, 454 and 456 may have various layouts.

The first to third contact plugs 432, 434 and 436 and the first to third wirings 452, 454 and 456 may include, e.g., a metal, a metal nitride, a metal silicide, doped polysilicon, etc.

In example embodiments, the third wiring 456 may extend in the third direction D3 on the first region I of the first substrate 100, and a plurality of third wirings 456 may be spaced apart from each other in the second direction D2. Each of the third wirings 456 may serve as a bit line of the semiconductor device.

Referring to FIGS. 17 and 18, a fifth insulating interlayer 460 including an oxide, e.g., silicon oxide may be formed on the fourth insulating interlayer 440, and a first via extending through the fifth insulating interlayer 460 to contact the first wiring 452, and second and third vias 474 and 476 extending through the fifth insulating interlayer 460 to contact the second and third wirings 454 and 456, respectively, may be formed.

A sixth insulating interlayer 480 may be formed on the fifth insulating interlayer 460, the first via and the second and third vias 474 and 476, and a fourth wiring extending through the sixth insulating interlayer 480 to contact the first via, fifth and sixth wirings 494 and 496 extending through the sixth insulating interlayer 480 to contact the second and third vias 474 and 476, respectively, and a first conductive pattern 492 may be formed. The sixth insulating interlayer 480 may include an insulating material, e.g., silicon oxide or silicon nitride.

The first via, the second and third vias 474 and 476, the fourth wiring, the fifth and sixth wirings 494 and 496, and the first conductive pattern 492 may include a conductive material, e.g., a metal, a metal nitride, a metal silicide, doped polysilicon, etc.

In example embodiments, a plurality of first conductive patterns 492 may be spaced apart from each other in the second and third directions D2 and D3 on the first and second regions I and II of the first substrate 100, and may have various layouts. For example, a plurality of first conductive patterns 492 each of which may extend in the second direction D2 may be spaced apart from each other in the third direction D3. Alternatively, a plurality of first conductive patterns 492 each of which may extend in the third direction D3 may be spaced apart from each other in the second direction D2.

In example embodiments, the first conductive patterns 492 neighboring in a horizontal direction substantially parallel to the upper surface of the first substrate 100, and a portion of the sixth insulating interlayer 480 between the neighboring first conductive patterns 492 may form a capacitor. Alternatively, each of the first conductive patterns 492 may form a resistor having a resistance greater than resistances of the fourth wiring and the fifth and sixth wirings 494 and 496. Alternatively, each of the first conductive patterns 492 may form an inductor.

A seventh insulating interlayer 500 including an oxide, e.g., silicon oxide may be formed on the sixth insulating interlayer 480, the fourth wiring and the fifth and sixth wirings 494 and 496, and a first bonding pattern extending through the seventh insulating interlayer 500 to contact the fourth wiring, a second bonding pattern 512 extending through the seventh insulating interlayer 500 to contact the first conductive pattern 492, and third and fourth bonding patterns 514 and 516 extending through the seventh insulating interlayer 500 to contact the fifth and sixth wirings 494 and 496, respectively, may be formed.

In example embodiments, the first bonding patterns, the second bonding patterns 512, the third boding patterns 514 and the fourth bonding patterns 516 may be spaced apart from each other in the second and third directions D2 and D3 on the first and second regions I and II of the first substrate 100, and may be arranged in a lattice pattern in a plan view. In an example embodiment, each of the first bonding pattern and the second to fourth bonding patterns 512, 514 and 516 may be formed by a dual damascene process, and thus may have a lower portion and an upper portion having a width greater than a width of the lower portion. Alternatively, each of the first bonding pattern and the second to fourth bonding patterns 512, 514 and 516 may be formed by a single damascene process.

The first bonding pattern and the second to fourth bonding patterns 512, 514 and 516 may include a metal having a low resistance, e.g., copper, aluminum, etc.

Referring to FIG. 19, a second substrate 700 including a second chip region 15 and a second scribe lane region 25 may be prepared.

The second substrate 700 may be a wafer substantially similar to the first substrate 100. Thus, the second substrate 700 may include a semiconductor material, e.g., silicon, germanium, silicon-germanium, etc., and may have a circular shape in a plan view. The second chip region 15 and the second scribe lane region 25 may have layouts substantially similar to the layouts of the first chip region 10 and the first scribe lane region 20 of the first substrate 100.

Referring to FIG. 20, the second chip region 15 of the second substrate 700 may include first and second regions I and II, which may be a cell array region and a pad region, respectively, correspondingly to the first chip region 10 of the first substrate 100.

Referring to FIG. 21, an upper circuit patterns may be formed on the second substrate 700 including first to third active regions 702, 704 and 706 that may be defined by a first isolation pattern 710. The upper circuit patterns may include, e.g., transistors, upper contact plugs, upper wirings, upper vias, etc.

FIG. 21 shows first to third transistors including first to third upper gate electrodes 752, 754 and 756, respectively, on the second substrate 700 and first to third impurity regions 701, 703 and 706, respectively, however, example embodiments are not limited thereto. The first to third transistors may have various layouts.

The first upper gate electrode 752 may include a first upper gate insulation pattern 722, a first upper gate electrode 732 and a first upper gate mask 742 sequentially stacked on the first active region 702, the second upper gate electrode 754 may include a second upper gate insulation pattern 724, a second upper gate electrode 734 and a second upper gate mask 744 sequentially stacked on the second active region 704, and the third upper gate electrode 756 may include a third upper gate insulation pattern 726, a third upper gate electrode 736 and a third upper gate mask 746 sequentially stacked on the third active region 706.

A first upper insulating interlayer 760 including an oxide, e.g., silicon oxide may be formed on the second substrate 700, and may cover the first to third transistors. First to third upper contact plugs 772, 774 and 776 may extend through the first upper insulating interlayer 760 to contact the first to third impurity regions 701, 703 and 706, respectively.

A first upper wiring 782 may be formed on the first upper insulating interlayer 760, and may contact an upper surface of the first upper contact plug 772. A first upper via 792, a fourth upper wiring 802, a fourth upper via 812 and a seventh upper wiring 822 may be sequentially stacked on the first upper wiring 782. Additionally, a second upper wiring 784 may be formed on the first upper insulating interlayer 760, and may contact an upper surface of the second upper contact plug 774. A second upper via 794, a fifth upper wiring 804, a fifth upper via 814 and an eighth upper wiring 824 may be sequentially stacked on the second upper wiring 784. Further, a third upper wiring 786 may be formed on the first upper insulating interlayer 760, and may contact an upper surface of the third upper contact plug 776. A third upper via 796, a sixth upper wiring 806, a sixth upper via 816 and a ninth upper wiring 826 may be sequentially stacked on the third upper wiring 786.

The first to ninth upper wirings 782, 784, 786, 802, 804, 806, 822, 824 and 826 and the first to sixth upper vias 792, 794, 796, 812, 814 and 816 may be formed on the first upper insulating interlayer 760, and may be covered by a second upper insulating interlayer 830 including an oxide, e.g., silicon oxide.

The first to third upper contact plugs 772, 774 and 776, the first to sixth upper vias 792, 794, 796, 812, 814 and 816, and the first to ninth upper wirings 782, 784, 786, 802, 804, 806, 822, 824 and 826 may include a metal, e.g., tungsten, titanium, tantalum, etc., and may also include a metal nitride.

Referring to FIG. 22, a third upper insulating interlayer 840 including an oxide, e.g., silicon oxide may be formed on the second upper insulating interlayer 830 and the seventh to ninth upper wirings 822, 824 and 826, and sixth to eighth bonding patterns 852, 854 and 856 may be formed through the third insulating interlayer 840 to contact the seventh to ninth upper wirings 822, 824 and 826.

In example embodiments, the sixth to eighth bonding patterns 852, 854 and 856 may be formed at positions corresponding to positions of the second to fourth bonding patterns 512, 514 and 516, respectively, on the first substrate 100. A fifth bonding pattern may be further formed on the second substrate 700 at a position corresponding to a position of the first bonding pattern on the first substrate 100, and a fourth transistor and upper contact plugs, upper wirings and upper vias may be further formed under the fifth bonding pattern.

The fifth bonding pattern and the sixth to eighth bonding patterns 852, 854 and 856 may be formed by a dual damascene process or a single damascene process, and may include a metal having a low resistance, e.g., copper, aluminum, etc.

Referring to FIGS. 23 to 25, a first dicing process or a first sawing process may be performed to separate (i.e., cut off) a first portion 900 of the second substrate 700, and may be turned over and bonded with a corresponding portion of the first substrate 100.

The third upper insulating interlayer 840 on the second substrate 700 may be bonded with the seven insulating interlayer 500 on the first substrate 100, and the fifth bonding pattern and the sixth to eighth bonding patterns 852, 854 and 856 on the second substrate 700 may contact the first bonding pattern and the second to fourth bonding patterns 512, 514 and 516, respectively on the first substrate 100.

Thus, upper and lower portions of structures on the second substrate 700 may be changed into lower and upper portions, respectively, of the structures.

In example embodiments, the first portion 900 of the second substrate 700 that may be separated by the first dicing process may be a central portion of the second substrate 700, and may include a plurality of second chip regions 15. That is, the first dicing process may be performed along a portion of the second scribe lane region 25 surrounding ones of the second chip regions 15 on the central portion of the second substrate 700.

In an example embodiment, the first portion 900 of the second substrate 700 may have a square or rectangular shape in a plan view.

Referring to FIG. 26, a second dicing process may be performed to separate a second portion 910 of the second substrate 700, and may be turned over and bonded with a corresponding portion of the first substrate 100.

As illustrated with reference to FIGS. 23 to 25, the fifth bonding pattern and the sixth to eighth bonding patterns 852, 854 and 856 on the second substrate 700 may contact the first bonding pattern and the second to fourth bonding patterns 512, 514 and 516, respectively on the first substrate 100.

In example embodiments, the second portion 910 of the second substrate 700 that may be separated by the second dicing process may be a first edge portion of the second substrate 700 adjacent to the central portion of the second substrate 700, and may include a plurality of second chip regions 15. That is, the second dicing process may be performed along a portion of the second scribe lane region 25 surrounding ones of the second chip regions 15 on the first edge portion of the second substrate 700.

Referring to FIG. 27, processes substantially the same as or similar to those illustrated with reference to FIG. 26 may be performed.

Thus, a third dicing process may be performed to separate a third portion 920 of the second substrate 700, and may be turned over and bonded with a corresponding portion of the first substrate 100.

In example embodiments, the third portion 920 of the second substrate 700 that may be separated by the third dicing process may be a second edge portion of the second substrate 700 adjacent to the first edge portion of the second substrate 700, and may include a plurality of second chip regions 15. That is, the third dicing process may be performed along a portion of the second scribe lane region 25 surrounding ones of the second chip regions 15 on the second edge portion of the second substrate 700.

Referring to FIG. 28, processes substantially the same as or similar to those illustrated with reference to FIG. 26 may be performed.

Thus, a fourth dicing process may be performed to separate a fourth portion 930 of the second substrate 700, and may be turned over and bonded with a corresponding portion of the first substrate 100.

In example embodiments, the fourth portion 930 of the second substrate 700 that may be separated by the fourth dicing process may be a third edge portion of the second substrate 700 adjacent to the second edge portion of the second substrate 700, and may include a plurality of second chip regions 15. That is, the fourth dicing process may be performed along a portion of the second scribe lane region 25 surrounding ones of the second chip regions 15 on the third edge portion of the second substrate 700.

If some of the second chip regions 15 that is not separated by a dicing process from the second substrate 700 remain, processes substantially the same as or similar to those illustrated with reference to FIG. 28 may be further performed. However, example embodiments are not limited thereto, and even if ones of the second chip regions 15 remain in the second substrate 700, structures in the remaining ones of the second chip regions 15, which may not satisfy a give criteria, may not be separated from the second substrate 700 to be bonded with the first substrate 100.

A final dicing process may be performed on a stacked structure of the first and second substrate 100 and 700, so that a chip including the first substrate 100 having one first chip region 10 and the second substrate 700 having one second chip region 15 may be provided.

Warpage may occur on each of the first and second substrates 100 and 700 due to structures thereon, and the warpage may mainly occur on edge portions of the first and second substrates 100 and 700. If the first and second substrates 100 and 700 are entirely stacked, misalignment may occur due to warpage differences between the first and second substrates 100 and 700.

Thus, for example, the fifth bonding pattern and the sixth to eighth bonding patterns 852, 854 and 856 on the second substrate 700 may not be bonded with the first bonding pattern and the second to fourth bonding patterns 512, 514 and 516, respectively, on the first substrate 100, and thus the first and second substrates 100 and 700 may not be securely bonded with each other. Even if the first and second substrates 100 and 700 are securely bonded with each other, electric connections between the structures on the first and second substrates 100 and 700, respectively, may not be reliable due to the misalignment.

However, in example embodiments, the second substrate 700 may not be entirely bonded with the first substrate 100 by a single process. Rather, the second substrate 700 may be divided into a plurality of parts and bonded with corresponding portions, respectively, of the first substrate 100 by a plurality of processes. Thus, the misalignment of the structures on the first and second substrates 100 and 700 due to the warpage differences may be prevented. In this regard, the first and second substrates 100 and 700 may be securely bonded with reliable electrical connections between the structures on the first and second substrates 100 and 700.

Process time for bonding the first and second substrates 100 and 700 by a plurality of processes may increase when compared to the bonding the first and second substrates 100 and 700 by a single process. However, the second chip regions 15 may not be separated from the second substrate 700 by respective dicing processes, but the second substrate 700 may be divided into a plurality of portions including a plurality of second chip regions 15, and the divided portions of the second substrate 700 may be separated from the second substrate 700 and bonded with corresponding portions of the first substrate 100. Thus, the increase of the process time may be minimized. Particularly, the central portion of the second substrate 700 of which a warpage occurrence probability is small may include a great number of the second chip regions 15 that may be separated from the second substrate 700 by a single dicing process, which may minimize the process time increase.

In the processes illustrated with reference to FIGS. 23 to 28, the second substrate 700 is divided into the first to fourth portions 900, 910, 920 and 930, however, example embodiments are not limited thereto. That is, the second substrate 700 may be divided into more or less than four portions, and a dicing process and a bonding process may be performed by the unit of the divided portions of the second substrate 700. One or ones of the divided portions, e.g., an edge portion of the second substrate 700 may include a single second chip region 15 instead of a plurality of second chip regions 15.

The order of the dicing and bonding processes may not be limited to the order described with reference to FIGS. 23 to 28, and for example, the fourth portion 930, the third portion 920, the second portion 910 and the first portion 900 may be separated and bonded with the first substrate 100 in this order, or the first to fourth portions 900, 910, 920 and 930 may be simultaneously separated and bonded with the first substrate 100.

In the processes illustrated with reference to FIGS. 23 to 28, the second substrate 700 is divided and bonded with the first substrate 100, however, example embodiments are not limited thereto, and for example, the first substrate 100 may be diced and bonded with the second substrate 700.

In the processes illustrated with reference to FIGS. 23 to 28, two substrates, that is, the first and second substrates 100 and 700 are stacked to manufacture the chip, however, example embodiments are not limited thereto, and more than two substrates may be stacked to manufacture a chip.

For example, if three substrates are stacked to manufacture the chip, a lower substrate and a middle substrate may be entirely bonded with each other by a single process, and an upper substrate may be divided into a plurality of parts, and separated and bonded with the middle substrate. Finally, the lower, middle and upper substrates may be diced to manufacture the chip.

Alternatively, the middle substrate may be divided into a plurality of parts, and separated and bonded with the lower substrate. Additionally, the upper substrate may be divided into a plurality of parts, and separated and bonded with the middle substrate on the lower substrate. Finally, the lower, middle and upper substrates may be diced to manufacture the chip.

FIGS. 29A, 29B and 29C illustrate plan views illustrating a shape of the first portion 900 of the second substrate 700 separated from the second substrate 700 by the first dicing process.

Referring to FIGS. 29A, 29B and 29C, unlike the shape of the first portion 900 shown in FIG. 23, the first portion 900 may have a square shape or a rectangular shape with corners having a staircase shape in a plan view.

The second substrate 700 has a circular shape in a plan view, and if the first portion 900 of the second substrate 700 is the central portion of the second substrate 700, the first portion 900 may have a square shape or a rectangular shape with staircase shape of corners so as to include more numbers of the second chip regions 15.

FIGS. 30 to 32 includes plan views illustrating positions and layouts of the first portion 900 of the second substrate 700 separated from the second substrate 700 by the first dicing process.

Referring to FIG. 30, the first portion 900 of the second substrate 700 may include an edge portion as well as the central portion thereof.

That is, the first portion 900 of the second substrate 700 that may be separated by the first dicing process may not necessarily include only ones of the second chip regions 15 in the central portion of the second substrate 700, but may also include ones of the second chip regions 15 in an edge portion thereof. Additionally, the first portion 900 of the second substrate 700 may include ones of the second chip regions 15 in a plurality of edge portions spaced apart from each other.

Referring to FIG. 31, the first portion 900 of the second substrate 700 may include ones of the second chip regions 15 in a plurality of central portions of the second substrate 700.

That is, the first portion 900 of the second substrate 700 that may be separated by the first dicing process may not necessarily include ones of the second chip regions 15 in a single central portion of the second substrate 700, but may include ones of the second chip regions 15 in a plurality of central portions thereof. The central portions of the second substrate 700 may have different areas from each other.

Referring to FIG. 32, the first portion 900 of the second substrate 700 may include ones of the second chip regions 15 in a plurality of edge portions of the second substrate 700.

That is, the first portion 900 of the second substrate 700 that may be separated by the first dicing process may not necessarily include ones of the second chip regions 15 in the central portion of the second substrate 700, but may include ones of the second chip regions 15 in an edge portion thereof. Additionally, the first portion 900 of the second substrate 700 may include ones of the second chip regions 15 in a plurality of edge portions spaced apart from each other.

As illustrated above, the first portion 900 of the second substrate 700 that may be separated by the first dicing process may have various shapes and layouts. Likewise, each of the second to fourth portions 910, 920, 930 and 940 of the second substrate 700 that may be separated by the second to fourth dicing processes, respectively, may also have various shapes and layouts.

FIGS. 33 to 52 are plan views and cross-sectional views illustrating a method of manufacturing a CMOS image sensor (CIS) in accordance with example embodiments. Particularly, FIGS. 33-34, 37-39 and 41-42 are the plan views, FIGS. 35 and 36 are cross-sectional views taken along lines E-E′ of corresponding plan views, respectively, FIGS. 40 and 45-52 are cross-sectional views taken along lines F-F′ of corresponding plan views, respectively, and FIGS. 43 and 44 are cross-sectional views taken along line G-G′ of corresponding plan views, respectively.

FIGS. 34, 38 and 42 are enlarged plan views of regions K, M and 0 of FIGS. 33, 37 and 41, respectively, and FIG. 52 is an enlarged plan view of region Q of FIG. 51. Additionally, FIGS. 35 and 36 are drawings of region L of FIG. 34, FIGS. 39 and 40 are drawing of region N of FIG. 38, and FIGS. 43 and 44 are drawings of region P of FIG. 42.

Referring to FIG. 33, a third substrate 1100 including a third chip region 30 and a third scribe lane region 40 may be prepared.

The third substrate 1100 may be a wafer including a semiconductor material, e.g., silicon, germanium, silicon-germanium, etc., and may have a circular shape in a plan view. In example embodiments, a plurality of third chip regions 30 may be spaced apart from each other in the second and third directions D2 and D3 in the third substrate 1100, and the third scribe lane region 40 may be formed between the third chip regions 30 to surround the third chip regions 30.

In example embodiments, the third substrate 1100 may be a substrate on which logic circuit patterns for processing electrical signals, e.g., electronic signals, voltage signals, etc., are formed.

Referring to FIG. 34, the third chip region 30 of the third substrate 1100 may include first and second regions I and II.

In example embodiments, the first region I of the third substrate 1100 may be a pixel region in which pixels are formed, and the second region II of the third substrate 1100 may be a connection region in which connection wirings for transferring electric signals in a vertical direction, that is, in the first direction D1 are formed. In example embodiments, the second region II may surround the first region I.

Referring to FIG. 35, fifth and sixth transistors may be formed on the first and second regions I and II of the third substrate 1100.

The fifth transistor may be formed by forming a fifth gate electrode 1112 on the first region I of the third substrate 1100, and doping impurities into upper portions of the third substrate 1100 adjacent to the fifth gate electrode 1112 to form a fourth impurity regions 1102. Additionally, the sixth transistor may be formed by forming a sixth gate electrode 1118 on the second region II of the third substrate 1100, and doping impurities into upper portions of the third substrate 1100 adjacent to the sixth gate electrode 1118 to form a fifth impurity regions 1108.

Contact plugs, wirings and vias may be formed to be electrically connected to the fifth and sixth transistors.

FIG. 35 shows a fourth contact plug 1122, a seventh wiring 1132, a fourth via 1142 and an eighth wiring 1152 sequentially stacked on the fifth gate electrode 1112 included in the fifth transistor, a fifth contact plug 1124, a ninth wiring 1134, a fifth via 1144 and a tenth wiring 1154 sequentially stacked on the fourth impurity region 1102 included in the fifth transistor, and a sixth contact plug 1128, an eleventh wiring 1138, a sixth via 1148 and a twelfth wiring 1158 sequentially stacked on the sixth gate electrode 1118 included in the sixth transistor.

An eighth insulating interlayer 1160 may be formed on the third substrate 1100 to cover the fifth and sixth transistors, the fourth to sixth contact plugs 1122, 1124 and 1128, the seventh to twelfth wirings 1132, 1152, 1134, 1154, 1138 and 1158, and the fourth to sixth vias 1142, 1144 and 1148.

Referring to FIG. 36, a seventh via 1178 may be formed through an upper portion of the eighth insulating interlayer 1160 to contact an upper surface of the twelfth wiring 1158, a first adhesion layer 1180 may be formed on the eighth insulating interlayer 1160 and the seventh via 1178, and a ninth bonding pattern 1198 may be formed through the first adhesion layer 1180 to contact the seventh via 1178 on the second region II of the third substrate 1100. The first adhesion layer 1180 may include an insulating nitride, e.g., silicon nitride, and the ninth bonding pattern 1198 may include a metal, e.g., copper.

Referring to FIG. 37, a fourth substrate 1200 including a fourth chip region 32 and a fourth scribe lane region 42 may be prepared.

The fourth substrate 1200 may be a wafer substantially similar to the third substrate 1100. Thus, the fourth substrate 1200 may be a wafer including a semiconductor material, e.g., silicon, germanium, silicon-germanium, etc., and may have a circular shape in a plan view. Additionally, the fourth chip region 32 and the fourth scribe lane region 42 included in the fourth substrate 1200 may have layouts substantially similar to the layouts of the third chip region 30 and the third scribe lane region 40, respectively, included in the third substrate 1100.

In example embodiments, the fourth substrate 1200 may be a wafer on which elements for converting electronic signals to voltage signals and memory elements are formed.

Referring to FIG. 38, the fourth chip region 32 of the fourth substrate 1200 may include first and second regions I and II, which may be a pixel region and a connection region, respectively, correspondingly to the third chip region 30 of the third substrate 1100.

Referring to FIGS. 39 and 40, an upper portion of the fourth substrate 1200 including first and second surfaces 1201 and 1203 opposite to each other in the first direction D1, that is, a portion of the fourth substrate 1200 adjacent to the second surface 1203 may be removed to form a second recess, and a second isolation pattern 1205 may be formed in the second recess.

The second isolation pattern 1205 may extend in the third direction D3 in the first region I of the fourth substrate 1200, and a plurality of second isolation patterns 1205 may be spaced apart from each other in the second direction D2. Thus, the first region I of the fourth substrate 1200 may be divided into third and fourth regions III and IV alternately and repeatedly disposed in the second direction D2.

The third and fourth regions III and IV of the fourth substrate 1200 may be a digital region in which digital block is formed and an analog region in which analog block is formed, respectively. That is, analog circuit patterns, which may form elements for converting electronic signals into voltage signals may be formed on the third region III of the fourth substrate 1200, and digital circuit patterns, which may form memory elements, may be formed on the fourth region IV of the fourth substrate 1200.

The second isolation pattern 1205 may include an oxide, e.g., silicon oxide.

Seventh and eighth transistors may be formed on the first region I of the fourth substrate 1200. In example embodiments, the seventh and eighth transistors may be formed on the third and fourth regions III and IV, respectively, divided by the second isolation pattern 1205 in the first region I of the fourth substrate 1200.

Particularly, the seventh transistor may be formed by forming a seventh gate electrode 1212 on the third region III of the fourth substrate 1200 and doping impurities into upper portions of the fourth substrate 1200 adjacent to the seventh gate electrode 1212 to form sixth impurity regions 1202. Additionally, the eighth transistor may be formed by forming an eighth gate electrode 1216 on the fourth region IV of the fourth substrate 1200 and doping impurities into upper portions of the fourth substrate 1200 adjacent to the eighth gate electrode 1216 to form seventh impurity regions 1206.

In example embodiments, the seventh transistor may be an element of circuit patterns of, e.g., an SRAM device or a DRAM device.

In example embodiments, the eighth transistor may be a source follower (SF) transistor. Additionally, a select transistor and a reset transistor may be further formed on the fourth region IV of the fourth substrate 1200.

Contact plugs, wirings and vias may be formed to be electrically connected to the seventh and eighth transistors.

FIG. 40 shows a seventh contact plug 1222, a thirteenth wiring 1232, an eighth via 1242 and a fourteenth wiring 1252 sequentially stacked on the seventh gate electrode 1212 included in the seventh transistor, an eighth contact plug 1224, a fifteenth wiring 1234, a ninth via 1244 and a sixteenth wiring 1254 sequentially stacked on the sixth impurity region 1202 included in the seventh transistor, and a ninth contact plug 1226, a seventeenth wiring 1236, a tenth via 1246 and an eighteenth wiring 1256 sequentially stacked on the eighth gate electrode 1216 included in the eighth transistor on the first region I of the fourth substrate 1200.

Additionally, a nineteenth wiring 1238, an eleventh via 1248 and a twentieth wiring 1258 may be sequentially stacked on the second region II of the fourth substrate 1200.

A ninth insulating interlayer 1260 may be formed on the second surface 1203 of the fourth substrate 1200 to cover the seventh and eighth transistors, the seventh to ninth contact plugs 1222, 1224 and 1226, the thirteenth to twentieth wirings 1232, 1252, 1234, 1254, 1236, 1256, 1238 and 1258, and the eighth to eleventh vias 1242, 1244, 1246 and 1248.

Twelfth and thirteenth vias 1276 and 1278 may be formed through an upper portion of the ninth insulating interlayer 1260 to contact upper surfaces of the eighteenth and twentieth wirings 1256 and 1258, respectively, a second adhesion layer 1280 may be formed on the ninth insulating interlayer 1260 and the twelfth and thirteenth vias 1276 and 1278, and tenth and eleventh bonding patterns 1296 and 1298 may be formed through the second adhesion layer 1280 to contact twelfth and thirteenth vias 1276 and 1278, respectively, on the first and second regions I and II of the fourth substrate 1200.

Referring to FIG. 41, a fifth substrate 1200 including a fifth chip region 34 and a fifth scribe lane region 44 may be prepared.

The fifth substrate 1400 may be a wafer substantially similar to the third substrate 1100. Thus, the fifth substrate 1400 may be a wafer including a semiconductor material, e.g., silicon, germanium, silicon-germanium, etc., and may have a circular shape in a plan view. Additionally, the fifth chip region 34 and the fifth scribe lane region 44 included in the fifth substrate 1400 may have layouts substantially similar to the layouts of the third chip region 30 and the third scribe lane region 40, respectively, included in the third substrate 1100.

Referring to FIG. 42, the fifth chip region 34 of the fifth substrate 1400 may include first and second regions I and II, which may be a pixel region and a connection region, respectively, correspondingly to the third chip region 30 of the third substrate 1100.

Referring to FIG. 43, a pixel division structure 1410, an eighth impurity region 1420 and a light sensing element 1430 (e.g., a photodiode) may be formed in the first region I of the fifth substrate 1400 including first and second surfaces 11401 and 403 opposite to each other in the first direction D1, and a transfer gate (TG) 1440 and a floating diffusion (FD) region 1450 may be formed.

In example embodiments, p-type well doped with p-type impurities, e.g., boron may be formed in the fifth substrate 1400.

The pixel division structure 1410 may extend in the first direction D1 from the second surface 1403 toward the first surface 1401 downwardly in an inside of the first region I and at a boundary between the first and second regions I and II of the fifth substrate 1400, and eighth impurity region 1420 doped with p-type impurities, e.g., boron may be formed at a portion of the fifth substrate 1400 adjacent to the pixel division structure 1410. An impurity concentration of the eighth impurity region 1420 may be higher than an impurity concentration of the p-type well.

In example embodiments, the pixel division structure 1410 may have a shape of a polygon, e.g., a rectangle, in a plan view, and thus unit pixel regions in which unit pixels are formed, which may be surrounded by the pixel division structure 1410, may be defined in the first region I of the fifth substrate 1400.

In example embodiments, the pixel division structure 1410 may include a core extending in the first direction D1 and a shell covering a sidewall of the core. The core may include undoped polysilicon or doped polysilicon, and the shell may include an insulating material, e.g., silicon oxide, silicon nitride, etc.

The light sensing element 1430 may be formed by doping n-type impurities, e.g., phosphorus into the p-type well in the first region I of the fifth substrate 1400.

The TG 1440 may be formed by forming a second trench extending in the first direction D1 from the second surface 1403 of the fifth substrate 1400 downwardly, and filling a conductive material in the second trench to protrude from the second surface 1403 of the fifth substrate 1400 upwardly.

The TG 1440 may include a filling portion extending from the second surface 1403 of the fifth substrate 1400 downwardly in the first direction D1, and a protrusion portion on the filling portion that has an upper surface higher than the second surface 1403 of the fifth substrate 1400. In example embodiments, the TG 1440 may be formed in the unit pixel region defined by the pixel division structure 1410.

N-type impurities, e.g., phosphorus may be doped into an upper portion of the fifth substrate 1400 adjacent to the TG 1440 to form the FD region 1450.

Referring to FIG. 44, contact plugs, wirings and vias electrically connected to the TG 1440 and the FD region 1450 may be formed.

FIG. 44 shows a tenth contact plug 1466, a twenty-first wiring 1476, a fourteenth via 1486 and a twenty-second wiring 1496 sequentially stacked on the FD region 1450, and an eleventh contact plug 1468, a twenty-third wiring 1478, a fifteenth via 1488 and a twenty-fourth wiring 1498 sequentially stacked on the TG 1440 on the first region I of the fifth substrate 1400.

One or ones of the wirings, e.g., the twenty-fourth wiring 1498 may extend from the first region I of the fifth substrate 1400 to the second region II of the fifth substrate 1400.

A tenth insulating interlayer 1500 may be formed on the second surface 1403 of the fifth substrate 1400 to cover the TG 1440, the FD region 1450, the tenth and eleventh contact plugs 1466 and 1468, the twenty-first to twenty-fourth wirings 1476, 1496, 1478 and 1498, and the fourteenth to fifteenth vias 1486 and 1488.

Sixteenth and seventeenth vias 1516 and 1518 may be formed through an upper portion of the tenth insulating interlayer 1500 to contact upper surfaces of the twenty-second and twenty-fourth wirings 1496 and 1498, respectively, a third adhesion layer 1520 may be formed on the tenth insulating interlayer 1500 and the sixteenth and seventeenth vias 1516 and 1518, and twelfth and thirteenth bonding patterns 1536 and 1538 may be formed through the third adhesion layer 1520 to contact the sixteenth and seventeenth vias 1516 and 1518, respectively, on the first and second regions I and II, respectively, of the fifth substrate 1400.

Referring to FIG. 45, processes substantially the same as or similar to those illustrated with reference to FIGS. 23 to 28 may be performed so that the fourth and fifth substrates 1200 and 1400 may be bonded with each other.

In an example embodiment, the fifth substrate 1400 may be divided into a plurality of portions, a plurality of dicing processes may be performed to separate the plurality of portions of the fifth substrate 1400, respectively, and each of the plurality of portions of the fifth substrate 1400 separated from the fifth substrate 1400 may be turned over and bonded with a corresponding portion of the fourth substrate 1200.

The twelfth and thirteenth bonding patterns 1536 and 1538 on the fifth substrate 1400 may contact the tenth and eleventh bonding patterns 1296 and 1298, respectively, on the fourth substrate 1200. Thus, the FD region 1450 on the fifth substrate 1400 and electrically connected to the sixteenth via 1516 may be electrically connected to the sixth transistor on the fourth substrate 1200 through the tenth and twelfth bonding patterns 1296 and 1536.

Alternatively, the fourth substrate 1200 may be divided into a plurality of portions, and a dicing process may be performed to separate the plurality of portions of the fourth substrate 1200, and may be turned over and bonded with corresponding portions, respectively, of the fifth substrate 1400.

Referring to FIG. 46, the bonded fourth and fifth substrates 1200 and 1400 may be turned over, and an upper portion of the first region I of the fourth substrate 1200, that is, a portion of the first region I of the fourth substrate 1200 adjacent to the first surface 1201 may be removed to form a fourth opening 1610 exposing an upper surface of the second isolation pattern 1205.

A second insulation layer 1620 may be formed on the upper surface of the second isolation pattern 1205 exposed by the fourth opening 1610, a sidewall of the fourth opening 1610 and the first surface 1201 of the fourth substrate 1200, and a second conductive layer 1630 including, e.g., a metal may be formed on the second insulation layer 1620 to fill the fourth opening 1610.

Hereinafter, portions of the second insulation layer 1620 and the second conductive layer 1630 in the fourth opening 1610 may be referred to as a second insulation pattern 1622 and a second conductive pattern 1632, respectively, which may form a third isolation pattern structure 1642. Additionally, the second isolation pattern 1205 and the third isolation pattern structure 1642 stacked in the first direction D1 in the first region I of the fourth substrate 1200 may be referred to as a second isolation structure 1900.

The third and fourth regions III and IV of the first region I of the fourth substrate 1200 may be separated from each other by the second isolation structure 1900 in the first region I of the fourth substrate 1200.

Referring to FIG. 47, a fifth opening 1640 may be formed through portions of the second conductive layer 1630 and the second insulation layer 1620 on the second region II of the fourth substrate 1200, that is, on the first surface 1201 of the fourth substrate 1200 and upper portions of the fourth substrate 1200 and the ninth insulating interlayer 1260 to expose an upper surface of the nineteenth wiring 1238.

A third insulation layer may be formed on the upper surface of the nineteenth wiring 1238 exposed by the fifth opening 1640, a sidewall of the fifth opening 1640 and an upper surface of the second conductive layer 1630, and may be partially removed by an anisotropic etching process. Thus, a third insulation pattern 1655 may be formed on the sidewall of the fifth opening 1640. The third insulation pattern 1655 may include a metal oxide, e.g., aluminum oxide, hafnium oxide, etc., or silicon oxide, e.g., TEOS.

A third conductive layer may be formed on the upper surface of the nineteenth wiring 1238, a sidewall and an upper surface of the third insulation pattern 1655 and the upper surface of the second conductive layer 1630 to fill the fifth opening 1640, and may be planarized until the upper surface of the second conductive layer 1630 is exposed. Thus, a third conductive pattern 1665 filling a remaining portion of the fifth opening 1640 may be formed. The third conductive pattern 1665 may include a metal, e.g., tungsten, copper, aluminum, etc.

The third insulation pattern 1655 and the third conductive pattern 1665 may form a through electrode structure 1675.

Referring to FIG. 48, an eleventh insulating interlayer 1670 may be formed on the second conductive layer 1630 and the through electrode structure 1675, and an eighteenth via 1688 may be formed through the eleventh insulating interlayer 1670 to contact the third conductive pattern 1665.

A fourth adhesion layer 1690 may be formed on the eleventh insulating interlayer 1670 and the eighteenth via 1688, and a fourteenth bonding pattern 1708 may be formed through the fourth adhesion layer 1690 to contact the eighteenth via 1688.

Processes substantially the same as or similar to those illustrated with reference to FIGS. 23 to 28 may be performed so that the third and fourth substrates 1100 and 1200 may be bonded with each other.

In an example embodiment, the bonded fourth and fifth substrates 1200 and 1400 may be divided into a plurality of portions, a plurality of dicing processes may be performed to separate the plurality of portions of the bonded fourth and fifth substrates 1200 and 1400, and each of the plurality of portions of the bonded fourth and fifth substrates 1200 and 1400 separated from the bonded fourth and fifth substrates 1200 and 1400 may be turned over and bonded with a corresponding portion of the third substrate 1100.

The fourteenth bonding pattern 1708 on the fourth substrate 1200 may contact the ninth bonding pattern 1198 on the third substrate 1100.

Alternatively, the third substrate 1100 may be divided into a plurality of portions, a plurality of dicing processes may be performed to separate the plurality of portions of the third substrate 1100, and each of the plurality of portions of the third substrate 1100 separated from the third substrate 1100 may be turned over and bonded with a corresponding portion of the fourth substrate 1200.

Referring to FIG. 49, an upper portion of the fifth substrate 1400, that is, a portion of the fifth substrate 1400 adjacent to the first surface 1401 of the fifth substrate 1400 may be removed.

Thus, an upper surface of the pixel division structure 1410 may be exposed, and as a result, the pixel division structure 1410 may extend through the fifth substrate 1400.

In example embodiments, the upper portion of the fifth substrate 1400 may be removed by, e.g., a grinding process or a planarization process such as a CMP process.

Referring to FIG. 50, a lower planarization layer 1710 may be formed on the first surface 1401 of the fifth substrate 1400 and the pixel division structure 1410.

In an example embodiment, the lower planarization layer 1710 may include first, second, third, fourth and fifth layers sequentially stacked in the first direction D1. The first to fifth layers may include, e.g., aluminum oxide, hafnium oxide, silicon oxide, silicon nitride and hafnium oxide, respectively.

A barrier layer and a fourth conductive layer may be sequentially formed on an upper surface of the lower planarization layer 1710, and portions of the fourth conductive layer and the barrier layer in the first region I may be patterned to form a second interference blocking pattern 1735 and a first interference blocking pattern 1725, respectively, and portions of the barrier layer and the fourth conductive layer in the second region II may remain as a barrier pattern 1720 and a fourth conductive pattern 1730, respectively.

The barrier layer may include, e.g., a metal nitride, and the fourth conductive layer may include, e.g., a metal.

The barrier pattern 1720 and the fourth conductive pattern 1730 may form a light blocking metal layer 1740, and the first and second interference blocking patterns 1725 and 1735 may form an interference blocking structure 1745.

A protection layer 1750 may be formed on the lower planarization layer 1710 and the interference blocking structure 1745 in the first region I. The protection layer 1750 may include a metal oxide, e.g., aluminum oxide.

Referring to FIGS. 51 and 52, a color filter array layer including color filters 1760 may be formed on the protection layer 1750 in the first region I.

In example embodiments, the color filters 1760 may be formed by depositing a color filter layer on the protection layer 1750 and the light blocking metal layer 1740 through, e.g., a spin coating process, and performing an exposure process and a developing process on the color filter layer. In an example embodiment, each of the color filters 1760 may be formed on each of the unit pixel regions defined by the pixel division structure 1410. Alternatively, each of the color filters 1760 may be formed on neighboring ones of the unit pixel regions.

A lower surface and a sidewall of each of the color filters 1760 may be covered by the protection layer 1750. For example, the color filters 1760 may include a green filter G, a blue filter B and a red filter R, however, example embodiments are not limited thereto.

An upper planarization layer 1770 may be formed on the color filter array layer, the protection layer 1750 and the light blocking metal layer 1740, and a patterning process and a reflow process may be performed on the upper planarization layer 1770 in the first region I to form a microlens 1775. The microlens 1775 and the upper planarization process 1770 may include, e.g., a photoresist material having a high transmittance. The

A transparent protection layer 1780 may be formed on the microlens 1775 and the upper planarization layer 1770. The transparent protection layer 1780 may include, e.g., SiO, SiOC, SiC, SiCN, etc.

By the above processes, the fabrication of the CIS may be completed.

When the fourth and fifth substrates 1200 and 1400 are bonded with each other and when the third and fourth substrates 1100 and 1200 are bonded with each other, processes substantially the same as or similar to those illustrated with reference to FIGS. 23 to 28 may be performed, however, example embodiments are not limited thereto.

For example, when the fourth and fifth substrates 1200 and 1400 are bonded with each other, the fourth and fifth substrates 1200 and 1400 may be entirely bonded with each other by a single process, and when the third and fourth substrates 1100 and 1200 are bonded with each other, one of the third and fourth substrates 1100 and 1200, e.g., the third substrate 1100 may be divided into a plurality of portions. Additionally, a plurality of dicing processes may be performed so as to separate the plurality of portions of the third substrate 1100, and may be bonded with corresponding portions of the other one of the third and fourth substrates 1100 and 1200, e.g., the fourth substrate 1200.

Alternatively, when the fourth and fifth substrates 1200 and 1400 are bonded with each other, one of the fourth and fifth substrates 1200 and 1400 may be divided into a plurality of portions. Additionally, a plurality of dicing processes may be performed so as to separate the plurality of portions of the one of the fourth and fifth substrates 1200 and 1400, and may be bonded with corresponding portions of the other one of the fourth and fifth substrates 1200 and 1400.

While aspects of example embodiments have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: forming a first structure on a first wafer;forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions;separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process;bonding the first ones of the second chip regions with the first wafer;separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process;bonding the second ones of the second chip regions with the first wafer; andseparating the bonded first and second wafers by a third dicing process.

2. The method of claim 1, wherein the first wafer includes first chip regions and a first scribe lane region surrounding the first chip regions, and wherein the bonding the first ones of the second chip regions with the first wafer comprises bonding the first wafer and the second wafer such that the first ones of the second chip regions of the second wafer are aligned with corresponding ones of the first chip regions of the first wafer.

3. The method of claim 2, wherein the bonding the second ones of the second chip regions with the first wafer comprises bonding the first and second wafers such that the second ones of the second chip regions of the second wafer are aligned with corresponding ones of the first chip regions of the first wafer.

4. The method of claim 2, wherein the first structure includes a first bonding pattern in each of the first chip regions, and the second structure includes a second bonding pattern in each of the second chip regions, each of the first and second structures including a metal, and wherein the bonding the first ones of the second chip regions of the second wafer with the first wafer comprises bonding the first and second wafers such that the first and second bonding patterns contact each other.

5. The method of claim 4, wherein the bonding the second ones of the second chip regions of the second wafer with the first wafer comprises bonding the first and second wafers such that the first and second bonding patterns contact each other.

6. The method of claim 1, wherein the method further comprises: separating third ones of the second chip regions in a first edge portion of the second wafer in a plan view and bonding the third ones of the second chip regions with the first wafer; andseparating, prior to the third dicing process, fourth ones of the second chip regions in a second edge portion of the second wafer in a plan view by a fourth dicing process and bonding the fourth ones of the second chip regions with the first wafer.

7. The method of claim 1, wherein the method further comprises, prior to the third dicing process: forming a third structure on a third wafer including third chip regions and a third scribe lane region surrounding the third chip regions;separating third ones of the third chip regions in a central portion of the third wafer in a plan view by a fourth dicing process;bonding the third ones of the third chip regions with the second wafer;separating fourth ones of the third chip regions in an edge portion of the third wafer in a plan view by a fifth dicing process;bonding the fourth ones of the third chip regions with the second wafer; andseparating the bonded first and second wafers by the third dicing process comprises separating the bonded first, second and third wafers.

8. The method of claim 7, wherein the forming the first structure comprises forming elements for converting electronic signals into voltage signals on the first wafer, wherein the forming the second structure comprises forming pixels of an image sensor on the first wafer, andwherein the forming the third structure comprises forming a logic device on the third wafer.

9. The method of claim 1, wherein the forming the first structure comprises: forming a memory channel structure on the first wafer extending in a vertical direction substantially perpendicular to an upper surface of the first wafer; andforming a gate electrode structure including gate electrodes spaced apart from each other in the vertical direction on the first wafer, each of the gate electrodes surrounding the memory channel structure.

10. The method of claim 9, wherein the forming the second structure comprises: forming a transistor on the second wafer; andforming a wiring on the second wafer that is electrically connected to the transistor.

11. A method of manufacturing a semiconductor device, the method comprising: forming a first structure on a first wafer including first chip regions, a first scribe lane region surrounding the first chip regions, and a first bonding pattern in each of the first chip regions, the first bonding pattern including a metal;forming a second structure on a second wafer including second chip regions, a second scribe lane region surrounding the second chip regions, and a second bonding pattern in each of the second chip regions, the second bonding pattern including a metal;after separating second ones of the second chip regions in a first portion of the second wafer, bonding the second ones of the second chip regions with corresponding first ones of the first chip regions of the first wafer such that the second bonding pattern contacts the first bonding pattern;after separating fourth ones of the second chip regions in a second portion of the second wafer, bonding the fourth ones of the second chip regions with corresponding third ones of the first chip regions of the first wafer such that the second bonding pattern contacts the first bonding pattern; andseparating the bonded first and second wafers by a dicing process.

12. The method of claim 11, further comprising, prior to the dicing process and after separating sixth ones of the second chip regions in a third portion of the second wafer, bonding the sixth ones of the second chip regions with corresponding fifth ones of the first chip regions of the first wafer such that the second bonding pattern contacts the first bonding pattern.

13. The method of claim 11, further comprising, prior to the dicing process: forming a third structure on a third wafer including third chip regions, a third scribe lane region surrounding the third chip regions, and a third bonding pattern in each of the third chip regions, the third bonding pattern including a metal;after separating sixth ones of the third chip regions in a first portion of the third wafer, bonding the sixth ones of the third chip regions with corresponding fifth ones of the second chip regions of the second wafer such that the third bonding pattern contacts the second bonding pattern; andafter separating eighth ones of the third chip regions in a second portion of the third wafer, bonding the eighth ones of the third chip regions with corresponding seventh ones of the second chip regions of the second wafer such that the third bonding pattern contacts the second bonding pattern,wherein the dicing process comprises separating the bonded first, second and third wafers.

14. The method of claim 13, wherein the forming the first structure comprises forming elements for converting electronic signals into voltage signals on the first wafer, wherein the forming the second structure comprises forming pixels of an image sensor on the second wafer, andwherein the forming the third structure comprises forming a logic device on the third wafer.

15. The method of claim 11, wherein the forming the first structure comprises: forming a memory channel structure extending on the first wafer in a vertical direction substantially perpendicular to an upper surface of the first wafer; andforming a gate electrode structure including gate electrodes spaced apart from each other in the vertical direction on the first wafer, each of the gate electrodes surrounding the memory channel structure.

16. The method of claim 15, wherein the forming the second structure comprises: forming a transistor on the second wafer; andforming a wiring on the second wafer that is electrically connected to the transistor.

17. A method of manufacturing a semiconductor device, the method comprising: forming a first structure on a first wafer including first chip regions and a first scribe lane region surrounding the first chip regions;forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions;forming a third structure on a third wafer including third chip regions and a third scribe lane region surrounding the third chip regions;after separating second ones of the second chip regions in a first portion of the second wafer, bonding the second ones of the second chip regions with corresponding first ones of the first chip regions of the first wafer;after separating fourth ones of the second chip regions in a second portion of the second wafer, bonding the fourth ones of the second chip regions with corresponding third ones of the first chip regions of the first wafer;after separating sixth ones of the third chip regions in a first portion of the third wafer, bonding the sixth ones of the third chip regions with corresponding fifth ones of the second chip regions of the second wafer;after separating eighth ones of the third chip regions in a second portion of the third wafer, bonding the eighth ones of the third chip regions with corresponding seventh ones of the second chip regions of the second wafer; andseparating the bonded first, second and third wafers by a dicing process.

18. The method of claim 17, further comprising, prior to the dicing process and after separating tenth ones of the second chip regions in a third portion of the second wafer, bonding the tenth ones of the second chip regions with corresponding ninth ones of the first chip regions of the first wafer.

19. The method of claim 17, further comprising, prior to the dicing process and after separating tenth ones of the third chip regions in a third portion of the third wafer, bonding the tenth ones of the third chip regions with corresponding ninth ones of the second chip regions of the second wafer.

20. The method of claim 17, wherein the first structure includes a first bonding pattern in each of the first chip regions, and the second structure includes a second bonding pattern in each of the second chip regions, each of the first and second bonding patterns including a metal, and wherein after separating the second ones of the second chip regions of the second wafer and bonding the second ones of the second chip regions with the corresponding first ones of the first chip regions of the first wafer, the first and second wafers are bonded such that the first and second bonding patterns contact each other.

21-31. (canceled)