The present invention claim priority from Japanese Application No. 2003-352707 filed on Oct. 10, 2003, which is hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, more particularly, the invention relates to a method of manufacturing a semiconductor device that has transistors whose gate breakdown voltage and drain breakdown voltage are different and a Metal-Nitride-Oxide-Semiconductor (MNOS) type memory transistor in the same semiconductor layer.
2. Description of the Related Art
In a process of manufacturing a high-breakdown-voltage transistor, a high temperature process compared to that of a low-voltage driving transistor is needed in order to form a deep well and a thick gate insulating layer. Such high temperature process is specific for the low-voltage driving transistor, and generally, the high-breakdown-voltage transistor for a high voltage operation and the low-voltage driving transistor are formed separately.
At the same time, so called System on Chip (SOC) technology has been developed recently. The SOC technology is a technique in which a system function that previously was realized by combining several integrated circuits (IC) can be realized in a single IC chip.
The present invention is intended to provide a method of manufacturing a semiconductor device that has a MNOS memory transistor and a transistor whose gate breakdown voltage and drain breakdown voltage are different in the same semiconductor layer.
A method of manufacturing a semiconductor device of an embodiment of the present invention is a method of forming a transistor that has a high-breakdown-voltage transistor, a low-voltage driving transistor and a Metal-Nitride-Oxide-Semiconductor (MNOS) type memory transistor. The method includes a step of forming a stack film that includes at least an oxide silicon layer and a nitride silicon layer over a high-breakdown-voltage transistor forming region where the high-breakdown-voltage transistor is formed, a low-voltage driving transistor forming region where the low-voltage driving transistor is formed and a MNOS type memory transistor forming region where the MNOS type memory transistor is formed in a semiconductor layer, a step of removing the stack film formed in a first gate insulating layer forming region of the high-breakdown-voltage transistor and a step of forming a first gate insulating layer in the high-breakdown-voltage transistor forming region by thermal oxidation. The method also includes a step of removing the stack film formed in the low-voltage driving transistor forming region, a step of forming a second gate insulating layer in the low-voltage driving transistor forming region, a step of forming gate electrodes in the high-breakdown-voltage transistor forming region, the low-voltage driving transistor forming region and the MNOS type memory transistor forming region and a step of forming source/drain regions in the high-breakdown-voltage transistor forming region, the low-voltage driving transistor forming region and the MNOS type memory transistor forming region.
In the method of manufacturing a semiconductor device of one embodiment of the present invention, a Metal-Oxide-Nitride-Semiconductor (MNOS) type memory transistor includes a Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) type memory transistor. In other words, the stack film includes at least the oxide silicon layer and the nitride silicon layer. That is, the first oxide silicon layer, the nitride silicon layer and the second oxide silicon layer may be stacked in layers.
In the method of manufacturing a semiconductor device of an embodiment of the present invention, forming another specific layer (hereinafter called “layer B”) over a specific layer (hereinafter called “layer A”) includes a case in which the layer B is directly formed on the layer A and a case in which the layer B is formed on the layer A with at least one layer therebetween. Also, “source/drain region” means a source region and/or a drain region.
According to the above-mentioned method of manufacturing a semiconductor device of one embodiment of the present invention, the high-breakdown-voltage transistor, which requires a high temperature process compared with the low-voltage driving transistor in order to form a deep well and a thick gate insulating electrode, and the MONOS type memory transistor that requires a special stack film forming process can be provided together.
In the method of manufacturing a semiconductor device according to one embodiment of the invention, the stack film may be formed such that a first oxide silicon layer, a nitride silicon layer and a second oxide silicon layer are stacked in layers.
The method of manufacturing a semiconductor device may include a step of forming sacrificial oxide layer may be formed over the semiconductor layer before the stack film.
The method of manufacturing a semiconductor device may include a step of forming well in the low-voltage driving transistor forming region and the MONOS type memory transistor forming region before the first gate insulating layer is formed.
The method of manufacturing a semiconductor device may include a step of forming well in the low-voltage driving transistor forming region and the MONOS type memory transistor forming region after the first gate insulating layer is formed.
The method of manufacturing a semiconductor device may include a step of forming an isolation region in the high-breakdown-voltage transistor forming region by a Local Oxidation of Silicon (LOCOS) method and a step of forming isolation region in the low-voltage driving transistor forming region and the MONOS type memory transistor forming region by a trench isolation method.
In the method of manufacturing a semiconductor device according to one embodiment of the invention, the LOCOS method includes a recess LOCOS method and a semi-recess LOCOS method.
In the method of manufacturing a semiconductor device, the well may be formed in the low-voltage driving transistor forming region and the MONOS type memory transistor forming region before the isolation region is formed in the low-voltage driving transistor forming region and the MONOS type memory transistor forming region.
In the method of manufacturing a semiconductor device, the well may be formed in the low-voltage driving transistor forming region and the MONOS type memory transistor forming region after the isolation region is formed in the low-voltage driving transistor forming region and the MONOS type memory transistor forming region.
In the method of manufacturing a semiconductor device, the high-breakdown-voltage transistor may be formed to have an offset insulating layer.
In the method of manufacturing a semiconductor device, the offset insulating layer may be formed by a LOCOS method.
Preferred embodiment of the present invention will now be described with reference to the accompanying drawings.
1. Semiconductor Device
Firstly, a semiconductor device that is obtained by a manufacturing method of the present embodiment is described.
A semiconductor device includes a semiconductor layer 10. The semiconductor device has a high-breakdown-voltage transistor forming region 10HV, a low-voltage driving transistor forming region 10LV and a Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) type memory transistor forming region 10M (hereinafter called “MONOS forming region”). The high-breakdown-voltage transistor forming region 10HV includes an n-type high-breakdown-voltage transistor forming region 10HVn and a p-type high-breakdown-voltage transistor forming region 10HVp. The low-voltage driving transistor forming region 10LV includes an n-type low-voltage driving transistor forming region 10LVn and a p-type low-voltage driving transistor forming region 10LVp. The MONOS forming region 10M includes a p-type MONOS type memory transistor forming region 10Mp (hereinafter called “p-type MONOS forming region”).
An n-type high-breakdown-voltage transistor 100N is formed in the n-type high-breakdown-voltage transistor forming region 10HVn, and a p-type high-breakdown-voltage transistor 100P is formed in the p-type high-breakdown-voltage transistor forming region 10HVp. In the same way, an n-type low-voltage driving transistor 200N is formed in the n-type low-voltage driving transistor forming region 10LVn, and a p-type low-voltage driving transistor 200P is formed in the p-type low-voltage driving transistor forming region 10LVp. In the p-type MONOS forming region 10Mp, a p-type MONOS type memory transistor 300P is formed.
In other words, the n-type high-breakdown-voltage transistor 100N, the p-type high-breakdown-voltage transistor 100P, the n-type low-voltage driving transistor 200N, the p-type low-voltage driving transistor 200P and the p-type MONOS type memory transistor 300P are all provided on the same substrate (the same chip). Though only five transistors are depicted in
In the high-breakdown-voltage transistor forming region 10HV, the n-type high-breakdown-voltage transistor 100N and the p-type high-breakdown-voltage transistor 100P are formed. A first isolation region 110 (see
Next, structure of the n-type high-breakdown-voltage transistor 100N and the p-type high-breakdown-voltage transistor 100P is explained.
The n-type high-breakdown-voltage transistor 100N includes a first gate insulating layer 60, an offset insulating layer 20b that is made of the semi-recess LOCOS layer, a gate electrode 70, an n-type offset region 40, a side-wall insulating layer 72 and an n-type source/drain region 42.
The first gate insulating layer 60 is formed at least over a channel region within a p-type first well 32. The p-type first well 32 is formed within an n-type first well 30. The offset insulating layer 20b is provided at the both sides of the first gate insulating layer 60 and within the n-type offset region 40. The gate electrode 70 is formed at least on the first gate insulating layer 60. The n-type offset region 40 is formed within the p-type first well 32. The side-wall insulating layer 72 is formed on a side surface of the gate electrode 70. The side-wall insulating layer 72 includes, for example, an oxide silicon layer 74 whose shape of cross section is L-shaped and a nitride silicon layer 76 formed on the oxide silicon layer 74. The n-type source/drain region 42 is provided outside the side-wall insulating layer 72 and within the semiconductor layer 10.
The p-type high-breakdown-voltage transistor 100P includes the first gate insulating layer 60, the offset insulating layer 20b that is made of the semi-recess LOCOS layer, the gate electrode 70, a p-type offset region 50, the side-wall insulating layer 72 and a p-type source/drain region 52.
The first gate insulating layer 60 is formed at least over a channel region within the n-type first well 30. The offset insulating layer 20b is provided at the both sides of the first gate insulating layer 60 and within the p-type offset region 50. The gate electrode 70 is formed at least on the first gate insulating layer 60. The p-type offset region 50 is formed within the n-type first well 30. The side-wall insulating layer 72 is formed on the side surface of the gate electrode 70. The side-wall insulating layer 72 includes, for example, the oxide silicon layer 74 whose shape of cross section is L-shaped and the nitride silicon layer 76 formed on the oxide silicon layer 74. The p-type source/drain region 52 is provided outside the side-wall insulating layer 72 and within the semiconductor layer 10.
Next, the low-voltage driving transistor forming region 10LV is described. In the low-voltage driving transistor forming region 10LV, the n-type low-voltage driving transistor 200N and the p-type low-voltage driving transistor 200P are formed. A second isolation region 210 (see
Next, structure of each transistor is described.
The n-type low-voltage driving transistor 200N includes a second gate insulating layer 62, the gate electrode 70, the side-wall insulating layer 72, an n-type extension region 41 and the n-type source/drain region 42.
The second gate insulating layer 62 is formed at least over a channel region within a p-type second well 36. The gate electrode 70 is formed on the second gate insulating layer 62. The side-wall insulating layer 72 is formed on the side surface of the gate electrode 70. The side-wall insulating layer 72 includes, for example, the oxide silicon layer 74 whose shape of cross section is L-shaped and the nitride silicon layer 76 formed on the oxide silicon layer 74. The n-type extension region 41 is formed within the p-type second well 36. The n-type source/drain region 42 is provided outside the side-wall insulating layer 72 and within the semiconductor layer 10.
The p-type low-voltage driving transistor 200P includes the second gate insulating layer 62, the gate electrode 70, the side-wall insulating layer 72, a p-type extension region 51 and the p-type source/drain region 52.
The second gate insulating layer 62 is formed at least over a channel region within an n-type second well 34. The gate electrode 70 is formed on the second gate insulating layer 62. The side-wall insulating layer 72 is formed on the side surface of the gate electrode 70. The side-wall insulating layer 72 includes, for example, the oxide silicon layer 74 whose shape of cross section is L-shaped and the nitride silicon layer 76 formed on the oxide silicon layer 74. The p-type extension region 51 is formed within the n-type second well 34. The p-type source/drain region 52 is provided outside the side-wall insulating layer 72 and within the semiconductor layer 10.
Next, the MONOS forming region 10M is described. In the MONOS forming region 10M, the p-type MONOS type memory transistor 300P is provided. The p-type MONOS type memory transistor 300P includes a third gate insulating layer 64, the gate electrode 70, the side-wall insulating layer 72, the p-type extension region 51 and the p-type source/drain region 52.
The third gate insulating layer 64 is a film stack in which a first oxide silicon layer, a nitride silicon layer and a second oxide silicon layer are stacked in layers. A high electric field is produced in the first oxide silicon layer by a voltage applied to the third gate insulating layer 64, and a threshold voltage is modulated to perform a writing operation or an erasing operation by moving an electron back and forth between a semiconductor layer and an interface between the first oxide silicon layer and the nitride silicon layer directly with the tunnel effect. The interface between the first oxide silicon layer and the nitride silicon layer has an electron trap level, and information is recorded and held by trapping an electron there.
The third gate insulating layer 64 is formed at least over a channel region within an n-type third well 38. The gate electrode 70 is formed on the third gate insulating layer 64. The side-wall insulating layer 72 is formed on the side surface of the gate electrode 70. The side-wall insulating layer 72 includes, for example, the oxide silicon layer 74 whose shape of cross section is L-shaped and the nitride silicon layer 76 formed on the oxide silicon layer 74. The p-type source/drain region 52 is provided outside the side-wall insulating layer 72 and within the semiconductor layer 10.
Next, a method of manufacturing a semiconductor device of the present embodiment will be described with reference to
(1) First, as shown in
Next, an oxide nitride silicon layer is formed on the semiconductor layer 10 by chemical vapor deposition (CVD). The semiconductor layer 10 at least includes silicon and is made of silicon, silicon-germanium and the like. The semiconductor layer 10 may be a silicon layer in a bulk silicon substrate or a silicon on insulator (SIO) substrate. A thickness of the oxide nitride silicon layer is, for example, 8-12 nm. Then, a nitride silicon layer is formed on the oxide nitride silicon layer by CVD. And then, a resist layer that has an opening corresponding to where the semi-recess LOCOS layer 20a and the offset insulating layer 20b are formed is formed on the nitride silicon layer. Subsequently, a concave part is formed in a forming region of the semi-recess LOCOS layer 20a and the offset insulating layer 20b by etching the nitride silicon layer, the oxide nitride silicon layer and the semiconductor layer 10 using the resist layer as mask. Then, the resist layer is removed.
After that, as shown in
(2) Secondly, as shown in
Then, a resist layer R1 having a prescribed pattern is formed. After an n-type impurity such as phosphorus and arsenic is injected into the semiconductor layer 10 once or more than once using the resist layer R1 as a mask, the resist layer R1 is removed by, for example, ashing. And then, the impurity layer is diffused with a heat treatment and the n-type first well 30 is formed in the semiconductor layer 10.
(3) Next, as shown in
(4) Next, as shown in
(5) Subsequently, as shown in
(6) Then, as shown in
(7) Next, the second isolation region 210 is formed by forming a trench insulating layer 22 in the low-voltage driving transistor forming region 10LV and the MONOS forming region 10M (see
First, as shown in
(8) Next, a trench oxide film (not shown in
Subsequently, an insulating layer (not shown in
(9) Then, as shown
Then, a well is formed in the low-voltage driving transistor forming region 10LV and the MONOS forming region 10M. First, a resist layer is formed so as to cover the whole surface other than the p-type low-voltage driving transistor forming region 10LVp and the p-type MONOS forming region 10Mp. Then, the n-type second well 34 is formed in the p-type low-voltage driving transistor forming region 10LVp and the n-type third well 38 is formed on the p-type MONOS forming region 10Mp by injecting an n-type impurity such as phosphorus and arsenic once or more than once using the resist layer as a mask. An injection volume of the n-type impurity will be decided in consideration of a thermal diffusion volume of the n-type impurity in a step (13). In the step (13), the first gate insulating layer 60 of the high-breakdown-voltage transistor is formed. Details of the step (13) will be described later. Then, the resist layer is removed.
Subsequently, a resist layer is formed so as to cover the whole surface other than the n-type low-voltage driving transistor forming region 10LVn. Then, the p-type second well 36 is formed by injecting a p-type impurity such as boron once or more than once using the resist layer as a mask. An injection volume of the p-type impurity will be decided in consideration of a thermal diffusion volume of the p-type impurity in the later-described step (13). In the step (13), the first gate insulating layer 60 of the high-breakdown-voltage transistor is formed. Then, the resist layer is removed. After this, if necessary, channel-doping in the low-voltage driving transistor forming region 10LV and the MONOS forming region 10M may be performed.
Since the well is formed in the low-voltage driving transistor forming region 10LV and the MONOS forming region 10M before a step (11) in which a stack film 64a is formed, an impurity injection through the stack film 64a is not needed. Therefore, injection damage to the stack film 64a will be avoided and the impurity injection can be accurately performed. Details of the step (11) will be described later.
(10) Next, as shown in
(11) Then, as shown in
(12) Subsequently, a resist layer (not shown in the figures) is formed in the high-breakdown-voltage transistor forming region 10HV so as to cover the whole surface other than the first gate insulating layer 60 of the n-type high-breakdown-voltage transistor 100N and the first gate insulating layer 60 of the p-type high-breakdown-voltage transistor 100P (see
(13) Next, as shown in
(14) Then, a resist layer (not shown in the
(15) Subsequently, as shown in
(16) Then, as shown in
(17) Next, as shown in
(18) Then, as shown in
(19) Next, as shown in
(20) Then, as shown in
Next, the p-type source/drain region 52 is formed within the semiconductor layer 10 and outside the side-wall insulating layer 72 by injecting a p-type impurity into a certain area of the semiconductor layer 10 in the p-type high-breakdown-voltage transistor forming region 10HVp, the p-type low-voltage driving transistor forming region 10LVp and the p-type MONOS forming region 10Mp. The n-type source/drain region 42 can be formed by commonly-used way. The p-type source/drain region 52 can be formed by a commonly-used way.
The semiconductor device according to the present embodiment is manufactured through the above-mentioned steps. According to the method of forming a semiconductor device of the present invention, there are following features.
According to the method of manufacturing a semiconductor device of the present embodiment, the high-breakdown-voltage transistor, which requires a high temperature process compared with the low-voltage driving transistor in order to form a deep well and a thick gate insulating electrode, and the MONOS type memory transistor that requires a special stack film forming process can be provided together in the same substrate.
According to the method of forming a semiconductor device of the present embodiment, in the step (13), in which the first gate insulating layer 60 of the n-type high-breakdown-voltage transistor 100N and the p-type high-breakdown-voltage transistor 100P is formed by selective thermal oxidation, an area other than where the first gate insulating layer 60 is formed is covered with the stack film 64a. In other words, the stack film 64a serves as the anti-oxidation film. Therefore, the manufacturing steps can be simplified by using the stack film 64a, which is the insulating layer of the MONOS type memory transistor, as the anti-oxidation film, compared with a case in which a nitride silicon film is separately formed as the anti-oxidation film through another step.
The present invention is not limited to the embodiments described above but applied to various kinds of modifications within the scope and spirit of the present invention. For example, though the MONOS type memory transistor is explained in the above-described embodiment, a MNOS type memory transistor can be formed by the same manufacturing method. Stated another way, the stack film 64a may consist of at least two layers, which are the oxide silicon film and the nitride film.
Also, for example, in the above-described embodiment, the semi-recess LOCOS method is employed to form the offset insulating layer 20b. However, the offset insulating layer 20b can be formed by a LOCOS method or a recess LOCOS method.
Furthermore, for example, in the above-described embodiment, the well in the low-voltage driving transistor forming region 10LV and the MONOS forming region 10M is formed after the trench insulating layer 22 is formed. However, the well in the low-voltage driving transistor forming region 10LV and the MONOS forming region 10M may be formed before the trench insulating layer 22 is formed, in other words before the above-mentioned step (7).
Furthermore, for example, in the above-described embodiment, the well in the low-voltage driving transistor forming region 10LV and the MONOS forming region 10M is formed before the first gate insulating layer 60 in the high-breakdown-voltage transistor. However, the well in the low-voltage driving transistor forming region 10LV and the MONOS forming region 10M may be formed after the first gate insulating layer 60 is formed, in other words after the above-mentioned step (13). In such case, it is not necessary to perform impurity injection in advance in consideration of a thermal diffusion volume of the impurity. As a result, the depth of the well can be accurately controlled
Number | Date | Country | Kind |
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2003-352707 | Oct 2003 | JP | national |