1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device for low voltage operation, low power consumption, and high-speed operation, formed on an SOI substrate using an extremely thin film.
2. Description of the Related Art
A MOS semiconductor device formed on an SOI (Silicon On Insulator) substrate whose active layer has a thickness of 100 nm or less, can operate in a complete depletion mode, and can also operate at lower voltage compared to a conventional semiconductor device in which a bulk semiconductor substrate is used. Accordingly low power consumption and higher speed operation due to its small parasitic capacitance are attained.
When the thickness of the active layer is further reduced in order to improve performance of the semiconductor devices formed on an SOI substrate, a problem occurs in which the bottom of contact holes, which electrically connect a source and a drain of a MOS transistor with metal wirings, reaches an insulating film under the active layer at the time of the contact hole formation because the active layer is thin, resulting in insufficient contacts.
In order to solve the problem, for example, JP 05-326556 A discloses a method in which single crystal is grown on a source and a drain.
The structure shown in the prior art has a problem that a crystal defect may be generated in single crystal growth by variation in apparatus setting, and the crystal growth cannot be made stably. Further, it is also disadvantageous that an apparatus for single-crystal growth is expensive and therefore the cost of the semiconductor device manufactured by this apparatus is also high.
The present invention has been made in view of the above, and an object of the present invention is to provide a method of manufacturing a MOS semiconductor device which can be manufactured stably for low voltage operation, low power consumption, and high-speed operation, formed on an SOI substrate using an extremely thin film.
In order to achieve the object, the following means are adopted in the present invention. The present invention provides:
(1) A method of manufacturing a semiconductor device comprising the steps of: forming a first insulating film on a source and a drain of a MOS transistor formed in a single crystalline semiconductor on an insulating film; forming first contact holes selectively in the first insulating film on the source and the drain, respectively; depositing a polycrystalline silicon film; selectively ion implanting impurities by setting a peak of an impurity profile at an interface between the polycrystalline silicon film and the source and the drain; forming a second insulating film thereon; forming second contact holes selectively in the second insulating film; and forming a metal wiring thereon.
(2) A method of manufacturing a semiconductor device in which the polycrystalline silicon film has a thickness of from 50 nm to 200 nm.
(3) A method of manufacturing a semiconductor device in which the first insulating film has a thickness of from 50 nm to 200 nm.
(4) A method of manufacturing a semiconductor device in which, as the impurities, phosphorous is introduced into an NMOS region with a dosage of from 1×1015/cm2 to 5×1015/cm2, and boron or BF2 is introduced into a PMOS region with a dosage of from 1×1015/cm2 to 5×1015/cm2.
As described above, according to the manufacturing method disclosed in the present invention, a MOS semiconductor device which can be manufactured stably for low voltage operation, low power consumption, and high-speed operation, formed on an SOI substrate using an extremely thin film, is provided.
In the accompanying drawings:
Hereinafter, description will be made to an embodiment of a method of manufacturing a semiconductor device according to the present invention with reference to the drawings. FIGS. 1 to 3 show the method of manufacturing a semiconductor device in accordance with the embodiment of the present invention.
Wet etching is used to form the contact holes in the first insulating film. Since selective ratio of the oxide film to silicon in wet etching is extremely large, the contact holes do not reach the buried insulating film even if the active layer of the SOI is extremely thin. For this reason, wet etching is adopted. However, when the first insulating film 107 is thick, undesirable side etch in wet etching is large, which is not suited for the formation of fine patterns. The thickness of the first insulating film 107 should thus be reduced to 200 nm or less within such a range that retains insulation. If the first insulating film is excessively thin (50 nm or less), the thickness of the film is hardly controlled, and there arises a difficulty in insulation.
It is sufficient when the thickness of the polycrystalline silicon film 109 falls within a range in which the film does not disappear at the formation of second contact holes described later. When the polycrystalline silicon film 109 has a thickness of 50 nm or less, the film may disappear in the second contact hole formation; on the contrary, when the polycrystalline silicon film 109 has a thickness of 200 nm or more, there arises a difficulty in miniaturization.
Since the polycrystalline silicon film is deposited without doping, contact resistance between the non-doped polycrystalline silicon film and the source or drain is not low. Thus, the impurities are introduced into the polycrystalline silicon film, thereby lowering the contact resistance. In the NMOS region phosphorous ion as a dopant is implanted with a dosage of from 1×1015/cm2 to 5×1015/cm2. And in the PMOS region boron or BF2 ion as a dopant is implanted with a dosage of from 1×1015/cm2 to 5×1015/cm2. Acceleration energy in ion implantation is set such that a peak of a projection range is located at the interface between the source/drain and the polycrystalline silicon film to effectively lower the contact resistance.
It has been described that patterning of the polycrystalline silicon film is performed after ion implantation. However, patterning of the polycrystalline silicon film can be performed before ion implantation. Further, there may be a case where heat treatment is needed to activate the impurities at temperature of, for example, 800° C. to 900° C.
Dry etching is used to form the second contact holes. Since the polycrystalline silicon film with a sufficient thickness is provided on the source and the drain, there does not arise a problem in which the contact holes reach the buried insulating film, which has occurred in the prior art.
Using the above-described manufacturing method in the contact-hole formation for obtaining the electrical junction between the metal wiring and the source and drain, the contact holes do not reach the buried insulating film even if the active layer of the SOI becomes thin, since the polycrystalline silicon film is provided on the source and the drain surface. Stable manufacturing can therefore be attained.
The embodiment shows the so-called single drain structure for the MOS structure. However, the same manufacturing method can also be applied to an LDD (lightly doped drain) structure or a drain extension structure, and the same effects as those in the embodiment can also be obtained in each structure.
Further, the embodiment can be implemented by using the apparatus widely spread in manufacturing of semiconductors. There is no need to use an expensive apparatus.
Number | Date | Country | Kind |
---|---|---|---|
2004-207222 | Jul 2004 | JP | national |