Method of manufacturing semiconductor device

Abstract

A junction leak current of a transistor including a silicide layer provided on a source/drain region is to be suppressed. After forming a gate electrode over a chip-side surface of a silicon substrate, an insulating layer is formed over the gate electrode. The insulating layer is etched back so as to form a sidewall that covers the sidewall of the gate electrode, and a region adjacent to the sidewall on the chip-side surface of the silicon substrate, where a source/drain region is to be formed, is etched so as to form a generally horizontal scraped section on the chip-side surface. Then a dopant is implanted to the silicon substrate around the gate electrode, to thereby form the source/drain region. On the chip-side surface of the silicon substrate where the gate electrode is provided, a Ni layer is formed, so that the Ni layer is reacted with the silicon substrate thus to form a Ni-silicide layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment;

FIGS. 2A to 2C are cross-sectional views sequentially showing a manufacturing process of the semiconductor device of FIG. 1;

FIGS. 3A to 3C are cross-sectional views sequentially showing a manufacturing process of the semiconductor device of FIG. 1; and

FIGS. 4A to 4C are cross-sectional views showing a structure of a gate electrode of the semiconductor device according to the embodiment.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a gate electrode over a chip-side surface of a silicon substrate;forming an insulating layer over said gate electrode;forming a sidewall that covers the side of said gate electrode by etching back said insulating layer on said gate electrode and on said silicon substrate, and removing by etching a portion of said chip-side surface of said silicon substrate in a region adjacent to said sidewall where a source/drain region is to be formed, thereby forming a generally horizontal scraped section on said chip-side surface;ion-implanting a dopant to said silicon substrate around said gate electrode after forming said sidewall and said scraped section, thereby forming said source/drain region;forming a metal layer on said scraped section of said silicon substrate where said gate electrode is provided; andreacting said metal layer with said silicon substrate thereby forming a silicide layer on said source/drain region.

2. The method according to claim 1, further comprising: cleaning an entire surface of said silicon substrate with a chemical solution, after forming said source/drain region and before forming said metal layer on said scraped section.

3. The method according to claim 1, wherein said forming a sidewall and said forming a scraped section include:removing said insulating layer on said gate electrode and on said silicon substrate by etching back under a first condition thereby forming said sidewall and exposing said chip-side surface of said silicon substrate, andetching said silicon substrate under a second condition thereby forming said scraped section.

4. The method according to claim 3, wherein said second condition includes selectively etching silicon with respect to said insulating layer.

5. The method according to claim 1, wherein said metal layer contains nickel, and said silicide layer is a nickel silicide layer.

6. The method according to claim 4, wherein said forming a metal layer includes forming said metal layer thinner than a scraped depth of said scraped section from said chip-side surface.

7. The method according to claim 1, wherein said forming a sidewall and said forming a scraped section include scraping said silicon substrate adjacent to said gate electrode by a depth of 5 nm to 50 nm with respect to a region right under said gate electrode.

8. The method according to claim 1, further comprising: forming an source/drain extension region in said silicon substrate around said gate electrode, before said forming a sidewall and a scraped section.

9. The method according to claim 1, further comprising: heating said silicon substrate thereby activating said dopant, after said forming a source/drain region and before said forming a metal layer.