Patent Application
20120326278
The present invention relates the forming of indicia on semiconductor chips and masks used to form semiconductor chips.
Semiconductor chips often use indicia, such as identifying indicia or fiduciary marks, to identify the chip. The identifying indicia can include company names, company logos or the like. Such indicia are put on the semiconductor masks used to form layers of the semiconductor chip. The indicia can provide benefits under the United States semiconductor mask work law that allow for notice including the symbol “M” and an identification of the owners of the rights of a mask work.
As the size of the processes get smaller, the fabrication design requirements for the identifying indicia become more stringent. For example, Chemical-Mechanical-Polishing (CMP) steps put restrictions on the design such as requiring densities above a minimum value. Traditional indicias have a relatively low density. Further, in metallization layers, the traditional indicia also have relatively large connected metal regions or co-incident metal edges on separate metallization layers that can, in some cases, form cracks or allow metallization fragments become free in a CMP step and interfere with other parts of the chip.
Embodiments of the present invention use a mask with an indicia section having a field of separated polygon elements with a defined negative space providing the indicia. These separated polygon shapes can be automatically generated fill shapes. The mask forms such an indicia onto a layer of the semiconductor chip.
The new design avoids low density problems of the prior solutions. When the mask is used for a metallization layer, such a design also avoids the creation of large connected metal regions that may provide problems with CMP processes.
The produced separated polygon elements are drawn to satisfy design rules for minimum feature dimension or space from the closest neighbor polygon element
The mask can be for a metallization layer, polysilicon layer or other layer.
The indicia is viewable using a microscope to identify the mask and chips.
The mask is used to form a chip with an indicia section including a field of separated polygon elements in a layer with a defined negative space in the separated polygon elements providing an indicia. Another indicia section with another field of separated polygon elements for another layer from another mask can be at the same or another location on the chip.
The present invention improves chip or die yield by:
With shrinking technologies, planarization requirements are getting more stringent so that feature line-widths can be drawn with negligible variation on the die in the face of tight depth to focus requirements of the optical system.
Indicias or fiducials (fiduciary marks) on the die are typically used for die alignment marks or for establishing Company-proprietary identifying marks, logos and dates.
These marks traditionally use drawn alphabets, alpha-numeric's characters or even symbols, in a language of user's choice and must be visually or machine identifiable on masks, reticles and on different layers on the dies.
However, in order to avoid circuit level failures, the drawing of these marks needs to also conform to the design-rule for the particular submicron technology. The manufacturing limitations imposed by the design-rules are typically (and not limited to):
Certain fabrication design rules do allow for the masking of design rule violations over user created indicias or fiduciary marks. However, the mere presence of the indicia or fiduciary marks, as drawn, still poses a yield problem as stated above.
The proposed method:
This method eliminates the requirement to create design rule compliant drawn shapes for generation of indicia or fiduciary marks. Therefore, it eases the creation of identifiable indicia or fiduciary marks while simultaneously improving on the chip or die yield requirements as stated above.
The fabrication design rules require a topographically uniform layout for efficient planarization of layers on the die. The density-check routine in the design rules checker will flag non-uniform density areas that could potentially and adversely impact planarization during the CMP process. These areas can be filled in with design rule approved shapes (“fill-shapes”).
The “fill-shapes” are arrayed to fill the areas that are deficient in meeting the density requirements. The patterning in the array of “fill-shapes” does meet the mandated design-rule requirements stipulated by the Fabrication House.
The proposed method uses these arrays of fabrication design rule layer fill shapes to generate the outlines of the indicia or fiduciary marks.
The proposed method focuses on adhering to the planarization requirements by the Fabrication Design Rules.
It employs the selective removal of fill-shapes to reveal and contrast the intended indicia or fiduciary marks for legibility as an open area without fill-shapes forming the desired lettering or pattern.
Since “fill-shapes” are typically much smaller than the drawing shapes used in indicia or fiduciary mark creation, this proposed method maintains high planarization and uniform topography of the areas around the indicia or fiduciary marks and allows easy detection of intended characters and patterns.
By selective removal of “fill-shapes”, there is no extra effort entailed to comply with the difficult Fabrication Design Rule requirements associated with the generation of indicia or fiduciary marks.
The previous method of having to commit to draw indicia or fiduciary marks is hereby eliminated in the proposed method. As technology shrinks the difficulty in the generation of Design Rule compliant indicia or fiduciary shapes as exercised in the previous art cannot be understated.
As stated above, the large shapes of the indicia or fiduciary mark are counter productive in enhancing chip or die yields (thereby leading to wasted dies and lowering yields). The proposed method, on the other hand, uses selective removal of smaller “fill-shapes”, instead, that:
The foregoing description of preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
