Patent Application
20140062619
An integrated circuit is a semiconductor device that has a substrate of a semiconductor material on which a series of layers are deposited using photolithographic techniques. The layers are doped, polarized and attacked, so that electrical elements (e.g., resistances, capacitors, or impedances) or electronic elements (e.g., diodes or transistors) are produced. Subsequently other layers are deposited, which form the structure of interconnection layers necessary for electrical connections.
A chip may include a micro-electro-mechanical system (MEMS) device and an integrated circuit, where the integrated circuit may control the MEMS. There are various techniques for manufacturing a chip that includes both a MEMS and an integrated circuit. One technique includes fabricating MEMS devices within the interconnection layers of the integrated circuit using most or all interconnection layers. However, this technique leaves little room in the interconnection layers for routing to and from electronic elements also on the integrated circuit. As a result, any silicon area of the chip allocated to the MEMS device typically cannot be used for routing and, thus, adds to the silicon area required to fabricate the integrated circuit.
Accordingly, there is a need for a technique of fabricating MEMS devices within interconnection layers of an integrated circuit that allows for more judicious use of the silicon area of the chip.
Additionally, there is a need for low cost and CMOS integrated radio frequency (RF) filters, with high quality factors and very low insertion losses. Commercially available solutions, such as Surface Acoustic Wave (SAW) and Bulk Acoustic Wave (BAW) filters, are not CMOS integrated. Hence, they cannot be integrated with the transceivers and amplifiers, thereby raising manufacturing cost.
The systems and methods described herein address deficiencies in the prior art by enabling fabrication of MEMS devices within interconnection layers of an integrated circuit without using most or all interconnection layers. In particular, systems and methods described herein provide for fabricating a MEMS device within the interconnection layers of an integrated circuit using at most two layers of conductor material.
Additionally, RF filters using MEMS-based devices are described, which have low manufacturing cost and are CMOS integrated. In some embodiments, the RF filter includes an array of mechanically decoupled resonator elements. In some embodiments, the RF filters are tunable, and result in reduced part count, size, and manufacturing cost.
In one aspect, the systems and methods described herein provide for a method for manufacturing a chip including a MEMS-based radio frequency filter arranged in an integrated circuit. The method includes forming electronic elements on a semiconductor material substrate. The method further includes forming above the semiconductor material substrate a stack of interconnection layers including layers of conductor material separated by layers of dielectric material. The method further includes forming a radio frequency filter within the stack of interconnection layers by applying gaseous HF to the interconnection layers. The radio frequency filter formed includes a plurality of mechanically decoupled resonator elements.
In some embodiments, the chip is manufactured using a 180 nm or lower CMOS process. In some embodiments, the chip is manufactured using a 22 nm CMOS process, a 32 nm CMOS process, a 45 nm CMOS process, or a 65 nm CMOS process. In some embodiments, a portion of the radio frequency filter is made from tungsten.
In some embodiments, the radio frequency filter includes a sensor array of mechanically decoupled resonator elements. The sensor array is configured to collectively operate as a radio frequency filter. In some embodiments, the sensor array includes about 60 to about 200 resonator elements.
In some embodiments, the sensor array is densely formed in a small area of the interconnection layers to reduce frequency mismatch between the resonator elements in the sensor array. In some embodiments, the sensor array has a Q factor of 100 or higher. In some embodiments, the sensor array has a Q factor ranging from about 5 to about 20.
In some embodiments, the plurality of resonator elements are calibrated using an external clock. In some embodiments, the plurality of resonator elements are different sizes, and each resonator element is configured to be turned on or off. In some embodiments, the radio frequency filter is configured for UMTS frequency range, GSM frequency range, LTE frequency range, cellular frequency range, Wifi frequency range, or any other suitable frequency range.
In some embodiments, the resonator elements are electrically connected in series. In some embodiments, the resonator elements are electrically connected in parallel. In some embodiments, the resonator elements are physically positioned in a configuration corresponding to one of a line, a square, and a grid. In some embodiments, the chip includes a controller for adjusting a voltage applied to one or more resonator elements to adjust a resonant frequency of the radio frequency filter.
In some embodiments, forming a resonator element includes forming a movable bridge and at least one capacitance electrode spaced away from the movable bridge by a first distance to form an initial gap within the resonator element. In some embodiments, the method further includes forming at least one mechanical stopper within the resonator element, the mechanical stopper extending beyond the at least one capacitance electrode by a second distance. In some embodiments, the method further includes applying an actuating voltage to at least one actuating electrode to move the movable bridge into contact with the at least one mechanical stopper to form an operating gap equal to about the second distance between the movable bridge and the at least one capacitance electrode. In some embodiments, the operating gap is less than or equal to about any one of 1 nm, 5 nm, 10 nm, 20 nm, 50 nm, and 100 nm. In some embodiments, the method further includes applying the actuating voltage after installation of the chip within a consumer electronic device.
In another aspect, the systems and methods described herein provide for a chip including a MEMS-based radio frequency filter arranged in an integrated circuit according to the description above. Furthermore, it should be noted that the systems and methods described above may be applied to, or used in accordance with, other systems and methods described elsewhere in this disclosure.
In some embodiments, a chip includes a MEMS device formed within a stack of interconnection layers of an integrated circuit. The stack includes, e.g., six layers of conductor material separated by six layers of dielectric material, where the top layer is a layer of conductor material (sometimes referred to as the capping). The MEMS device is formed within the stack of interconnection layers by applying gaseous HF to at least a layer of dielectric material positioned highest in the stack. As a result, the MEMS device is released within the two layers of conductor material highest in the stack. However, the remaining layers of dielectric material are unetched, and one or more of the remaining layers of conductor material may be used for routing connections. Accordingly, a MEMS device may be fabricated within a stack of interconnection layers of an integrated circuit while still allowing for routing connections within the lower layers of the stack, thereby reducing silicon area needed for the chip.
The described approach may also be beneficial for fabricating a MEMS device within a stack of interconnection layers of an integrated circuit when using complementary metal oxide semiconductor (CMOS) fabrication processes including low-k dielectric materials, e.g., 130 nm or lower CMOS processes. Low-k dielectric materials have a dielectric constant lower than silicon dioxide, and are typically difficult to etch compared to silicon dioxide when using, e.g., gaseous HF. A layer of silicon dioxide dielectric material may be included as the highest layer of dielectric material in the stack, while the remaining layers may include low-k dielectric material. The MEMS device may be formed within the stack of interconnection layers by applying gaseous HF to the layer of silicon dioxide dielectric material, without need for etching any of the layers of low-k dielectric material. Additionally, etching using gaseous HF may provide relatively uniform results, and provide higher yield when fabricating such MEMS devices. Etching fewer layers during fabrication may also reduce etching byproducts and reduce risk of corrosion to the MEMS device, thereby improving long-term reliability.
The described approach also offers certain other advantages. For example, any supporting anchors for the MEMS device may require less area within the interconnection layers due to the MEMS device being partially supported by the unetched layers in the stack. This may also reduce parasitic capacitances typically observed when a MEMS device is fabricated within most or all interconnection layers of an integrated circuit.
In certain cases, a MEMS device fabricated within interconnection layers of an integrated circuit using the described approach may not have the sensitivity required for its intended application. This is because the MEMS element released from the layers of conductor material may not have a sufficient length or mass. For example, a MEMS accelerometer may require a certain proof mass for use in its intended environment. In order to achieve a critical mass or length for the MEMS device to have the target sensitivity, an array of MEMS devices may be fabricated within the interconnection layers. For example, an array of MEMS accelerometers having a appropriate combined proof mass may be used as an accelerometer having the required proof mass.
Furthermore, due to silicon area savings from the described approach, multiple arrays of MEMS devices may be fabricated in the interconnection layers and disposed above an application specific integrated circuit (ASIC) that can selectively control the arrays. In some embodiments, multiple arrays each having a different type of MEMS device are fabricated and then the ASIC may switch between each array as required. For example, a reconfigurable motion sensor cell may be formed that includes an accelerometer array, a gyroscope array, and a magnetometer array fabricated within the interconnection layers of the ASIC. The motion sensor cell's ASIC may then select whether the motion sensor cell should offer the functionality of an accelerometer, a gyroscope, or a magnetometer.
In some embodiments, a single type of MEMS device is fabricated above the ASIC. Certain devices may be initially unused and reserved for redundancy in case of failure of another in-use device. In case of failure of a device due to issues during fabrication, the redundant device may help improve yield. In case of failure of a device during operation, the redundant device may help improve long-term reliability. In some embodiments, a hybrid motion sensor is built having redundant elements as well multiple types of device arrays, thereby offering the combined benefits of reconfigurability, redundancy, and reliability.
In one aspect, the systems and methods described herein provide for a method for manufacturing a chip including MEMS devices arranged in an integrated circuit. The method includes forming electronic elements on a semiconductor material substrate. The method further includes forming above the semiconductor material substrate a stack of interconnection layers including layers of conductor material separated by layers of dielectric material. The method further includes forming MEMS devices within the stack of interconnection layers by applying gaseous HF to a first layer of dielectric material positioned highest in the stack of interconnection layers, while allowing at least one layer of dielectric material to remain unetched, and allowing at least one layer of conductor material for routing connections to and from the electronic elements.
In some embodiments, the unetched layer of the dielectric material is the lowest layer of the dielectric material in the stack. In some embodiments, the chip is manufactured using a 180 nm or lower CMOS process. In some embodiments, the chip is manufactured using one of a 22 nm CMOS process, a 32 nm CMOS process, a 45 nm CMOS process, and a 65 nm CMOS process.
In some embodiments, the highest layer of conductor material in the stack includes aluminum. In some embodiments, the first layer of dielectric material includes silicon dioxide. In some embodiments, the method further includes forming at least one anchor within the layers of conductor material for supporting a MEMS device or a top layer of the plurality of layers of conductor material.
In some embodiments, the MEMS devices are of a same type. In some embodiments, the MEMS devices comprises a first device and second device, and the second device is reserved for redundancy in case of failure of the first device. In some embodiments, the MEMS devices are of different types including a magnetometer, a gyroscope, or an accelerometer.
In some embodiments, the MEMS devices include a sensor array of MEMS devices that is configured to collectively operate as a resonator. In some embodiments, the sensor array includes about 60 to about 200 MEMS devices. In some embodiments, the sensor array includes a first set of MEMS devices configured to collectively operate as a first type of device and a second set of MEMS devices configured to collectively operate as a second type of device. The sensor array is reconfigurable from operating as the first type of device to operating as the second type of device. In some embodiments, the sensor array is densely formed in a small area of the interconnection layers to reduce frequency mismatch between the MEMS devices in the sensor array. In some embodiments, the sensor array has a Q factor of 100 or higher. In some embodiments, the sensor array has a Q factor ranging from about 5 to about 20.
In another aspect, the systems and methods described herein provide for a chip including electronic elements formed on a semiconductor material substrate. The chip further includes above the semiconductor material substrate a stack of interconnection layers including layers of conductor material separated by layers of dielectric material. MEMS devices are formed within the stack of interconnection layers by applying gaseous HF to a first layer of dielectric material positioned highest in the stack of interconnection layers, while allowing for at least one unetched layer of dielectric material to remain unetched, and allowing at least one layer of conductor material for routing connections to and from the electronic elements.
In some embodiments, the unetched layer of the dielectric material is the lowest layer of the dielectric material in the stack. In some embodiments, the chip is manufactured using a 180 nm or lower CMOS process. In some embodiments, the chip is manufactured using one of a 22 nm CMOS process, a 32 nm CMOS process, a 45 nm CMOS process, and a 65 nm CMOS process.
In some embodiments, the highest layer of conductor material in the stack includes aluminum. In some embodiments, the first layer of dielectric material includes silicon dioxide. In some embodiments, the chip further includes at least one anchor within the layers of conductor material for supporting a MEMS device or a top layer of the plurality of layers of conductor material.
In some embodiments, the MEMS devices are of a same type. In some embodiments, the MEMS devices comprises a first device and second device, and the second device is reserved for redundancy in case of failure of the first device. In some embodiments, the MEMS devices are of different types including a magnetometer, a gyroscope, or an accelerometer.
In some embodiments, the MEMS devices include a sensor array of MEMS devices that is configured to collectively operate as a resonator. In some embodiments, the sensor array includes about 60 to about 200 MEMS devices. In some embodiments, the sensor array includes a first set of MEMS devices configured to collectively operate as a first type of device and a second set of MEMS devices configured to collectively operate as a second type of device. The sensor array is reconfigurable from operating as the first type of device to operating as the second type of device. In some embodiments, the sensor array is densely formed in a small area of the interconnection layers to reduce frequency mismatch between the MEMS devices in the sensor array. In some embodiments, the sensor array has a Q factor of 100 or higher. In some embodiments, the sensor array has a Q factor ranging from about 5 to about 20.
In yet another aspect, the systems and methods described herein provide for a method for manufacturing a chip including MEMS devices arranged in an integrated circuit. The method includes forming electronic elements on a semiconductor material substrate. The method further includes forming above the semiconductor material substrate a stack of interconnection layers including layers of conductor material separated by layers of dielectric material. The method further includes forming the MEMS devices within the stack of interconnection layers by applying gaseous HF to a first layer of dielectric material positioned highest in the stack of interconnection layers, while allowing at least one layer of dielectric material to remain unetched. The chip is manufactured in a CMOS process including low-k dielectric material having a dielectric constant lower than silicon dioxide. The first layer of dielectric material includes silicon dioxide and the at least one unetched layer of dielectric material includes low-k dielectric material. In some embodiments, the CMOS process is a 130 nm or lower CMOS process.
In yet another aspect, the systems and methods described herein provide for a chip including MEMS devices arranged in an integrated circuit. The chip includes electronic elements formed on a semiconductor material substrate. The chip further includes produced above the semiconductor material substrate a stack of interconnection layers including layers of conductor material separated by layers of dielectric material. The chip further includes MEMS devices formed within the stack of interconnection layers by applying gaseous HF to a first layer of dielectric material positioned highest in the stack of interconnection layers, while allowing at least one layer of dielectric material to remain unetched. The chip is manufactured in a CMOS process including low-k dielectric material having a dielectric constant lower than silicon dioxide. The first layer of dielectric material includes silicon dioxide and the at least one unetched layer of dielectric material includes low-k dielectric material. In some embodiments, the CMOS process is a 130 nm or lower CMOS process.
In yet another aspect, the systems and methods described herein provide for a MEMS resonator device including a resonator element, a supporting member attached to the resonator element, and a calibration element disposed proximate to the resonator element. The resonator element is calibrated based on a magnetic field generated on passing current through the calibration element.
In some embodiments, the resonator element is formed within a first layer of conductor material, and the calibration element is formed within a second adjacent layer of conductor material. The resonator element is further calibrated based on a capacitance generated between the first layer of conductor material and the second layer of conductor material. The capacitance aids in determining a distance between the calibration element and the resonator element.
In some embodiments, the MEMS resonator device further includes a first capacitive element disposed within the first layer of conductor material, and a second capacitive element disposed within the second adjacent layer of conductor material. The resonator element is further calibrated based on a first capacitance of the first capacitive element. The first capacitance aids in determining a thickness of the first layer of conductor material. The resonator element is further calibrated based on a second capacitance of the second capacitive element. The second capacitance aids in determining a thickness of the second layer of conductor material.
In some embodiments, the calibration element includes a metal wire disposed proximate to the resonator element in a parallel fashion. In some embodiments, the calibration element includes an inductor disposed proximate to the resonator element. In some embodiments, a portion of the calibration element is disposed in an unetched layer of dielectric material. In some embodiments, the resonator element includes a magnetometer, and calibrating the resonator element includes calibrating a gain of the magnetometer.
In yet another aspect, the systems and methods described herein provide for a method of calibrating a MEMS resonator device. The MEMS resonator device includes a resonator element formed within a first layer of conductor material, a supporting member attached to the resonator element, and a calibration element formed within a second adjacent layer of conductor material. The calibration element disposed proximate to the resonator element. The method includes applying a current to the calibration element to generate a magnetic field, and measuring a capacitance generated between the first layer of conductor material and the second layer of conductor material. The capacitance aids in determining a distance between the calibration element and the resonator element. The method further includes calibrating the resonator element based on the magnetic field and the measured capacitance.
In some embodiments, the MEMS resonator device includes a first capacitive element disposed within the first layer of conductor material, and a second capacitive element disposed within the second adjacent layer of conductor material. The method further includes calibrating the resonator element based on a first capacitance of the first capacitive element. The first capacitance aids in determining a thickness of the first layer of conductor material. The method further includes calibrating the resonator element based on a second capacitance of the second capacitive element. The second capacitance aids in determining a thickness of the second layer of conductor material.
In yet another aspect, the systems and methods described herein provide for a method for manufacturing a chip including anchors arranged in an integrated circuit. The method includes forming electronic elements on a semiconductor material substrate. The method further includes forming a stack of interconnection layers above the semiconductor material substrate. The stack of interconnection layers includes layers of conductor material separated layers of dielectric material. The method further includes forming the anchors within the stack of interconnection layers by applying gaseous HF to a first layer of dielectric material in the stack of interconnection layers, while allowing a layer of dielectric material to remain unetched, and allowing a layer of conductor material for routing connections to and from the electronic elements. Each anchor includes conductor layer portions from the layers of conductor material separated by vias. Each anchor supports a top layer of conductor material or a MEMS device formed within the stack of interconnection layers.
In some embodiments, a portion of an anchor includes dielectric material that replaces conductor material or via. In some embodiments, an anchor is formed according to a CMOS process design rule violation. The design rule violation may include conductor layer portions and vias that are substantially similar in width and do not overlap. The design rule violation may include vias that are wider than a width according to the CMOS process.
In yet another aspect, the systems and methods described herein provide for a chip including anchors arranged in an integrated circuit. The chip includes electronic elements formed on a semiconductor material substrate. The chip further includes a stack of interconnection layers formed above the semiconductor material substrate. The stack of interconnection layers includes layers of conductor material separated layers of dielectric material. The chip further includes the anchors formed within the stack of interconnection layers by applying gaseous HF to a first layer of dielectric material in the stack of interconnection layers, while allowing a layer of dielectric material to remain unetched, and allowing a layer of conductor material for routing connections to and from the electronic elements. Each anchor includes conductor layer portions from the layers of conductor material separated by vias. Each anchor supports a top layer of conductor material or a MEMS device formed within the stack of interconnection layers.
In some embodiments, a portion of an anchor includes dielectric material that replaces conductor material or via. In some embodiments, an anchor is formed according to a CMOS process design rule violation. The design rule violation may include conductor layer portions and vias that are substantially similar in width and do not overlap. The design rule violation may include vias that are wider than a width according to the CMOS process.
Other advantages and characteristics of the systems and methods described herein may be appreciated from the following description, which provides a non-limiting description of illustrative embodiments, with reference to the accompanying drawings, in which:
To provide an overall understanding of the systems and methods described herein, certain illustrative embodiments will now be described. However, it will be understood by one of ordinary skill in the art that the systems and methods described herein may be adapted and modified as is appropriate for the application being addressed and that the systems and methods described herein may be employed in other suitable applications, and that such other additions and modifications will not depart from the scope thereof.
The configuration of
The configurations described with respect to
Additionally, etching using gaseous HF may provide relatively uniform results, and provide higher yield when fabricating such MEMS devices. Etching fewer layers during fabrication may also reduce etching byproducts and reduce risk of corrosion to the MEMS device, thereby improving long-term reliability. In some embodiments, a time based stop may be used to limit etching of the interconnection layers by gaseous HF. Without adding any complex structures as described with respect to
The configurations described with respect to
Described below are process flow steps for fabricating a MEMS device of an array via a CMOS MEMS-based process. For example, the MEMS device may be fabricated using a CMOS MEMS-based process described in commonly-owned U.S. Patent Application Publication No. 2010/0295138, entitled “Methods and Systems for Fabrication of MEMS CMOS Devices.” However, fabrication processes for the MEMS device need not be limited to CMOS MEMS-based processes, and may include MEMS-based processes, NEMS-based processes, and other suitable processes.
In some embodiments, a MEMS device is arranged in an integrated circuit. The process flow steps of
Additionally, the proposed configuration may require anchors 556 for supporting the capping 552, and ensuring that the capping 552 does not bend and damage the MEMS device. In some embodiments, a dense array of anchors 556 is required to support the capping 552. In addition to supporting capping 552, anchors 558 may be used to support the MEMS device. However, need for these anchors may be eliminated by simply burying the MEMS device in a dielectric layer (e.g., silicon dioxide), which is illustrated in
Furthermore, due to silicon area savings from the described approach, multiple arrays of MEMS devices may be fabricated in the interconnection layers and disposed above an application specific integrated circuit (ASIC) that can selectively control the arrays. In some embodiments, a single type of MEMS device is fabricated above the ASIC. Certain devices may be initially unused and reserved for redundancy in case of failure of another in-use device. In case of failure of a device due to issues during fabrication, the redundant device may help improve yield. In case of failure of a device during operation, the redundant device may help improve long-term reliability.
In some embodiments, a metal layer is etched using a time based stop to form a MEMS device having a moveable plate and attached springs. Since the MEMS device is formed from a single metal layer, a typical moveable plate may bend or collapse with an electrode or surrounding oxide. In such a case, the moveable plate can be split into multiple smaller moveable plates. Consequently, an array of MEMS devices each having a moveable plate and attached springs may be built. Such an array will have an effectively higher stiffness due to the combined stiffness of the springs. However, soft springs may be used to counter the stiffness (described further with respect to
In some embodiments, the MEMS devices include a sensor array of MEMS devices that is configured to collectively operate as a resonator. In some embodiments, the sensor array includes about 60 to about 200 MEMS devices. In some embodiments, the sensor array is densely formed in a small area of the interconnection layers to reduce frequency mismatch between the MEMS devices in the sensor array. In some embodiments, the sensor array has a Q factor of 100 or higher. In some embodiments, the sensor array has a Q factor ranging from about 5 to about 20.
In some embodiments, the MEMS array is used to build a gyroscope. Such a gyroscope may require a large proof mass to be implemented using the MEMS technology. In embodiments where structural layers produced via the MEMS technology are thin, an array of small elements or devices may be produced to provide an effect similar to that of a large proof mass. Such a gyroscope may further require autocalibration to compensate for, e.g., mechanical properties that may change with temperature, aging, usage, and production. In some embodiments, values of the proof mass and capacitances of the gyroscope may be measured and stored, while other parameters, such as vertical and lateral stiffness, may be autocalibrated. In some embodiments, an autocalibration algorithm may be used that does not need measurement or calibration of the proof mass and capacitances.
In some embodiments, the MEMS array is used to build a magnetometer. The magnetometer may be made with an array of small devices (or elements). The array of small devices may minimize bending of structural layers. The array of small devices may simplify etching by, for example, allowing the etching to be shorter and more controllable. Such an array of small devices may provide an aggregate large mass and/or area. The array may allow sensing physical magnitudes with the appropriate sensitivity, and may provide higher reliability than one or more big devices. In some embodiments, the small devices in the array may be nano-magnetometers.
Since each MEMS device 682 is formed from a single metal layer, a typical moveable plate may bend or collapse with an electrode or surrounding oxide. In such a case, the moveable plate can be split into multiple smaller moveable plates. Consequently, an array of MEMS devices each having a moveable plate and attached springs may be built. Such an array will have an effectively higher stiffness due to the combined stiffness of the springs. However, soft springs may be used to counter the stiffness. Such soft springs are fabricated as thin one-layer springs, which are attached to the moveable plate, and bend together with the moveable plate. As such, since there is no rigid portion to add stiffness, even the combined stiffness of the soft springs may be suitable for allowing the multiple moveable plates to operate together as a single device.
For those devices requiring a large quality factor, Q, e.g., a magnetometer or a gyroscope, if the elements of the array are mechanically decoupled, the Q factor of the array will be low due to the frequency mismatch of the individual elements. The frequency mismatch may result due to process tolerance and different history of use for each individual element. A low Q of the array despite having a high Q of the individual elements may be advantageous in the design of accelerometers, where typically there is a trade off between the high Q required to reduce the brownian noise and the low Q required to reduce a ringing response to a step function and the amplification of high frequency vibrations. With these arrays of mechanically decoupled elements, we can have a high Q for the individual elements, which is what matters to reduce brownian noise, and a low Q of array, which is what matters to avoid amplification of the high frequency vibrations and the ringing of the step response. Applicants have experimentally observed that the values of Q of the array are enough to achieve the sensitivity specs for compelling motion sensors in the consumer space.
Building an array of mechanically coupled elements may be challenging in the case of a magnetometer. Since each element is formed from a single metal layer, any mechanical coupling may electrically short circuit the elements, and the current may not flow in the intended direction. In some embodiments, the elements are joined by means of a high density sublayer of silicon oxide, which will remain unetched while a low density sublayer of oxide will be removed in the same area while the high density sublayer will remain unetched. In order to facilitate etching of a low density sublayer beneath a lower conductor layer, a column may be placed just below a release hole of the top conductor layer. Applicants have observed that such a column may advance gaseous HF faster vertically below the lower conductor layer, and help horizontally etch the target low density sublayer.
In some embodiments, the elements are joined by means of oxide of a metal-insulator-metal (MIM) layer, e.g., silicon nitride enriched with silicon, which may not be etched away easily along with silicon nitride. This may require the addition of MIM capacitors to the array to be implemented between a top conductor layer and a second adjacent conductor layer. In some embodiments, a silicon nitride sublayer found within the inter-metal dielectric layer of certain CMOS processes (e.g., 130 nm or lower CMOS process) is used instead of a MIM layer.
The resonator element 882 is formed within a first layer of conductor material. The calibration element 888 is formed within a second adjacent and lower layer of conductor material. The resonator element 882 is further calibrated based on a capacitance generated between the first layer of conductor material and the second layer of conductor material. The capacitance aids in determining a distance between the calibration element and the resonator element.
In some embodiments, the MEMS resonator device 880 further includes a first capacitive element disposed within the first layer of conductor material, and a second capacitive element disposed within the second adjacent layer of conductor material. The resonator element 882 is further calibrated based on a first capacitance of the first capacitive element. The first capacitance aids in determining a thickness of the first layer of conductor material. The resonator element 882 is further calibrated based on a second capacitance of the second capacitive element. The second capacitance aids in determining a thickness of the second layer of conductor material.
In some embodiments, the resonator element includes a magnetometer, and calibrating the resonator element includes calibrating a gain of the magnetometer. However, in addition to the gain, an offset of the magnetometer may need to be calibrated as well. This may be desirable to avoid a high offset that saturates the detection chain, or requires an unfeasible front end with an unrealistic high dynamic range and to avoid a constant or fixed error in the output.
There may be two sources of magnetometer offset. The first source may be the electronic elements. This offset may be measured by turning off the Lorentz current, such that no magnetic force is generated. The second source may be electrostatic force that is added to the magnetic force. The electrostatic force is proportional to the square of the voltage. If there is a DC and a AC voltage component (Vdc and Vac) at frequency f0, the square will generate electrostatic force components at DC, f0 and 2*f0. The magnetic force will only have a component at f0 (since the Lorentz current is an AC current at f0, the resonant frequency of the resonator element). Therefore, there is a component of the electrostatic force that will sum with the magnetic force, adding an offset, since this will be a constant term irrespective of the magnetic force.
This term of the electrostatic force at f0 is proportional to Vdc*Vac. Since Vac appears because of the voltage drop of the Lorentz current through the resistances of the resonator element, it cannot be eliminated. Instead Vdc may be reduced as close to zero as possible. For example, a Vdc of 10 uV may suffice in order to have a contribution almost below the noise level of the magnetometer having about 1 uT. A problem may be that the offset of electronic elements is typically in the 20-50 mV, so it may not be possible to control that DC voltage, at least in an open loop.
In some embodiments, a digital-to-analog converter (DAC) may be used to try different voltages until we arrive at the required voltage. In order to determine the required DC voltage from the DAC such that Vdc is close to zero (e.g., between about −10 uV and about +10 uV), we sense the effect of Vdc. This may be accomplished by placing an electrode, either below the resonator element (for out-of plane vibration, i.e., X or Y magnetic field components) or parallel to the resonator element (for in-plane vibration, i.e., Z magnetic field component). The electrode may be actuated electrostatically with an AC signal at a frequency fc, such that the bridge has some deflection at this frequency fc. This modulates the electrostatic force component but not the magnetic component, helping distinguish the two components. Subsequently, the voltage of the DAC is adjusted such that this spectral component of the current sensed, which will be located at a fc distance from the magnetic force, is minimized. Alternatively, determining the required DC voltage may be accomplished by adding a DC voltage, applying two different voltages, and solving a system of equations to solve for the required voltage value.
RF filters, e.g., in cell phone applications and UMTS communications, are typically required to have losses less than 3 dB and attenuations of more than 50 dB with narrow passbands. This may imply a quality factor, Q, on the order of 100 at the frequency range of 0.8 GHz to 3 GHz. Due to these demanding specifications, such filters cannot be implemented using passive LC filters because of the high Q required. In other words, inductors and capacitors, especially if they are integrated in a CMOS chip, result in resistances that degrade the quality factor and/or insertion losses of the filter, thus not being a viable option. These filters cannot be implemented digitally either because in transmission they need to handle power signals, and in reception the power consumption requirement would be huge since we cannot reduce the signal bandwidth until we apply the RF filter.
Typically such RF filters are implemented using SAW and BAW filters. SAW (Surface Acoustic Wave) filters are electromechanical devices where electrical signals are converted to a mechanical wave in a device constructed of a piezoelectric crystal or ceramic.
An evolution of SAW filters are BAW (Bulk Acoustic Wave) filters. BAW filters can implement ladder or lattice filters. BAW filters typically operate at frequencies from 2 to 16 GHz, and may be smaller or thinner than equivalent SAW filters. One important variant of BAW filters is FBAR (Thin Film Bulk Acoustic Resonator). This is a device consisting of a piezoelectric material sandwiched between two electrodes and acoustically isolated from the surrounding medium. FBAR devices using piezoelectric films with thicknesses ranging from several micrometres down to tenth of micrometres resonate in the frequency range of about 100 MHz to 10 GHz. Aluminum nitride and zinc oxide are two common piezoelectric materials used in FBARs.
Another approach to build high performance RF filters is using micromechanical resonators by means of MEMS technology. Unfortunately the frequencies of these resonators may be fairly low, typically in the 10 kHz-10 MHz range, and may need active transimpedance amplifiers to sense the tiny currents that they generate. This may limit its applicability to cell phone applications, which require passive filters around 1 GHz.
Unlike what is done in conventional filters, where the signal either goes through it or it is bounced back depending on its frequency content,
In some embodiments, the filters described in
In some embodiments, a DC voltage is applied to the resonators elements to turn the filter on and off, as required. Due to process variation or otherwise, it may be possible to have resonator elements with different sizes and hence different resonant frequencies across the array. This would enable the characterization of a filter with any desired shape. And this shape could be tunable if the design is such that we can apply different voltage (typically on or off) to the different resonator sizes. However, if desired, the sensor array may be densely formed in a small area of the interconnection layers to reduce frequency mismatch between the resonator elements in the sensor array.
In some embodiments, the systems and methods described herein provide for a filter having a large array of mechanically decoupled resonators. Such a filter may accommodate large resonant frequencies while maintaining small device size. Since small devices have small electromechanical coupling and large motional resistance, a large array may be built having these resonator elements placed in parallel. This may reduce the total motional resistance, since this will be inversely proportional to the number of resonator elements in parallel. In some embodiments, the resonator elements are arranged in series, a square, or any other desired configuration.
These resonator elements may be made with a single bridge as shown in
In some embodiments, once the pull-in voltage is released, the gap does not open again due to stiction. The pull-in voltage may be simply turned on whether the bridges are already collapsed to the stoppers or not.
In certain implementations, the pull-in voltage may be applied during the chip manufacturing process to set the operating gap at the time of manufacture. However, in other implementations, the pull-in voltage may be applied by the device, e.g. a consumer electronic device, to which the chip was installed during initial power on, initialization, and/or periodically. In some implementations, a device may sense the position of a bridge in relation to a capacitor electrode to determine whether and when to apply a pull-in voltage to reduce the distance to the operating gap distance between the bridge and its corresponding one or more capacitor electrodes. In another implementation, the mechanical resonator may include electrodes that enable the formation of one or more micro-welds depending on the amount of pull-in voltage applied. Thus, a sufficient pull-in voltage may be applied such that the bridge is fixed to one or more mechanical stoppers. Once fixed in position with the operating gap fixed, a pull-in voltage is no longer required.
An important need for the described filters is the ability to tune them easily. One reason is to have only one filter in the phone headset RF front end, instead of a large bank of filters, and the corresponding multiplexers or switches to select them. This is specially needed in the new multi-mode multi-band cell phones that are starting to appear in the market. But there is another reason for this need using the manufacturing process described above with respect to
Because of these tolerances and drifts, the filter may be calibrated using an external clock, and adjusted as often as needed. Changing the voltage changes the electromechanical coupling coefficient. Therefore both the motional inductance and the motional capacitances change, but their product is kept constant. However, in practice the stress on the bridges may change, and the effective young modulus may be different, depending on the applied biasing voltage. In addition the electrical capacitance may change noticeably, and this may affect the frequency response as well. This voltage dependence will be different for each resonator design. As an example,
In some embodiments, the described filters may be designed to match the required specifications for implementing UMTS filters. Very low insertion losses may be achieved by means of increasing the biasing voltage and the number of elements in the array. However, the voltage may have a practical limit, and increasing the number of elements may reduce the attenuation in the stop band. In some embodiments, the insertion loss requirements may be matched but not the attenuation requirements if an array is used. In some embodiments, the attenuation requirements may be matched but not the insertion loss requirements if a single element is used. Additionally, the gap may be set to the grid resolution limit, but due to the non vertical walls of the metal layers, the real effective gap may be smaller than expected. In some configurations, the RF filter operation in frequency ranges associated with protocols for GSM, UMTS, CDMA, AMPS, 802.11, and LTE communication protocols. In some configurations, an RF filter operates in anywhere from about 3 Hz to about 3 GHz. With respect to wireless communications networks, an RF Filter may operation in one or more frequency bands between about 400 MHz to about 4 GHz.
There are at least two ways to overcome these losses versus attenuation trade-off: lower pressures and modal filters. Lowering the pressures such that the quality factor of the individual resonator elements goes beyond the maximum measured value may result in non-uniform admittance and filter transference functions due to plenty of sharp edges and random CMOS processing for MEMS devices and their applications from device to device. However, for some frequencies, a sufficiently large number of resonator elements may be aligned, thus giving the performance desired at that frequency. In some embodiments, these filters may include intelligent circuitry to adjust the voltage so that the resonant frequency of those frequency matched filters is set to the desired center frequency for the filter.
The other option is to use variable impedances made with an array of mechanically coupled resonator elements inside a modal filter architecture. The modal filter may provide extremely high attenuation. In some embodiments, the modal filter may work well provided impedance changes in the order of 20 dB are implemented. Using this combination, a mechanical resonator array may be designed to minimize losses, and use the modal architecture to maximize the attenuation. This way, a very high performance, tunable and low cost UMTS filter may be implemented. Furthermore, being implemented in CMOS, the filter may be integrated with other functions, like the transceiver and the amplifiers.
Applicants consider all operable combinations of the embodiments disclosed herein to be patentable subject matter. Those skilled in the art will know or be able to ascertain using no more than routine experimentation, many equivalents to the embodiments and practices described herein. Accordingly, it will be understood that the systems and methods described herein are not to be limited to the embodiments disclosed herein, but is to be understood from the following claims, which are to be interpreted as broadly as allowed under the law. It should also be noted that, while the following claims are arranged in a particular way such that certain claims depend from other claims, either directly or indirectly, any of the following claims may depend from any other of the following claims, either directly or indirectly to realize any one of the various embodiments described herein.
This application claims priority to U.S. Provisional Patent Application No. 61/587,401 filed Jan. 17, 2012, and U.S. Provisional Patent Application No. 61/646,664 filed May 14, 2012, and is a continuation in part of U.S. patent application Ser. No. 13/364,149 filed Feb. 1, 2012, which claims priority to U.S. Provisional Patent Application No. 61/438,558 filed Feb. 1, 2011, U.S. Provisional Patent Application No. 61/440,223 filed Feb. 7, 2011, U.S. Provisional Patent Application No. 61/496,403 filed Jun. 13, 2011, U.S. Provisional Patent Application No. 61/501,950 filed Jun. 28, 2011, and U.S. Provisional Patent Application No. 61/558,689 filed Nov. 11, 2011, all of which are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61587401 | Jan 2012 | US | |
| 61438558 | Feb 2011 | US | |
| 61440223 | Feb 2011 | US | |
| 61496403 | Jun 2011 | US | |
| 61501950 | Jun 2011 | US | |
| 61558689 | Nov 2011 | US | |
| 61646664 | May 2012 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13364149 | Feb 2012 | US |
| Child | 13674440 | US |
