The field of invention relates generally to the field of semiconductor integrated circuit manufacturing and, more specifically but not exclusively, relates to the formation of a composite mask pattern using double patterning methods.
As semiconductor devices continue to be scaled to smaller sizes, lithography technology may not be able to pattern masking layers having a desired pitch. Accordingly, lithography may become a limiting factor in the scaling of semiconductor devices.
The present invention is illustrated by way of example and not as a limitation in the figures of the accompanying drawings, in which
An apparatus and methods for double patterning photoresist are described in various embodiments. In the following description, numerous specific details are set forth such as a description of a method to fabricate a composite mask that may be used to form features, such as a plurality of lines, trenches, bodies, or other definable structures in a layer or substrate that are too small or complicated to achieve in a single lithography step. One skilled in the relevant art will recognize that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
It would be an advance in the art of semiconductor manufacturing to reduce the number of process steps required to form a composite mask pattern in a target layer or substrate using a double patterning or a multiple patterning process. Double patterning is used to pattern one or more layers on a substrate, or the substrate itself, to form devices (e.g., transistor fins, gate stacks, etc.) therein to enable scaling of semiconductor devices for a lithography ratio of imaged half-pitch to optical resolution limit (or exposure k1 factor) at approximately less than 0.30. Existing double patterning methods includes using multiple resist layers and a plurality of etch processes to pattern one or more underlying layers. It would be a further advance in the art to provide a method to prevent degradation of a resist pattern upon contact with solvents or aqueous solutions, even after the resist pattern is further exposed to electromagnetic energy, such as ultraviolet (UV) light at an appropriate wavelength.
These advances in the art would avoid issues that can otherwise arise using contemporary manufacturing methods such as thermal processing and/or a deep UV cure process. Resist patterns formed using lithography can degrade significantly upon treatment with solvents and aqueous solutions. For example, a resist pattern formed on a surface such as a substrate can be washed away by a miscible solvent and can be consumed to a significant degree by immiscible solvents. Contact between a resist pattern and an aqueous solution such as water can lead to swelling of the resist pattern, as would be expected when using a thermal process or a deep UV cure process to cross link and stabilize the resist. Additional barrier layers, such as a thin organic layer, may be applied to the resist pattern to avoid swelling of the resist pattern upon contact with aqueous solutions. However, the use of one or more barrier layers causes undesirable enlargement of patterned lateral dimensions. To achieve desired lateral dimensions, it is necessary to use smaller patterns to account for the expected enlargement of the pattern with the addition of one or more barrier layers. Application of the barrier layer thus increases the lithographic challenge.
Another issue that can arise using contemporary manufacturing methods is that a resist pattern, formed on a surface using a first exposure source, that is further exposed to a second electromagnetic source such as UV light and then developed through contact with a weak basic solution can lift from the surface. Unintended resist lifting is a source a defects in the manufacture of semiconductor devices and is avoided to prevent a decrease in manufacturing yield.
One such advance in the art may comprise providing a first patterned resist layer on a target layer and/or substrate. A dopant is incorporated in the first patterned resist layer. A second resist layer is coated on the target layer and/or substrate. The second resist layer is patterned to form a composite mask on the target layer and/or substrate. A composite pattern is etched in the target layer and/or substrate using the composite mask. This embodiment of a method for double patterning photoresist is very flexible as it may be applied to a variety of resist chemistries, the equipment necessary to perform the method is commercially available, the dopant may be incorporated in the resist at a controlled depth and energy to stabilize portions of the resist most sensitive to attacks by solvent and aqueous solutions thus preserving critical physical resist dimensions, dopant incorporated in the resist may be tuned independent of the resist thickness, and selection of fluorine as the incorporated dopant adds a hydrophobic characteristic to the resist pattern thereby resisting or substantially preventing swelling from water penetration and/or retention.
Turning now to the figures, the illustration in
The resist material may be a deep ultraviolet (DUV) resist and may further be chemically amplified to increase sensitivity to a desired exposure energy. The target layer 205 may be prepared prior to the application of the resist material using hexamethyldisilazane (HMDS) to prime the target layer 205 and promote adhesion of the resist material to the target layer 205. The words “photoresist” and “resist” are used interchangeably in the description and title.
The patterned resist 200 is comprised of a plurality of lines including a first line 210 with a first line width 220 and a second line 215 with a second line width 240 wherein the first line and the second line are separated by a gap 230. A pitch of the patterned resist is equal to the first line width 220 plus the gap 230. The target layer 205 may comprise one or more films typically used in contemporary device fabrication known to one skilled in the art, and/or alternatively the target layer 205 may be a substrate comprising silicon, gallium arsenide (GaAs), or indium antimonide (InSb) in monocrystalline form. The target layer 205 may further comprise buried layers such as a silicon on insulator layer.
The patterned resist 200 illustrated in
In the embodiment illustrated in
Energy delivered by the ions breaks chemical bonds within the patterned resist 200 of
The doped resist layer thickness 425 may be approximately the same thickness as the patterned resist thickness 310 of
The embodiment illustrated in
In one embodiment, the incident angle is at least partly established using an ion implant or GCIB tool tilt angle. Further, the incident angle may be constrained as a function of the pitch of the patterned resist, for example due to shadowing effects. The doping process 410 may be characterized, at least in part, by the dopant species, energy, dose, and incident angle.
The energy range used in the dopant process 410 is related, at least in part, to the dopant species used in the dopant process 410. In one embodiment, an energy range used for the doping process 410 is between 5 and 25 thousand electron volts (KeV). The energy selected for the doping process 410 is designed to reduce or minimize damage to an underlying layer, such as the doped target layer 450 shown in
In another embodiment, the distribution profile of dopant in the multipass doped resist layer 520 is established with the highest concentration of dopant in the lower doped resist portion 530. The multipass doping process 510 of
In
In some embodiments, the doped resist layer 420 is resistant to immiscible solvents, such as water, that would otherwise deform or damage the patterned photoresist 200. For example, it has been demonstrated that a use of fluorine in the doping process 410 provides a doped resist layer 420 that is resistant to attacks by water. As an example, the patterned photoresist 200 when exposed to water may be susceptible to swelling, or an expansion of the patterned photoresist 200. Swelling of patterned photoresist 200 modifies a masked pattern so that placement and size of the masked pattern deviates from a desired pattern. Formation of the doped resist layer 420 provides a mechanism to preserve lateral dimensions and profiles of fine geometries, particularly those geometries with an exposure k1 factor of approximately equal to or less than 0.30. Further, formation of the doped resist layer 420 eliminates the need for an extra barrier layer that would otherwise be used to protect a masked pattern such as patterned resist 200. The extra barrier layer, while serving the purpose of shielding the masked pattern from miscible or immiscible solvents, also causes undesirable enlargement of patterned lateral dimensions. In addition, enlargement of patterned lateral dimensions due to application of the extra barrier layer can vary with feature geometry and size, leading to unexpected variation of patterned lateral dimensions.
A plurality of embodiments of methods for double patterning photoresist has been described. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.” The term “on” as used herein (including in the claims) does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations.
However, one skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and/or structures may be included and/or described features may be omitted in other embodiments.
Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.