Embodiments disclosed herein pertain to methods of etching trenches into silicon of a semiconductor substrate, to methods of forming trench isolation in silicon of a semiconductor substrate, and to methods of forming a plurality of diodes.
In the fabrication of integrated circuitry, numerous devices are packed into a small area of a semiconductor substrate to create an integrated circuit. Many of the individual devices are electrically isolated from one another. Accordingly, electrical isolation is an integral part of semiconductor device design for preventing unwanted electrical coupling between adjacent components and devices.
As the size of integrated circuits is reduced, the devices that make up the circuits are positioned closer together. Conventional methods of isolating circuit components include trench isolation. Such occurs by etching trenches into a semiconductor substrate and filling the trenches with insulative material. As the density of components on the semiconductor substrate has increased, the widths of the trenches have decreased. Further, the depths of the trenches have tended to increase. One type of semiconductor substrate material within which isolation trenches are formed is crystalline silicon, and which may include other materials such as germanium and/or conductivity modifying dopants. A need remains for developing improved etching chemistries which enable trenches to be etched into silicon, for example in the fabrication of trench isolation.
Embodiments of the invention include methods of etching trenches into silicon of the semiconductor substrate, and also methods of forming trench isolation in silicon of the semiconductor substrate. Further, embodiments of the invention also include methods of forming a plurality of diodes.
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A series of masking layers is received above silicon material 20. Such includes a pad oxide layer 22, a silicon nitride or polysilicon layer 24, a hardmasking layer 26, an antireflective coating layer 28, and a patterned photoresist layer 30. Any of such layers are optional, and may comprise multiple different materials and/or layers with respect to each. Such materials may or may not be ultimately sacrificial. In certain embodiments, hardmask layer 26 may be any of insulative, semiconductive, or conductive. Example insulative materials for hardmask layer 26 include silicon dioxide, whether doped or undoped, as well as silicon nitride. Example conductive materials for hardmask layer 26 include any one or combination of refractory metal nitrides (i.e., TiN, WN, etc.), refractory metal silicides (WSix, TiSx, etc.), or any metal in elemental form (Ti, W, etc.). Photoresist 30 is depicted as having been patterned to form trenches 32 to antireflective coating layer 28.
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Further of course, the precursor gases might comprise two oxygen-containing compounds, for example with one of the oxygen-containing compounds being void of nitrogen and another of the oxygen-containing compounds comprising nitrogen. For example in but one embodiment, the precursor gases might comprise SF6, N2, O2, and NOx. Alternately in such example, the precursor gases from which the plasma etching occurs might not include N2. Further in one embodiment, the precursor gases might comprise, consist essentially of, or consist of SF6, O2, and N2. Additional precursor gases might also of course be utilized, for example HBr. In one embodiment, the precursor gases from which the plasma etching is conducted might comprise more N2 than each of SF6 and O2 where such three gases are used. In one embodiment, the mask used during the etch comprises an outermost hardmask layer during at least a latter portion of the plasma etching into the silicon, and in one embodiment such outer mask layer is void of carbon as the stated plasma etching chemistry may etch an outermost hardmask layer that comprises carbon.
The invention was reduced to practice using a LAM Kiyo plasma etching chamber. Regardless and by way of examples only, example pressure during etching may be from about 1 mTorr to about 50 mTorr, and an example temperature range for the susceptor upon which the substrate rests is from about 0° C. to about 50° C. An example source power range is from about 100 W to about 1,000 W, and an example bias voltage is from about −20V to about −1,000V. Where, for example SF6, O2, N2, and HBr are precursor gases, example flow rates include from about 1 sccm to about 100 sccm for SF6; from about 10 sccm to about 500 sccm for O2; from 0 sccm to about 500 sccm for HBr; and from about 1 sccm to about 500 sccm for N2. A specific reduction-to-practice example in the LAM Kiyo plasma etching chamber included 5 mTorr, 7° C., −500V voltage bias, 400 W source power, 350 sccm SF6, 45 sccm O2, 60 sccm N2, and 20 sccm HBr. The particular plasma etcher used might be capable of operation such that either the bias voltage or the bias power can be the set point while the other is allowed to float. In one embodiment, bias voltage is set and bias power is allowed to float. In another embodiment, bias power is set and bias voltage is allowed to float.
It was determined that etching with SF6 and O2 without any nitrogen-containing compound may result in significant trench sidewall erosion, irregular trench sidewalls, and/or v-shaped trench bases. However, it was discovered that by adding a nitrogen-containing compound to the plasma etching chemistry, smoother and/or straighter trench sidewall resulted and with flatter trench bases, although the invention does not necessarily require achieving any of such results unless literally so claimed. Further, and without necessarily being limited by any theory of invention, presence of nitrogen in the plasma may be creating an NFx species that may or may not be facilitating straighter sidewalls and flatter bases.
Regardless, one embodiment of the invention includes plasma etching trenches into silicon of a semiconductor substrate using a mask having trenches formed there-through, wherein the plasma etching comprises an etching plasma comprising a sulfur-containing component, an oxygen-containing component, and NFx. In one embodiment, the sulfur-containing component is formed from a precursor gas comprising SF6. In one embodiment, the oxygen of the oxygen-containing component may be formed from a precursor gas comprising O2, and the nitrogen of the NFx may be formed from a precursor gas compound which is void of oxygen. Further in one embodiment, the oxygen of the oxygen-containing component and the nitrogen of the NFx may be formed from a precursor gas comprising NOx. Further, example precursor gases include any of those described above, including any combinations thereof.
Example etch depths for trenches 32 within silicon 12 are from about 7,500 Angstroms to about 20,000 Angstroms, with 9,000 Angstroms being but one specific example.
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Some or all of such materials 22, 24, 26, 42, and 44 may or may not be ultimately removed from the substrate.
Embodiments of the invention include methods of forming trench isolation within silicon of a semiconductor substrate, and may or may not comprise formation of spaced silicon-comprising mesas. For example and by way of example only, the above-described processing after
Regardless, embodiments of the invention also encompass methods of forming a plurality of diodes in conjunction with forming spaced silicon-comprising mesas. For example and by way of example only,
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In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
This patent resulted from a divisional application of U.S. patent application Ser. No. 13/570,583 which was filed Aug. 9, 2012, which is a divisional of U.S. patent application Ser. No. 12/726,243 which was filed Mar. 17, 2010, which resulted from a divisional application of U.S. patent application Ser. No. 11/949,643, filed Dec. 3, 2007, entitled “Methods of Etching Trenches Into Silicon Of A Semiconductor Substrate, Methods Of Forming Trench Isolation In Silicon Of A Semiconductor Substrate, And Methods Of Forming a Plurality Of Diodes”, naming Krupakar M. Subramanian as inventor, the disclosure of which is incorporated by reference.
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Number | Date | Country | |
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20140349487 A1 | Nov 2014 | US |
Number | Date | Country | |
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Parent | 13570583 | Aug 2012 | US |
Child | 14454521 | US | |
Parent | 12726243 | Mar 2010 | US |
Child | 13570583 | US | |
Parent | 11949643 | Dec 2007 | US |
Child | 12726243 | US |