Methods of forming capacitors and methods of forming capacitor dielectric layers

Information

  • Patent Grant
  • 7153736
  • Patent Number
    7,153,736
  • Date Filed
    Friday, February 13, 2004
    20 years ago
  • Date Issued
    Tuesday, December 26, 2006
    18 years ago
Abstract
A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed over the first capacitor electrode material. The semiconductor substrate with silicon nitride comprising layer is provided within a chamber. An oxygen comprising plasma is generated remote from the chamber. The remote plasma generated oxygen is fed to the semiconductor substrate within the chamber at a substrate temperature of no greater than 750° C. effective to form a silicon oxide comprising layer over the silicon nitride comprising layer. After the feeding, a second capacitor electrode material is formed over the silicon oxide comprising layer. Methods of forming capacitor dielectric layers are also disclosed.
Description
TECHNICAL FIELD

This invention relates to methods of forming capacitors and to methods of forming capacitor dielectric layers.


BACKGROUND OF THE INVENTION

Capacitors are commonly-used electrical components in semiconductor circuitry, for example in DRAM circuitry. As integrated circuitry density increases, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing capacitor area. A typical capacitor is comprised of two conductive electrodes separated by a non-conducting dielectric region. The dielectric region is preferably comprised of one or more materials preferably having a high dielectric constant and low leakage current characteristics. Example materials include silicon compounds, such as SiO2, and Si3N4. Si3N4 is typically preferred due to its higher dielectric constant than SiO2.


Numerous capacitor dielectric materials have been and are being developed in an effort to meet the increasing stringent requirements associated with the production of smaller and smaller capacitor devices used in higher density integrated circuitry. Most of these materials do, however, add increased process complexity or cost over utilization of conventional SiO2 and Si3N4 capacitor dielectric materials.


One dielectric region in use today includes a composite of silicon oxide and silicon nitride layers. Specifically, a first capacitor electrode is formed to have a silicon oxide comprising layer, typically silicon dioxide, of 6 to 10 Angstroms thereover. Such might be formed by deposition, or more typically by ambient or native oxide formation due to oxidation of the first electrode material (for example conductively doped polysilicon) when exposed to clean room ambient atmosphere. Thereafter, a silicon nitride layer is typically deposited by low pressure chemical vapor deposition. This can, however, undesirably produce very small pinholes in the silicon nitride layer, particularly with thin layers of less than 200 Angstroms, with the pinholes becoming particularly problematic in layers of less than or equal to about 75 Angstroms thick. These pinholes can undesirably reduce film density and result in undesired leakage current in operation.


One technique for filling such pinholes is to wet oxidize the substrate, for example at 750° C.-800° C., atmospheric pressure, and feeding 5 slpm H2, 10 slpm O2 for 15-60 minutes. Such forms silicon oxide material which fills the pinholes and forms a silicon oxide layer typically from about 5 Angstroms to about 25 Angstroms thick over the silicon nitride. It is generally desirable, however, to overall minimize the thermal exposure of the wafer/substrate upon which integrated circuitry is being fabricated. Exposure to 750° C.-800° C. for from 15 minutes-60 minutes is significant in this regard.


SUMMARY

The invention includes methods of forming capacitors and methods of forming capacitor dielectric layers. In one implementation, a method of forming a capacitor dielectric layer includes forming a silicon nitride comprising layer over a substrate. The substrate with silicon nitride comprising layer is provided within a chamber. An oxygen comprising plasma is generated remote from the chamber. The remote plasma generated oxygen is fed to the substrate within the chamber at a substrate temperature of no greater than 750° C. effective to form a silicon oxide comprising layer over the silicon nitride comprising layer.


In one implementation, a method of forming a capacitor includes forming first capacitor electrode material comprising silicon over a semiconductor substrate. A silicon nitride comprising layer is formed over the first capacitor electrode material. The silicon nitride comprising layer has pinholes formed therein. The semiconductor substrate with silicon nitride comprising layer is provided within a chamber. An oxygen comprising plasma is generated remote from the chamber. The remote plasma generated oxygen is fed to the semiconductor substrate within the chamber at a substrate temperature of no greater than 550° C. and for no longer than 30 seconds effective to form a silicon oxide comprising layer over the silicon nitride comprising layer and effective to fill said pinholes with silicon oxide. The chamber is essentially void of hydrogen during the feeding. After the feeding, a second capacitor electrode material is formed over the silicon oxide comprising layer.





BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below with reference to the following accompanying drawings.



FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment in process in accordance with an aspect of the invention.



FIG. 2 is a diagrammatic view of processing equipment.



FIG. 3 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1.



FIG. 4 is a view of the FIG. 3 wafer fragment at a processing step subsequent to that shown by FIG. 3.





DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).


Referring initially to FIG. 1, a wafer fragment in process in accordance with a method of forming a capacitor in accordance with an aspect of the invention is indicated generally with reference numeral 10. Such comprises a bulk monocrystalline silicon substrate 12. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also in the context of this document, the term “layer” includes both the plural and the singular unless otherwise indicated. An insulative layer 14, for example doped or undoped silicon dioxide, or silicon nitride, is formed over bulk substrate 12.


A first capacitor electrode material 16 is formed over insulative layer 14. At this point, or preferably later in the process, electrode material 16 is ultimately patterned/provided into some desired first capacitor electrode shape. Exemplary materials for electrode 16 include silicon (for example polysilicon) metals, conductive metal oxides, and any other conductive layer. An exemplary thickness in one preferred embodiment, and particularly where layer 16 comprises polysilicon, is 600 Angstroms. A first or inner silicon oxide comprising layer 18 is formed over, and “on” as shown, first capacitor electrode 16. An exemplary method for forming layer 18 is by oxidizing an outer portion of electrode material 16, for example by exposure to clean room ambient. This oxide layer is not preferred, but rather an effect of an exposed silicon or other oxidizable substrate. Typical thickness for layer 18 is less than or equal to 15 Angstroms. Layer 18 preferably consists essentially of silicon dioxide.


A silicon nitride comprising layer 20 is formed over first capacitor electrode material 16 and in the illustrated preferred embodiment is formed on first or inner silicon oxide comprising layer 18. An exemplary thickness is from 30 Angstroms to 80 Angstroms. In but one embodiment, silicon nitride comprising layer 20 is formed to have a plurality of pinholes 22 formed therein. Such are shown in exaggerated width/size in the figures for clarity. In the illustrated embodiment, at least some pinholes extend completely through layer 20 to silicon oxide comprising layer 18. Silicon nitride comprising layer 20 might be deposited by any existing or yet-to-be developed technique, with chemical vapor deposition or plasma enhanced chemical vapor deposition being but examples. One exemplary process whereby a silicon nitride layer 20 is deposited by chemical vapor deposition includes NH3 at 300 sccm, dichlorosilane at 100 sccm, 750 mTorr, 600° C., and 60 minutes of processing.


Referring to FIG. 2, semiconductor substrate 10 with silicon nitride comprising layer 20 is provided within a processing chamber 60. The processing chamber might be the same or different from any chamber utilized to produce any of the FIG. 1 construction. An example preferred processing chamber is a rapid thermal processor, with the invention being reduced to practice using an Applied Materials RTP-XE Chamber having a volume of 2700 cc. A suitable remote plasma generator 62 is diagrammatically shown and provided upstream of processing chamber 60. Any suitable remote plasma generation is contemplated, whether existing or yet-to-be-developed, with by way of example only microwave and RF plasma generation being examples. The invention was reduced to practice using an ASTEX FI20160-02 power source with a microwave unit number Ax3151-1, available from ASTEX of Wilmington, Mass. FIG. 2 depicts a suitable oxygen gas feed and an inert gas feed to the diagrammatic remote plasma generator 62.


An oxygen comprising plasma is generated remote from chamber 60, for example in generator 62. The remote plasma generated oxygen is then fed to the semiconductor substrate within chamber 60, with the substrate temperature being no greater than 750° C., effective to form a silicon oxide comprising layer 24 (FIG. 3) over, preferably “on” as shown, silicon nitride comprising layer 20, and effective to fill pinholes 22 with silicon oxide. More preferably, the substrate temperature during the feeding is maintained at no greater than 550° C., and even more preferably no greater than 500° C. Further preferably, the feeding is for no longer than 1 minute, with a feeding of less than or equal to 30 seconds being more preferred, and a feeding of less than or equal to 15 seconds being most preferred. In the most preferred embodiment, layers 18, 20 and 24 constitute a dielectric region 27 of the capacitor being formed, with such dielectric region consisting essentially of an ONO composite which consists essentially of such silicon oxide comprising-silicon nitride comprising silicon oxide comprising layers.


The oxygen comprising plasma is preferably derived, at least in part, from a gas selected from the group consisting of O2, O3, NyOx (with “x” and “y” being greater than zero) and mixtures thereof. Further as shown in the FIG. 2 embodiment, the oxygen comprising plasma is preferably generated, at least in part, from a suitable inert gas in addition to an oxygen feed gas. Examples include N2, Ar and He. One specific example includes an oxygen comprising plasma derived, at least in part, from feeding O2 and N2. Another exemplary embodiment in accordance with the above parameters includes forming an oxygen comprising plasma derived, at least in part, from N2O and at least one of Ar and He. Preferably in such latter example, the ultimate feeding of the remote generated plasma material to chamber 60 is void of feeding of N2 but for N2 which is inherently produced from the dissociation of N2O in the generation of the remote plasma. Further preferably, and contrary to the prior art described above, chamber 60 is essentially void of hydrogen during the feeding, thereby preventing any steam formation. In the context of this document, “essentially void” means below detectable levels.


A specific example with respect to the FIG. 2 processing with the ASTEX and Applied Materials equipments includes a feed of 2000 sccm with O2 and 1000 sccm of N2. Pressure within the remote plasma unit was maintained at approximately 2.9 Torr with microwave power provided at 2000 Watts. Temperature of the wafer was 650° C., with pressure maintained at 2.9 Torr. By way of example only, and with respect to the above-identified reduction-to-practice equipment, pressure is preferably maintained within the system at from 1 to 8 Torr, power supplied to the remote plasma generator at from 500 Watts to 3000 Watts, and temperature maintained within the system at from 500° C. to 750° C. Preferred flow ranges for each of O2 and N2 are from 0.5 slm to 5 slm. Temperatures as low as 350° C. might be used with other equipment.


The above-described preferred embodiments, in the fabrication of a capacitor dielectric region such as region 27, reduces the thermal exposure as compared to the prior art, in the most preferred embodiment, from in excess of 750° C. to less than 550° C., and further with the preferred embodiment reducing the exposure time even at the reduced temperature to well less than 1 minute. Properties of the capacitor dielectric region formed as described above appear comparable to ONO layers produced by prior art methods. For example, exposure of the dielectric region nitride to a remote oxygen plasma at 2000 Watts for 10 seconds resulted in a capacitor dielectric region having capacitance and leakage approximately equivalent to a prior art control wet oxidation. Further, an improvement in breakdown voltage for the 2000 Watt, 10 second treatment indicates that an increased capacitance via reduced thickness might be feasible, also.


Referring to FIG. 4, and after the feeding, a second capacitor electrode material 40 is formed over silicon oxide comprising layer 24. In the preferred and illustrated embodiment, second capacitor electrode material 40 is formed on (in contact with) oxide layer 24. An exemplary thickness for layer 40 is from 300 Angstroms to 600 Angstroms. Second electrode material 40 might comprise the same or different materials from first electrode material 16.


In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims
  • 1. A method of forming a capacitor comprising: forming first capacitor electrode material over a semiconductor substrate; forming a silicon nitride-comprising layer over the first capacitor electrode material; generating an oxygen-comprising plasma remote from over the substrate comprising the silicon nitride-comprising layer, the oxygen-comprising plasma being generated at least in part from one of a) a mixture of O2 and O3; b) a mixture of O2 and N2O; c) a mixture of O3 and N2O; or d) a mixture of O2, O3 and N2O; feeding the remote plasma-generated oxygen to the semiconductor substrate for no longer than 15 seconds at a substrate temperature of from 550° C. to 750° C. effective to form a silicon oxide-comprising layer over the silicon nitride-comprising layer; and after the feeding, forming second capacitor electrode material over the silicon oxide-comprising layer.
  • 2. The method of claim 1 wherein the remote plasma and environment over the substrate is essentially void of hydrogen during the feeding.
  • 3. The method of claim 1 wherein the oxygen-comprising plasma is at least in part generated from an inert gas.
  • 4. The method of claim 1 wherein the period of time is 10 seconds.
  • 5. The method of claim 1 wherein the substrate temperature is 650° C.
  • 6. The method of claim 1 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O2 and O3.
  • 7. The method of claim 1 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O2 and N2O.
  • 8. The method of claim 1 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O3 and N2O.
  • 9. The method of claim 1 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O2, O3 and N2O.
  • 10. A method of forming a capacitor comprising: forming first capacitor electrode material comprising silicon over a semiconductor substrate; forming a silicon nitride-comprising layer over the first capacitor electrode material, the silicon-nitride comprising layer comprising pinholes formed therein; generating an oxygen-comprising plasma remote from over the substrate comprising the silicon nitride-comprising layer, the oxygen-comprising plasma being generated at least in part from one of a) a mixture of O2 and O3; b) a mixture of O2 and N2O; c) a mixture of O3 and N2O; or d) a mixture of O2, O3 and N2O; feeding the remote plasma-generated oxygen to the semiconductor substrate for no longer than 15 seconds at a substrate temperature of from 550° C. to 750° C. effective to form a silicon oxide-comprising layer over the silicon nitride-comprising layer and effective to fill said pinholes with silicon oxide, the remote plasma and environment over the substrate being essentially void of hydrogen during the feeding; and after the feeding, forming second capacitor electrode material over the silicon oxide-comprising layer.
  • 11. The method of claim 10 further comprising forming a silicon oxide-comprising layer over the first capacitor electrode material prior to forming the silicon nitride-comprising layer, the capacitor being formed to have a dielectric region consisting essentially of an ONO composite consisting essentially of said silicon oxide-comprising layer and said silicon nitride-comprising layer.
  • 12. The method of claim 10 wherein the oxygen-comprising plasma is at least in part generated from an inert gas.
  • 13. The method of claim 10 wherein the period of time is 10 seconds.
  • 14. The method of claim 10 wherein the substrate temperature is 650° C.
  • 15. The method of claim 10 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O2 and O3.
  • 16. The method of claim 10 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O2 and N2O.
  • 17. The method of claim 10 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O3 and N2O.
  • 18. The method of claim 10 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O2, O3 and N2O.
  • 19. A method of forming a capacitor dielectric layer, comprising: forming a silicon nitride-comprising layer over a substrate; generating an oxygen-comprising plasma remote from over the substrate comprising the silicon nitride-comprising layer, the oxygen comprising plasma being generated at least in part from O3; and feeding the remote plasma-generated oxygen to the substrate at a substrate temperature of no greater than 750° C. effective to form a silicon oxide-comprising layer on the silicon nitride-comprising layer.
  • 20. The method of claim 19 wherein the substrate temperature during the feeding is no greater than 550° C.
  • 21. The method of claim 19 wherein the substrate temperature during the feeding is no greater than 500° C.
  • 22. The method of claim 19 wherein the feeding is for no longer than 1 minute.
  • 23. The method of claim 19 wherein the feeding is for no longer than 30 seconds.
  • 24. The method of claim 19 wherein the feeding is for no longer than 15 seconds.
  • 25. The method of claim 19 wherein the remote plasma and environment over the substrate is essentially void of hydrogen during the feeding.
  • 26. The method of claim 19 wherein the oxygen-comprising plasma is at least in part generated from an inert gas.
  • 27. The method of claim 19 further comprising forming a silicon oxide-comprising layer over the first capacitor electrode material prior to forming the silicon nitride-comprising layer, the capacitor being formed to have a dielectric region consisting essentially of an ONO composite consisting essentially of said silicon oxide-comprising layer and said silicon nitride-comprising layer.
  • 28. A method of forming a capacitor dielectric layer, comprising: forming a silicon nitride-comprising layer over a substrate; generating an oxygen-comprising plasma remote from over the substrate comprising the silicon nitride-comprising layer, the oxygen-comprising plasma being generated at least in part from one of a) a mixture of O2 and O3; b) a mixture of O2 and N2O; c) a mixture of O3 and N2O; or d) a mixture of O2, O3 and N2O; and feeding the remote plasma-generated oxygen to the substrate for no longer than 15 seconds at a substrate temperature of from 550° C. to 750° C. effective to form a silicon oxide-comprising layer over the silicon nitride-comprising layer.
  • 29. The method of claim 28 wherein the period of time is 10 seconds.
  • 30. The method of claim 28 wherein the substrate temperature is 650° C.
  • 31. The method of claim 28 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O2 and O3.
  • 32. The method of claim 28 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O2 and N2O.
  • 33. The method of claim 28 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O3 and N2O.
  • 34. The method of claim 28 wherein the oxygen-comprising plasma is generated at least in part from a mixture of O2, O3 and N2O.
RELATED PATENT DATA

This patent resulted from a continuation application of U.S. patent application Ser. No. 10/006,032, filed Dec. 3, 2001 U.S. Pat. No. 6,723,599, entitled “Methods of Forming Capacitors and Methods of Forming Capacitor Dielectric Layers”, naming Denise M. Eppich and Kevin L. Beaman as inventors, the disclosure of which is incorporated by reference.

US Referenced Citations (153)
Number Name Date Kind
3627598 McDonald et al. Dec 1971 A
4254161 Kemlage Mar 1981 A
4262631 Kubacki Apr 1981 A
4435447 Ito et al. Mar 1984 A
4605447 Brotherton et al. Aug 1986 A
4882649 Chen et al. Nov 1989 A
4891684 Nishioka et al. Jan 1990 A
4980307 Ito et al. Dec 1990 A
4996081 Ellul et al. Feb 1991 A
5026574 Economu et al. Jun 1991 A
5032545 Doan et al. Jul 1991 A
5051794 Mori Sep 1991 A
5142438 Reinberg et al. Aug 1992 A
5164331 Lin et al. Nov 1992 A
5227651 Kim et al. Jul 1993 A
5237188 Iwai et al. Aug 1993 A
5254489 Nakata Oct 1993 A
5258333 Shappir et al. Nov 1993 A
5318924 Lin et al. Jun 1994 A
5324679 Kim et al. Jun 1994 A
5330920 Soleimani et al. Jul 1994 A
5330936 Ishitani Jul 1994 A
5334554 Lin et al. Aug 1994 A
5350707 Ko et al. Sep 1994 A
5376593 Sandhu et al. Dec 1994 A
5378645 Inoue et al. Jan 1995 A
5382533 Ahmad et al. Jan 1995 A
5393702 Yang et al. Feb 1995 A
5397748 Watanabe et al. Mar 1995 A
5398641 Shih Mar 1995 A
5436481 Egawa et al. Jul 1995 A
5445999 Thakur et al. Aug 1995 A
5449631 Giewont et al. Sep 1995 A
5459105 Matsuura Oct 1995 A
5464792 Tseng et al. Nov 1995 A
5498890 Kim et al. Mar 1996 A
5500380 Kim Mar 1996 A
5504029 Murata et al. Apr 1996 A
5508542 Geiss et al. Apr 1996 A
5518946 Kuroda May 1996 A
5518958 Giewont et al. May 1996 A
5523596 Ohi et al. Jun 1996 A
5596218 Soleimani et al. Jan 1997 A
5612558 Harshfield Mar 1997 A
5619057 Komatsu Apr 1997 A
5620908 Inoh et al. Apr 1997 A
5633036 Seebauer et al. May 1997 A
5663077 Adachi et al. Sep 1997 A
5674788 Wristers et al. Oct 1997 A
5685949 Yashima Nov 1997 A
5716864 Abe Feb 1998 A
5719083 Komatsu Feb 1998 A
5731235 Srinivasan et al. Mar 1998 A
5760475 Cronin et al. Jun 1998 A
5763922 Chau Jun 1998 A
5821142 Sung et al. Oct 1998 A
5834372 Lee Nov 1998 A
5837592 Chang et al. Nov 1998 A
5837598 Aronowitz et al. Nov 1998 A
5840610 Gilmer et al. Nov 1998 A
5844771 Graettinger et al. Dec 1998 A
5851603 Tsai et al. Dec 1998 A
5861651 Brasen et al. Jan 1999 A
5882978 Srinivasan et al. Mar 1999 A
5885877 Gardner et al. Mar 1999 A
5897354 Kachelmeier Apr 1999 A
5920779 Sun et al. Jul 1999 A
5939750 Early Aug 1999 A
5960289 Tsui et al. Sep 1999 A
5960302 Ma et al. Sep 1999 A
5969397 Grider, III et al. Oct 1999 A
5970345 Hattangady et al. Oct 1999 A
5972783 Arai et al. Oct 1999 A
5972800 Hasegawa Oct 1999 A
5981366 Koyama et al. Nov 1999 A
5994749 Oda Nov 1999 A
5998253 Loh et al. Dec 1999 A
6001741 Alers Dec 1999 A
6001748 Tanaka et al. Dec 1999 A
6008104 Schrems Dec 1999 A
6033998 Aronowitz et al. Mar 2000 A
6040249 Holloway Mar 2000 A
6051865 Gardner et al. Apr 2000 A
6054396 Doan Apr 2000 A
6057220 Ajmera et al. May 2000 A
6063713 Doan May 2000 A
6077754 Srinivasan et al. Jun 2000 A
6080629 Gardner et al. Jun 2000 A
6080682 Ibok Jun 2000 A
6087229 Aronowitz et al. Jul 2000 A
6087236 Chau et al. Jul 2000 A
6091109 Hasegawa Jul 2000 A
6091110 Hebert et al. Jul 2000 A
6093661 Trivedi et al. Jul 2000 A
6096597 Tsu et al. Aug 2000 A
6100163 Jang et al. Aug 2000 A
6110780 Yu et al. Aug 2000 A
6110842 Okuno et al. Aug 2000 A
6111744 Doan Aug 2000 A
6114203 Ghidini et al. Sep 2000 A
6136636 Wu Oct 2000 A
6140187 DeBusk et al. Oct 2000 A
6146948 Wu et al. Nov 2000 A
6150226 Reinberg Nov 2000 A
6168980 Yamazaki et al. Jan 2001 B1
6171900 Sun Jan 2001 B1
6174821 Doan Jan 2001 B1
6184110 Ono et al. Feb 2001 B1
6197701 Shue et al. Mar 2001 B1
6201303 Ngo et al. Mar 2001 B1
6207532 Lin et al. Mar 2001 B1
6207586 Ma et al. Mar 2001 B1
6207985 Walker Mar 2001 B1
6225167 Yu et al. May 2001 B1
6228701 Dehm et al. May 2001 B1
6232244 Ibok May 2001 B1
6245616 Buchanan et al. Jun 2001 B1
6255703 Hause et al. Jul 2001 B1
6265327 Kobayashi et al. Jul 2001 B1
6268296 Misium et al. Jul 2001 B1
6274442 Gardner et al. Aug 2001 B1
6297162 Jang et al. Oct 2001 B1
6323114 Hattangady et al. Nov 2001 B1
6323138 Doan Nov 2001 B1
6331492 Misium et al. Dec 2001 B1
6348420 Raaijmakers et al. Feb 2002 B1
6350707 Liu et al. Feb 2002 B1
6362085 Yu et al. Mar 2002 B1
6399445 Hattangady et al. Jun 2002 B1
6399448 Mukhopadhyay et al. Jun 2002 B1
6399520 Kawakami et al. Jun 2002 B1
6410991 Kawai et al. Jun 2002 B1
6413881 Aronowitz et al. Jul 2002 B1
6436771 Jang et al. Aug 2002 B1
6450116 Noble et al. Sep 2002 B1
6482690 Shibata Nov 2002 B1
6492690 Ueno et al. Dec 2002 B1
6649543 Moore Nov 2003 B1
6653184 Moore Nov 2003 B1
6660657 Sandhu et al. Dec 2003 B1
6660658 Sandhu et al. Dec 2003 B1
6682979 Moore Jan 2004 B1
6686298 Beaman et al. Feb 2004 B1
6690046 Beaman et al. Feb 2004 B1
6875707 Moore et al. Apr 2005 B1
6878585 Moore et al. Apr 2005 B1
6891215 Moore et al. May 2005 B1
6893981 Park et al. May 2005 B1
20010036752 Deboer et al. Nov 2001 A1
20020009861 Narwankar et al. Jan 2002 A1
20020052124 Raaijmakers et al. May 2002 A1
20030034518 Yoshikawa Feb 2003 A1
20050167727 Moore et al. Aug 2005 A1
Foreign Referenced Citations (4)
Number Date Country
0 886 308 Dec 1998 EP
237243 Apr 2001 JP
2001237243 Aug 2001 JP
WO 9639713 Dec 1996 WO
Related Publications (1)
Number Date Country
20040161889 A1 Aug 2004 US
Continuations (1)
Number Date Country
Parent 10006032 Dec 2001 US
Child 10779244 US