Patent Application
20070082454
The present invention refers to a microelectronic device and a method of manufacturing a microelectronic device, and in particular, a microelectronic device having a recessed channel array transistor (RCAT) and/or a trench capacitor.
The manufacturing costs of microelectronic devices are essentially proportional to the chip area. And there is a continuous tendency to increase the number of transistors, capacitors and other elements in microelectronic devices. For both reasons, microelectronic devices and their single electronic elements are continuously miniaturized. For this purpose, the linear dimensions of each electronic element are reduced and new designs for transistors, capacitors and other elements are developed.
For example, the gate electrode, the gate oxide and the channel region of a field effect transistor (FET) have been flat and essentially parallel to the surface of a substrate for a long period of time. The FIGS. 6 to 8 display a more recent design of a transistor. In a substrate 10 with a surface 12, a high aspect ratio recess, or trench 14 is formed essentially vertical to the surface 12 of the substrate 10. A thin dielectric layer 16 made of silicon oxide or any other electrically insulating material is deposited in the recess 14. The recess is filled with doped polysilicon or any other electrically conductive material forming a gate electrode 18. Highly doped source and drain electrode regions 20, 22 are formed at the surface 12 of the substrate 10 at opposite sides of the trench 14. A thin U-shaped channel region 24 is formed in the substrate 10 directly adjacent to the dielectric layer 16.
The electrical conductivity of the channel region 24 can be controlled by the electrical potential of the gate electrode 18 thereby electrically conductively connecting the source and drain electrode regions 20, 22 or insulating the same from each other. The local conductivity of the channel region 24 at any location depends on the local electrical field and the resulting local electrical potential at that location. However, the electrical field is strongly inhomogeneous at the lower end or bottom of the trench 14.
FIGS. 6 to 8 display three different examples of the shape of the trench 14. The circles 30 indicate regions with reduced electrical field. These regions of reduced electrical field exist at all edges or corners of the trench 14. The value of the gate electrode 18 potential necessary for switching on the channel region 24 in these low electrical field regions 30 is considerably higher than for other parts of the channel regions 24, and the electrical potential of the gate electrode 18 necessary to switch on the entire channel region 24 strongly depends on the particular geometry of the lower end of the trench 14. Further, local variations of the dopant concentration strongly influence these electrical properties.
However, it is very difficult to control the particular shape of the trench 14. While the geometry displayed in
While FIGS. 6 to 8 display vertical gate FETs, or RCATs, similar problems of a hardly reproducible trench geometry strongly influencing electric and electronic properties exist for trench capacitors and other trench electronic elements of microelectronic devices as well. It is a further problem that not only the geometry of the trench 14 but also the thickness and the homogeneity of the thickness of the dielectric layer 16 are difficult to control.
The present invention provides an improved microelectronic device and an improved method of manufacturing a microelectronic device, the microelectronic device having an electronic element formed in a recess. The present invention also provides a microelectronic device and a method of manufacturing a microelectronic device, the microelectronic device having a transistor or capacitor formed in a recess. The present invention also provides a microelectronic device and a method of manufacturing a microelectronic device wherein the influence of the specific geometry of a recess on the electrical and electronic properties of an electronic element of the microelectronic device is eliminated or reduced. The present invention also provides a microelectronic device and a method of manufacturing a microelectronic device wherein the microelectronic device is a memory device.
In one embodiment of the present invention there is a microelectronic device comprising a substrate and a transistor, the transistor comprising: a channel region in the substrate; a recess in the channel region; a first dielectric layer being deposited at the bottom of the recess, the first dielectric layer comprising a first dielectric material; a second dielectric layer being deposited at a sidewall of the recess, the second dielectric layer comprising a second dielectric material; and a gate electrode positioned in the recess and being electrically insulated from the channel region by the first and second dielectric layers, wherein the dielectric constant of the first dielectric material is higher than the dielectric constant of the second dielectric material.
In another embodiment of the present invention there is a microelectronic device with: a substrate comprising an electrically conductive material in an electrically conductive region; a recess formed in the electrically conductive region; a first dielectric layer being deposited at the bottom of the recess, the first dielectric layer comprising a first dielectric material; a second dielectric layer being deposited at a sidewall of the recess, the second dielectric layer comprising a second dielectric material; and a filling member positioned in the recess and being electrically insulated from the electrically conductive material of the electrically conductive region by the first and second dielectric layers.
In still another embodiment of the present invention there is a method of manufacturing a microelectronic device, the method comprising: providing a substrate with a surface; producing an electrically conductive region under the surface of the substrate; producing a recess in the electrically conductive region; generating a first dielectric layer at the bottom of the recess; generating a second dielectric layer at a sidewall of the recess; and filling the recess with a filling material, thereby forming a filling member, wherein the filling member is electrically insulated from the electrically conductive region by the first and second dielectric layers.
In yet another embodiment of the invention, there is a microelectronic device and a method of manufacturing a microelectronic device wherein a first dielectric layer comprising a first dielectric material is deposited at the bottom of a recess and a second dielectric layer comprising a second dielectric material is deposited at a sidewall of the recess. The first and second dielectric materials are different from each other and preferably provide different dielectric constants. The first dielectric material of the first dielectric layer is selected such that the influence of the particular geometry of the bottom of the recess on the electrical or electronic properties of the element is reduced or eliminated. Thus the present invention provides the advantage that there is no need to control the geometry of the bottom of the recess. Thereby the manufacturing costs are reduced.
In another embodiment of the invention, the microelectronic device with a transistor formed in the recess wherein the dielectric constant of the first dielectric material is higher than the dielectric constant of the second dielectric material. Adjacent to the first dielectric layer the electrical conductivity of the channel region is increased at an electrode voltage the absolute value of which is lower than the absolute value of the electrode voltage necessary to increase the electrical conductivity of the channel region adjacent to the second dielectric layer. Thereby, the conductivity of the entire channel and the switching behaviour and the threshold voltage of the transistor are merely influenced by the essentially vertical sidewalls of the recess but not by the geometry of the bottom of the recess.
In one aspect of the invention, the high dielectric constant of the first dielectric material of the first dielectric layer at the bottom of the recess causes a kind of short circuit of the channel at the bottom of the recess. At a gate electrode potential at the transition between the off state and the on state of the transistor (threshold voltage) that part of the channel adjacent to the first dielectric layer is already locally in the on state. The transition between the off state and the on state of the transistor is a transition of merely the sidewall parts of the channel. This is particularly advantageous since the geometry of the essentially vertical sidewalls of the recess and thereby the switching behaviour of the sidewall parts of the channel are easily controlled with a high reproducibility. In particular, the influence of local variations of the dopant concentration is reduced.
The present invention, in another embodiment, forms a dielectric layer comprising the second dielectric material at the sidewalls and at the bottom of the recess and to implant nitrogen or other ions into the dielectric layer at the bottom of the recess thereby locally transforming the second dielectric material to the first dielectric material. This method provides the advantage that the nitrogen or other ions are easily implanted selectively at the bottom of the recess by means of a vertical stream of energized ions. The stream vertical to the surface of the substrate and parallel to the sidewalls of the recess causes a concentration of implanted ions which is much higher at the bottom of the recess than in its sidewalls.
The implantation of ions is a standard technology. The concentration and the depth of implantation can be easily controlled. However, it is not necessary to control the concentration of nitrogen or other ions in the bottom part of the dielectric layer with high accuracy. It is a further advantage of the present invention that due to the small depth of implantation it is not necessary to protect the surface of the substrate outside the recess against the ions. For example, the electrical properties of source and drain regions under the surface of the substrate are scarcely modified by the implantation of nitrogen in a shallow surface layer.
The present invention also provides the microelectronic device with a capacitor formed in the recess. The first dielectric material of the first dielectric layer at the bottom of the recess preferably provides a dielectric constant which is lower than the dielectric constant of the second dielectric material of the second dielectric layer at the sidewalls of the recess. Thereby, the contribution of the bottom region to the capacitance of the capacitor and the influence of the geometry of the bottom of the recess on the capacity of the capacitor are reduced. In this way the present invention provides the advantage that the capacitance can be set precisely more easily.
The present invention is particularly advantageous for highly miniaturized elements like cell transistors or storage capacitors of storage cells of memory devices or other microelectronic devices.
The invention is described in more detail with reference to the exemplary embodiments and figures, in which:
FIGS. 6 to 8 show sectional views of conventional microelectronic devices.
FIGS. 1 to 4 display schematic sectional views of parts of microelectronic devices wherein the sectional area is perpendicular to the surface 12 of a substrate 10. Each of the microelectronic devices displayed in FIGS. 1 to 4 are transistor devices or capacitor devices or any other devices comprising memory cells. However, the present invention is advantageous for all highly miniaturized microelectronic devices with electronic elements formed in or at a recess.
Preferably, the substrate comprises Si or Ge or GaAs or any other crystalline or polycrystalline or amorphous semiconductor material. The source and drain electrode regions 20, 22 are highly doped with a dopant concentration of 1019 cm−3 . . . 1021 cm−3. The substrate 10 or at least the channel region 24 in the substrate 10 is preferably lightly doped with a dopant concentration of 1016 cm−3 . . . 1018 cm−3. Preferably, the first dielectric material of the first dielectric layer 40 comprises silicon oxynitride or silicon nitride or hafnium oxide or hafnium oxynitride or hafnium nitride wherein the stoichiometry of silicon or hafnium oxide can be variable. Preferably, the second dielectric material of the second dielectric layer 16 is silicon oxide. Preferably, the width of the trench 14 is between 50 nm and 100 nm or even smaller and the depth of the trench 14 is between 100 nm and 200 nm or even larger. Preferably, the thickness of the first and second dielectric layers 40, 16 is between 1.5 nm and 10 nm. Preferably the gate electrode 18 comprises highly doped polysilicon or tungsten or any other metal or any other electrically conductive material.
For an NFET, the source and drain electrode regions 20, 22 are n-doped, the substrate 10 or at least the channel region 24 is p-doped and the gate electrode 18 is n-doped if it comprises a semiconductor. For a PFET, the source and drain electrode regions 20, 22 are p-doped, the substrate 10 or at least the channel region 24 is n-doped and the gate electrode 18 is p-doped if it comprises a semiconductor.
The dielectric constant of the first dielectric material of the first dielectric layer 40 is higher than the dielectric constant of the second dielectric material of the second dielectric layer 16. For example, the relative dielectric constant εr of silicon oxide SiO2 is εr=3.9, and the relative dielectric constant of pure silicon nitride Si3N4 is εr=7.5. For the first dielectric material comprising silicon, oxygen and nitrogen, the relative dielectric constant of the first dielectric layer is 3.9<εr<7.5 depending on the nitrogen content.
Along the interface between the substrate 10 and the first and second dielectric layers 40, 16, an electrically conductive inversion layer, or channel, electrically conductively connecting the source and drain electrodes 20, 22 can be formed in the channel region 24. The formation of the conductive channel depends on the electrostatic potential of the gate electrode 18 and on the voltages between the gate electrode 18 and the source and drain electrodes 20, 22 and the substrate 10. Due to the dielectric constant of the first dielectric layer 40 being higher than the dielectric constant of the second dielectric layer 16, adjacent to the first dielectric layer 40 the channel is formed earlier than adjacent to the second dielectric layer 16.
In other words, at a potential of the gate electrode 18 at which no channel is formed adjacent to the second dielectric layer 16 but close to the threshold at which a channel is formed adjacent to the second dielectric layer 16, a channel is formed adjacent to the first dielectric layer 40. Thereby, the switching behaviour of the transistor formed by the source and drain electrodes 20, 22, the gate electrode 18 and the channel region 24 is largely independent of the geometry of the bottom of the trench 14.
The threshold voltage, or threshold potential of the transistor is the threshold voltage, or threshold potential, respectively, at which the source and drain electrodes 20, 22 are electrically conductively connected via a channel in the channel region 24. Due to the dielectric constant of the first dielectric material being higher than the dielectric constant of the second dielectric material, the threshold voltage of the transistor is largely independent of the particular geometry of the bottom of the recess 14. In other words, due to the dielectric constant of the first dielectric material being higher than the dielectric constant of the second dielectric material, at the threshold voltage of the transistor the channel region adjacent to the first dielectric layer 40 is short circuited.
It has been found that with usual nitrogen implantation parameters the influence of edges or other structures at the bottom of the trench 14 on the threshold voltage of the transistor can be compensated as long as the radius of curvature is not less than twice the thickness of the dielectric layers 40, 16.
A first dielectric layer 40 is deposited at the bottom of the trench 14, and a second dielectric layer 16 is deposited at the sidewalls of the trench 14. At least in a region adjacent to the trench 14, the substrate 10 is electrically conductive and forms a first capacitor electrode 52. The trench 14 is filled with doped polysilicon, tungsten or any other metal or electrically conductive material forming a second capacitor electrode 54. The second capacitor electrode 54 is connected to a conductor 56. In this example, the conductor 56 is oriented parallel to the surface 12 and arranged in the electrically insulating layer 50.
The first and second dielectric layers 40, 16 provide different dielectric materials. Preferably, the dielectric constant of the first dielectric material of the first dielectric layer 40 is lower than the dielectric constant of the second dielectric material of the second dielectric layer 16. In this way the influence of the geometry of the bottom of the trench 14 on the capacitance of the capacitor is reduced. The value of the capacitance of the capacitor is better defined and more reliable and the fluctuations of the capacitance from capacitor to capacitor is reduced.
Whereas the geometry of the bottom of the trench 14 displayed in
Two extreme geometries are displayed in
It is advantageous to provide a microelectronic device with both a transistor as described above with reference to
In a first step 82, a substrate 10 with a surface 12 is provided. In a second step 84, a conductive region 24, 52 is produced in the substrate 10. This is preferably done by doping the substrate material. In a third step 86, a recess 14 is produced in the conductive region 24, 52. Preferably, this recess is a trench with a high aspect ratio and is produced by an anisotropic etching process. The recess 14 provides sidewalls which are essentially vertical to the surface 12 of the substrate 10.
In a fourth step 88, a first dielectric layer 40 comprising a first dielectric material is generated at the bottom of the recess 14. In a fifth step 90, a second dielectric layer 16 comprising a second dielectric material is generated. The fourth and fifth steps 88, 90 can be performed in this sequence or in the reverse sequence or even simultaneously. According to a preferred embodiment, a dielectric layer is generated in the recess 14 comprising for example silicon oxide. Subsequently ions, for example nitrogen ions, are implanted in the dielectric layer at the bottom of the recess 14. The dielectric material of the dielectric layer portion 16 at the sidewalls of the recess 14 without implanted atoms is the second dielectric material of the second dielectric layer. By the implantation of the atoms, the original dielectric material is transformed to the first dielectric material of the first dielectric layer 40.
Alternatively, the first and second dielectric layers 40, 16 are generated separately. According to this alternative, low-k dielectrics like stoichiometric or non-stoichiometric silicon oxynitride, pure silicon nitride, hafnium oxide, hafnium oxynitride or pure hafnium nitride can be used as first dielectric material with a high dielectric constant.
When the electronic element formed with this method is a capacitor, the dielectric constant of the second dielectric layer 16 is preferably higher than the dielectric constant of the first dielectric layer 40, the first dielectric material is preferably silicon oxide and the second dielectric material is preferably selected from the group comprising silicon oxynitride, silicon nitride, hafnium oxide, hafnium oxynitride and hafnium nitride.
In a sixth step 92, the recess is filled with an electrically conductive material like doped polysilicon, tungsten, any other metal or any other electrically conductive material.
