Patent Grant
11990266
This invention relates to miniature circuit components for application in connection with integrated circuits and certain types of miniature discrete circuits and methods for manufacturing such devices. The invention is related to improvements upon and replacement of conventional miniature spiral inductors for example. Other embodiments include transmission lines, capacitors, and low impedance power distribution networks in integrated circuits. More particularly, design techniques and structures are disclosed with mathematical proofs that permit realization of small, very high current, and high inductance components with good quality factor Q in one embodiment and also in applications where high current distribution problems are found in miniature structures such as integrated circuit chips and power supplies.
A class of devices called spiral inductors is known for use with semiconductor devices, and they represent an example of the types of devices that can be made according to the invention. Spiral inductors are defined as planar structures having a characteristic inductance, and they are known to some degree for realizing inductors in integrated circuit and packaging technologies. They are extensively used in RFIC (Radio Frequency Integrated Circuits) in LNA (Low Noise Amplifier), VCO (Voltage Controlled Oscillators), PLL (Phase Locked Loops) designs. Recently, spiral inductors have been considered for DC/DC converter architectures, mainly for buck converter designs for supplying on-chip, high current, low voltage requirements for processor designs. [3-9][Reference numbers refer to listed reference items below.]
Accurate analysis in preparation for suitable designs requires a good understanding of complex electromagnetics and suggests a need for sophisticated and accurate analysis software. Designing a spiral inductor with a desired inductance value and AC performance in a smallest possible area is a more difficult optimization problem than analyzing a given structure. Extending the concept of a small area spiral inductor for use in power space as in DC/DC converter architectures puts even more difficult constraints on the design for a given process technology, due to the high current specifications (1 A-130 A) and much larger needed inductance values (10 nH-80 nH) within a reasonably small area, such as regions not exceeding several hundred microns on a side for applications operating below 200 MHz with good quality (Q>10 (Quality Factor). This is a nearly impossible problem to solve with current process technologies related to integrated circuit architectures [3-24]. Therefore, the only presently known option is use of off-chip inductors. Such inductors suffer from undesirable issues in design [3-24] and are not inherently small relative to the dimensions of elements in a semiconductor device, resulting in a large area penalty on the overall system dimension.
The electromagnetics of any inductor is complex. Even a distributed circuit model is highly complex compared to capacitor and resistors. The distributed circuit model requires many mutual coupled inductors, resistors and capacitors that need to be calculated from the physical geometry. However a distributed circuit model is still is a simpler way of understanding the circuit behavior of a spiral inductor compared to complex electromagnetics associated with it. To understand the invention explained it is useful to start from inductor basics. In this work both complex electromagnetic simulations and circuit models derived from the simplified solution of the three-dimensional simulation results are used. Thus, this disclosure is a fundamental tutorial for realizing miniature inductance devices.
The inventor would like to acknowledge the assistance of Prof. Dr. Yusuf Leblebici and Dr. Seniz E. Kucuk Eroglu of the Microelectronic Systems Laboratory Swiss Federal Institute of Technology, Lausanne, Switzerland for providing technical assistance in manufacturing structures as herein disclosed and Michael Brunolli of San Diego, California, for introducing this very challenging problem, circuit level discussions and his constant encouragements throughout the work.
The following references, many of which are herein cited, provide supplemental and background information for this invention and are incorporated herein by reference for all purposes. No representation is made as to the extent of relevance to the present invention.
According to the invention, miniature circuit components of various disclosed manufacturing techniques are provided that are suitable for forming or embedding in semiconductor structures or coupling to miniature circuitry and suitable as inductors, capacitors, transmission lines and power distribution networks based on a principle of tight coupling among conductive segments. In a specific embodiment, a miniature inductor is provided for integrated circuit applications that comprises a rectangular-cross-section metal conductive element formed in various configurations as a multiple-turn winding formed of adjacent segments and disposed such that the thickness dimension is much greater than the width dimension and windings are closely spaced in the width dimension on a scale comparable to the width dimension to attain tight coupling across multiple turns. Further embodiments include a spiral winding disposed in a silicon substrate formed of a deep, narrow, conductor-covered spiral ridge separated by a narrow spiral channel trough or valley. Other embodiments, useful especially for experimental verification, comprise wide, thin conductors (corresponding to conventional windings) that are formed on a thin, flexible insulative substrate sheet (Flex Technology) wherein the sheet is wound into a roll with the conductor-formed windings adjacent one another. Alternatively conductors are formed on thin insulative sheets and folded or stacked into layers with the conductor-formed windings adjacent one another. The conductors of the alternative-embodiment devices may be fabricated using flex-film processing techniques. The conductors may be disposed in a continuous spiral or a rectangular spiral configuration and attached to a conventional semiconductor chip via interposers. The conductors are of sufficient surface area to support intended or design currents at intended or design frequencies in both cases substantially greater than is heretofore known due to achievement of very tight coupling across multiple windings. Further according to the invention, a method of manufacture of inductors comprises forming a narrow spiral ridge of substantial depth by etching into an insulative substrate that is typically of silicon, then the substrate is electroplated with a conductor, and finally the valley between the ridges is directionally etched to remove conductor to establish continuous, closely spaced windings of a width substantially greater than conductor thickness or the ridge depth. The manufacturing techniques are adaptable to transmission lines, and capacitors.
The disclosed design parameters allow realization of very small area, large value and high Q inductors when operated at lower frequency ranges suited to power applications, as well as realization of relatively high-Q, small-area inductors at any frequency range for a given process technology. Sizes of such devices make them compatible with many semiconductor chip designs. Inductors constructed according to the invention can achieve inductance values heretofore not achievable in miniature inductors.
The invention will be better understood upon reference to the following detailed description in connection with the accompanying drawing and embedded tables. The written descriptions in the drawings and the tables form an integral part of this disclosure.
Referring to
Alternative designs, are shown in
Device 310 of
Only a few windings are shown for illustrative purposes, but there are normally four or more, up to about ten windings. Various patterns of serpentine traces embedded in ribbon may be realized, differing from layer to layer, although a circular or rectangular spiral is likely simpler to design, to fabricate, to analyze and to test. The embodiment of
More precise tolerances may be achieved where the devices are manufactured in a semiconductor substrate, particularly as herein disclosed. The steps are explained in more detail hereinbelow with respect to actual structures.
The basic steps are as follows:
Step A, a semiconductor substrate of silicon over silicon oxide of suitable thickness is provided. If an interposer design is contemplated, then the substrate is stock material. If the inductor is to be integrated into the same chip with a semiconductor circuit, the circuit is formed first and is usually in the silicon layer the surface of the chip or wafer opposite from the inductor.
Step B, a spiral channel 602 is etched into the silicon substrate that is of sufficient width to leave a spiral ridge of width less than winding width w and of sufficient separation for a winding spacing s to yield a continuous ridge in a spiral surface pattern of a design length, wherein height of the ridge is sufficient to establish winding thickness t. Thus the channel is of a depth corresponding to the design thickness t and spacing s+w in the substrate to yield a continuous ridge in a spiral surface pattern (cf.
Step C, a binding material 606 is applied to the surface of the ridged semiconductor material, for example titanium nitride, tantalum or like common semiconductor-to-metal adhesive. Application is by means of conventional processing, and it should at least cover the length, width and depth of the ridge 604.
Step D, a conductor 608, such as copper, aluminum or gold metal, is plated onto the entire ridge 604, including all tops and sidewalls, and bound to the ridge 604 by the binder. For this purpose, electroplating is suitable, since it is capable of adhering to sidewalls. The build-up depth of the plating process is determined by the intended spacing s between plated facing walls of the ridge 604. The width of the ridge plus the combined thickness of the plating corresponds to the intended width of the winding w.
Step E, the bottom 610 of the channel 602 is etched away, thus forming an air gap between walls of the ridge 604 along its length and forming the winding of thickness t, width w separated by spacing s between windings. Both conductive faces of the ridge 602 are conductively couple across the top. This selective etching process is realized by the technique of directional etching 612. Directional etching includes for example deep silicon reactive etching (the Bosch process), plasma etching or possibly ion beam etching, along a spiral path tracing the bottom 620 of the channel 602. To the extent that side walls may be etched in the process, the electroplating step may include adding sufficient material to the side walls to compensate for residual etching.
Alternative etching techniques, such as use of photoresist patterns are also within the contemplation of the invention. Moreover, the technology to perform the semiconductor fabrication process may be an older, larger-spacing processing technology than is used for fabrication of the associated semiconductor chip. It can now be seen how a high inductance, high current capability, high frequency, high Q, and closely spaced, high-aspect-ratio-winding inductor can be realized that is suitable for embedding on (and eventually in) a semiconductor chip.
The following is a design tutorial leading to an understanding of the parameters employed according to the present invention, plus a description of specific embodiments of the invention made according to these design criteria.
Self and Mutual Inductance Calculations
An excellent source of inductance and mutual inductance calculations can be found in the classic book Inductance Calculations by Frederick Grover, first published in 1946 [1]. Due to demand by those working in the field it has been re-printed many times and remains a valuable source. In that work, numerical calculations of any arbitrary cross-sections for self inductance and mutual inductance of their arbitrary arrangements in spatial coordinates are used. What follows here is a practical guide for design with respect to self-inductance and mutual inductance considerations.
The general formula of the DC self inductance (internal inductance for uniform current density distribution) of a prism geometry with any given cross-section can be given as the general inductance formula [1]:
where l, r, δ1 are in cm and (1.1) gives LGENERAL in Henry units, r and δ1 being geometric- and arithmetic-mean-distance-related quantities, which are related to the cross-sectional geometry of the prism, which is assumed to have a uniform current distribution flowing through its cross-section. Geometric Mean Distance (g.m.d) and Arithmetic Mean Distance (a.m.d) are important concepts in inductance and mutual inductance calculations [1,2]. The “geometric mean distance” (g.m.d.) between any pair of n points can be expressed as,
Similarly, “arithmetic mean distance” (a.m.d.) can be expressed as,
where r1 and di are distances between pairs of points in selected regions as can be shown in
The general inductance formula (1.1) can be written explicitly for specific cross-sectional geometries. For rectangular cross-sections, of the type upon which this invention is focused, Equation (1.1) becomes,
where, l, w, and t are the length, width and thickness, respectively.
For a circular cross-section the general formula Equation (1.1) becomes,
where, r is the radius of the circular cross-section.
For a coaxial or ring cross-section which is also named as a “hollow cylinder” Equation (1.1) becomes,
where, r1 and r2 are the outer and inner radiuses of the coax, ring or the hollow cylinder.
For elliptical cross-section where a and b are the major and minor axes of the ellipse, (1.1) becomes,
A closer look at relations (1.4-1.7) shows that there is a minimum length lMIN as a function of the cross-sectional dimensions where these formulas apply. For the rectangular cross-section, which is the main focus in this invention, lMIN can be expressed as a function of w and t by solving,
The function ƒ1(w,t) is plotted in
A solution of (1.9) for lMIN will give the minimum value for l for which (1.4) will be valid. Below this lMIN value Equation (1.4) will give a negative inductance value, which is not physical. Therefore (1.4) is valid only for l>lMIN. The value of lMIN depends on the sum of width w and the thickness t and can be given as,
Similar calculations can be done to obtain lMIN for other cross-section geometries.
The Neumann integral formulation of mutual inductance for straight infinitely thin filaments (the “Filament Method”) as shown in
where, u and v are unit vectors on each filament.
Performing the integral (1.11) for two parallel lines with a length of Z and spacing d as shown in
To calculate the mutual inductance between any parallel two arbitrary cross-sectional geometries with the same length l—under the assumption of uniform current density distribution—one calculates the (g.m.d) between the two cross-sectional geometries and substitutes the g.m.d. value as the variable d in the filament formula in (1.12).
The “Filament Method” can be generalized for any filament arrangement and placement in three-dimensional space by double integrals in the Neumann integral formulation given by (1.11), again under the assumption of constant current density distribution. For n coupled inductors, where n>1, given as a multi-inductor system shown in
The diagonal matrix entries of (1.13) are self-inductance values, which are always positive. The off-diagonal entries can be positive, negative or zero. The Inductance Matrix L is ALWAYS symmetric as shown.
A quantity that is very important in a mutual inductance matrix for satisfying the passivity requirement of the system is the coupling ratio K, which is expressed as,
where Kij, Lij, Li,i and Ljj are the coupling ratio, self inductances of elements i and j, the mutual inductances between inductances i and j respectively.
For an inductance matrix L resulting from same cross-sectional geometry and lengths will give equal self inductances at the diagonals. Having the same values in the diagonal of the inductance matrix (1.14) states that,
|Ki,j|<1→Li,j≤Li,i (1.15)
In other words, for this case the mutual inductances in the inductance matrix can never exceed the self-inductance values! This is a very important concept that allows for the derivation and realization of the invention herein disclosed.
Inductance for a Rectangular Cross-Section Having a Constant area S and Under Constant Current Density JMAX Across its Cross-Section
As will be explained hereinafter, embodiments of the invention employ a rectangular cross-section. One must always comply with minimum cross-section requirements when designing an inductor for any application. Sources for this minimum cross-sectional area can be many and are listed below, depending on the application;
i) For on-chip power converter applications [3-9], a large DC current must flow through the inductor, at least in the order of several Amperes (1-50 A) [3-9]. This imposes a minimum cross-sectional area SMIN requirement on the inductor design due to the electro-migration current density limit that cannot be exceeded. This electro-migration current density limit JEM is a function of the chip metallization process. As an example, for a typical Aluminum/Si alloy metallization, JEM is in the order of 105 to 2.106 A/cm2. For a given maximum DC current specification, one cannot exceed the current density imposed by the electro-migration current density limit, therefore one cannot make the inductor cross-sectional area smaller than SMIN. SMIN can be calculated as,
where IDCMAX is the maximum DC current determined by the design specification.
Table [1] shows the typical cross-sectional areas that need to be satisfied for some practical IDCMAX values common in today's power management and FIVR work.
ii) When designing an inductor, one always has a resistance RIND in series with the inductor. Again, in power converter applications, the efficiency of a step-down or buck converter is closely related to the DC resistance of the inductor RIND and cannot exceed an RIND_MAx value that is a small load-dependent quantity which can be given as,
where V, η and I are the DC voltage output, power conversion efficiency and load current, respectively. As an example, a 1V DC supply with a 1 A load is equivalent to 1Ω load resistance. For a 90% efficiency goal in a buck converter design with no switching losses, one has to keep the DC resistance RIND_MAX of the inductor less than 0.11Ω. A typical “conservative” FIVR on-chip buck converter specification is 10 A at 1V. As can be seen for this case the DC resistance of the inductor RIND MAX has to be less than 0.011Ω regardless of the inductor value. This can be a major challenge.
iii) The circuit topology of LNA (Low Noise Amplifier) IC designs can employ several on-chip inductors, transformers or Baluns (Balanced-un-Balanced). Since the thermal noise voltage generated in a resistor is proportional to the square root of its resistance at the operating frequency, the resistance value is an important contributor to the overall noise figure of the LNA [31]. Therefore one needs to keep the resistance of these passive elements less than an RMAX value at the operating frequency. The RMAX value at a given frequency for this case is not straight-forward to calculate, but it is related to its DC resistance, and the “smaller the better” principal always applies. The AC-resistance-to-DC-resistance relation is given for rectangular cross-sections hereinafter.
iv) For VCO/PLL (Voltage Controlled Oscillators/Phase Lock Loop) applications the phase noise is inversely proportional to the square of the Q value of the inductor. Q of an inductor. It is a complex quantity to calculate as a function of frequency, but it is very closely related to the AC resistance of the inductor. AC resistance is related to the DC resistance RDC, so again the “smaller the better” rule applies for RMAX!
v) The power consumption limit on the inductor is another design factor in determining the RMAX value at the frequency of operation. It is given by relation,
where PMAX is the maximum power consumption specification at a given operating frequency on the inductor, where RMAX is the frequency dependent resistance of the inductor. Again RMAX is related to RDC.
As can be seen, there is one factor that directly defines the SMIN of the inductor design and there are an additional four factors that are indirectly related to it through the DC resistance formula of a prism, given as,
where l, ρ, S, w and t are the length, resistivity, cross-sectional area, width and thickness for a rectangular cross-section straight conductor.
In any kind of inductor design one starts with a straight wire and generates geometries that give mutual inductances such that their presence increases the inductance compared to its straight conductor inductance value. Therefore, there is a need to formulate a geometrical configuration that provides for high mutual couplings with the proper sign in the designed structure, such as in coils and spiral inductors. Calculating even RDC for any kind of inductor design such as spiral or coil inductors is not straightforward, but it is straightforward to calculate it for a straight conductor. That is a good point to start the analysis.
Optimum Width/Thickness Relation for a Desired Inductor Value L for a Given Cross-Sectional Area S for a Rectangular Cross-Section Straight Conductor Giving Highest Possible Q for Uniform Current Distribution Assumption Across its Cross-Section
The “exact” result of the starting analysis under this model is incorrect, but it is a suitable starting point for the optimization of an inductor, and it conveys the key points and the thought process of the invention very quickly and clearly, as hereinafter shown.
The problem at this stage is to find out if one can design an inductor with a desired value L with minimum resistance R for a given cross-sectional area S. If there is such a width/thickness combination, using this combination will give the highest Q possible for a straight inductor. Ignoring capacitive and high frequency effects on the quality factor Q, the simple case is given as,
As can be seen, the Q formulation (1.20) assumes that both the resistance and the inductance of the straight wire is frequency independent. Therefore the subscript DC in (1.20) indicates the low frequency Q, where L and R are not taken as functions of frequency and where there are no capacitance effects. These effects will be brought in to the analysis later.
First, inductor relation for a rectangular cross-section, as given in (1.4) as a function of given area S is,
As can be seen in (1.21) the width w, in (1.4) is just replaced by Sit. Close examination of (1.21) suggest that one can expect a thickness t, which gives the shortest length l for a desired inductance value L for any given cross-sectional area S. Ideally one needs to differentiate (1.21) with respect to t, equate it to zero and solve t to perform this task. This requires several intermediate differentiation steps in the process. It can be done with simpler and shorter intermediate math and will be more conclusive, as well as get the point across more quickly and clearly. (We will have to take the longer approach for Q optimization later, so no need to complicate the matter at this very first stage!)
Let the u(t,S) function, which is the denominator term in the log function given in (1.21) be defined as,
The t value, which gives the minimum for u(t,S), will satisfy this “minimum length for a given inductance value of L for any given S” condition by differentiating it with respect to t as,
and equating (1.23) to zero and solving gives,
As can be seen in (1.24), there is an optimal thickness t, for a given S and moreover the width w and thickness t are equal, which is directly the result of area relation, giving,
w=t=√{square root over (S)}. (1.25)
The advances in the art that form the basis of the present invention can now be identified. One conclusion is this: To minimize the length of a conductor for a desired inductor value of L for a given cross-sectional area S in a rectangular cross-sectional geometry, one would need a square cross-section with sides given as (1.25)!
The typical metal thickness in IC (Integrated Circuit) technology is less than a micron. Very few IC processes provide higher than about 3μ to 4μ metal thickness and only at the top metal layer (M5) with 2.8μ width and spacing. As can be seen, the thicknesses obtainable from this very first simplified analysis are much larger than any metal thicknesses provided in any known IC process technology, which are shown in Table [1] as tOPT0.
Combining the resistance formulation given by (1.19) for uniform current density distribution, one can plot the Q versus thickness for given L and S values as well and see the peak Q being at the calculated thicknesses. As noted above, the simplified analysis shown here is very important in showing that there is an optimal w and t as a function of a given cross-sectional area S for maximizing Q and it is also independent from the targeted inductance value. Closer examination however demonstrates that this “qualitative” result is misleading. It is misleading in that the resulting cross-sectional geometry, which is said to be a square and is dependent on the given area S, is given as in (1.25). The misleading result comes from the “constant current density” assumption given by (1.19) for the resistance which cannot be satisfied at operating frequencies of the inductors under consideration due to skin and proximity effects. The following section includes an explanation of the non-uniform current density distribution effects in a rectangular cross-section with some detail, taking the skin effect into consideration.
Optimum Width/Thickness Relation for a Desired Inductor Value L for a Given Cross-Sectional Area S for a Rectangular Cross-Section Straight Conductor Giving Highest Possible Q for Non-Uniform Current Distribution Assumption Across its Cross-Section
The general analysis of this problem can be tackled by solving Maxwell's equations for a sinusoidal wave assumption which can be reduced to the solution of the Helmholtz's equation in non-uniform media. Just for the electric field E, Helmholtz wave equation in complex form can be written as [24, 25],
where μ, ε, σ, ω and ƒ are the magnetic permeability, dielectric constant, conductivity, angular frequency and frequency, respectively. A similar equation can be written for the magnetic fields H and it can be shown that they are related [24,25]. A complete spiral inductor analysis can be done by solving (1.26) for the three dimensional spiral geometry (which is possible only numerically). Employing Maxwell's equation which leads to Helmholtz wave equation (1.26) in three dimensions, one can calculate electric and magnetic fields and the non-uniform current density distribution in any point of any of the winding regions [10-23]. This is a complex analysis, but looking at the results of the complex simulations and using some common electromagnetic sense, the analysis can be simplified. Here we will first focus on the principles and the important analytical results of the solution of the simplified Helmholtz wave equation for plane waves, which is applicable to the spiral inductor regions in the interior of its winding as shown in a very simple spiral inductor geometry shown in
The cross-sectional geometry of the spiral inductor structure shown in
In some other applications, such as in RFIC, PLL and VCO's, both of the pins of the inductor have to be connected to the IC. This is illustrated in
When an electromagnetic wave enters a conductive region, such as into the windings of the spiral cross-section shown in
under a “good conductor” approximation which is defined as,
Equation (1.27) simplifies to the well-known “skin depth” [24, 25] given as,
From the calculated electric and magnetic field distributions in the conductor regions of
One can speculate on three possible forms of solutions for the non-uniform current density distribution in the spiral windings:
i) Current Density Distribution is Uniform at the Surface of the Conductors.
This solution cannot apply to the majority of the known spirals which have w>>t. If the width and thicknesses (w,t) are not in the same order and if the distance dG between the ground plane and winding is not on the same order of magnitude as the spacing s, the external field distribution on the conductor surface will be far from uniform and therefore cannot support this boundary condition. Therefore it only has its merit for square cross-sections in conductors having similar s and dG. This mode has an analytical solution for circular cross-sections [24] using Bessel functions (Ber, Bei), but for a rectangular cross-section, one needs a numerical solution of the Helmholtz wave equation where an analytical solution does not exist.
On the other hand, if t>>w and s<<d, and there are vertically stacked inductor winding structures which have w>>t, d (as shown for illustrative purposes in
ii) Majority of the Fields are Confined Between the Bottom of the Conductors and the Ground Plane.
This solution applies fairly well for PCB (Printed Circuit Boards), ribbons and the majority of the on-chip spiral inductors where w>>t and s>dG. For this case a fairly good analytical derivation of the current density distribution can be given, which is once again in line with the solution of the Helmholtz wave equation for the exact structures. This type of current density distribution in the windings is referred as the “single sided solution” in this disclosure. Therefore the straightforward analytical analysis will be given once and for the case related to the invention below.
iii) Majority of the External Fields are Between the Windings.
The solution in this case is applicable to one of the embodiments of the invention explained in this work given as, t>>w, dG<<s. This approximation also applies to the structure where longer sides of the windings are along the x axis, but are stacked as shown in
Single Sided Current Density Distribution Assumption and its Impact on RAC/RDC
Consider an analytical derivation for the conductor cross-section shown on the right of
In reality the electric and magnetic fields can enter from both sides of the spiral windings. For this case the problem becomes more complex for spiral inductor current density calculations in its windings and it is referred as the “complete solution” and will be discussed herein below.
Integrating the current density relation (1.30) from 0 to the width w gives the total current flowing in the conductor and is formulated as,
On the other hand the DC current, where the current density is uniform, is given as,
IDC=J0w. (1.32)
If the windings were infinitely wide, then the total AC current as a result of (1.31) becomes,
1imw→∞(IAC)=J0δ. (1.33)
As can be seen in (1.33), the AC current does not go to infinity as it would in the DC current case! We can ratio the AC current expression (1.31) to the DC current relation (1.32) and get the frequency-dependent AC resistance as,
Rearranging variables in (1.34) gives,
The expression (1.35) is the Bernoulli Generation Function [27] for n=1 defined as,
In shorthand, we refer to (1.36) as B(u). B(u) is a Bernoulli function that will give only positive values for −∞<u<∞ and 1 at u=0 as shown in
As an example for u=w/δ=10, one can right away say RAC/RDC will be very close to 10 without any calculations. If the w/δ ratio is small, by solving the nonlinear equation (1.35) for a desired acceptable RAC/RDC value at a given frequency one can determine the width w as a function of δ.
The top curve in
Table [2.0] shows skin depth as a function of typical frequencies for copper and aluminum. As will be noted the skin depth is on the same order of magnitude as the width dimension of the inductor.
Single Sided Current Density Distribution Assumption and its Impact on Q
In designing a high Q inductor, it is important to calculate the RAC besides the RAC/RDC. The AC resistance can be calculated as,
For a given length 1, substituting the DC resistance relation (1.18) in (1.38) the AC resistance becomes,
With some arithmetic manipulation, (1.39) gives,
As can be seen in (1.40) the width dependency AC resistance is very weak compared to the DC resistance for large values of u!
Another interesting result is that the RAC is no longer directly proportional to resistivity ρ as in RDC. It becomes linearly proportional to the square root of the resistivity and frequency.
Rearranging (1.40) gives,
As can be seen, making width w much wider than the skin depth δ increases the RAC/RDC ratio, but still helps to reduce the RAC.
Thus, making the width w wider does not give much reduction in the AC resistance. Rather it just wastes area and adds more capacitance to the inductor if not carefully calculated (as shown herein below)! It is a better practice to increase the thickness rather than to increase the width for maintaining the same cross-sectional area S!
Ultimately we are interested in a width w of a conductor giving highest possible Q at a given frequency while maintaining the same cross-sectional area S for a desired inductance value of L.
First one calculates the Q of a straight inductor, ignoring all the capacitance effects, under the uniform current density distribution and names it QLRDC, which actually represents a very low frequency case. Applying Q relation given at (1.20) gives,
Doing some arithmetic manipulation gives,
As can be seen, the length l in the front of (1.42) cancels and (1.43) can be written in terms of S as,
Forcing the constant S condition to (1.44) as done earlier allows (1.44) to be written as,
Doing some arithmetic manipulation in the log expression as done earlier gives,
Ignoring the terms after the natural log expression in the bracket approximates (1.46) as,
Finding the maximum or minimum of (1.47) with respect to t requires differentiation of (1.47) as before. With the help of the following variable transformation,
and using the basic differentiation rule [26-29],
gives,
where,
With further arithmetic manipulation,
Simplification of (1.52) gives,
Substituting (1.53) in (1.50) gives,
Straight forward arithmetic manipulation on (1.54) results in,
Equating (1.55) to zero and solving it,
which gives the same result for t as done before with much shorter intermediate math giving,
t=√{square root over (S)} w=t=√{square root over (S)}. (1.57)
Let us denote the optimal thickness given in (1.57) as tOPT0. The advantage of taking this approach is to be sure of the result, as well as finding the peak Q at (1.57), giving,
Doing the arithmetic in the natural log expression gives this very interesting result,
Table [1] above shows tOPT0 for cross-sectional areas determined by desired current values I without violating Al electro-migration current density rules for various large value inductors at 100 MHz. As can be seen, even with the uniform current density assumption, which it will be shown to be incorrect, the required metal thickness values are very large compared to IC process metal thicknesses!
Applying the “Single Sided Current Density Distribution Assumption” in the analysis done earlier by substituting the RAG term (1.41) in (1.42) gives,
Similar arithmetic gives,
Applying the same approximation to (1.61) gives,
where v that appears on the exponent as a function of S becomes,
Differentiation of (1.62) requires longer work, but it will not yield the result as earlier. To apply the chain rule [26-29] for differentiation easily let the following functions be defined as,
Substituting the g1(t) and g2(t) in (1.62) gives,
QLRAC=a·t·g1(t)·g2(t) (1.65)
where,
The derivatives of g1(t) and g2(t) functions with respect to t are,
and,
The chain rule applied to (1.65) gives,
To shorten Equation (1.69) to a manageable representation to perform the analysis more clearly, (1.69) can be written as the sum of y(t) and z(t) functions given as,
where,
The first function y(t) can be written explicitly as,
With some arithmetic manipulation, (1.70) becomes,
and,
After some simple and straightforward arithmetic manipulations, (1.72) becomes simpler. Equating it to zero gives,
where,
By using the relation (1.63) for v, (1.75) can be rewritten using “only” the variable v instead of variables of v and b as,
As can be seen, (1.77) is a nonlinear equation in t and can be solved “only” numerically. Before going into the solution of (1.77) it is useful to see the functional behavior of v, which is an important argument of (1.77) as a function of frequency ƒ. This analytical investigation will also lead to very important results which are the basis of claims of this application without even solving (1.77).
The first thing to note is that v will be “always” a positive number. In addition to that for any material when the signal in the medium is at zero frequency (ω=0), v will become zero (v=0). If we substitute some real values into the v expression given in (1.63), such as for copper (Cu) resistivity, along with the numerical value of μ, v becomes,
It can be shown that (1.78) for Cu, frequencies above 42.7 Hz, the square root term exceeds 1 and increases with the square root of the frequency. Now let's investigate the properties of the solution of (1.77) without solving it. It will show that the uniform current distribution solution is incorrect for frequencies ƒ>0!
i) The Optimal Thickness Tom′ Satisfying the Solution of (1.80) is Greater than S0.5, Giving High Aspect Ratio Conductor Cross-Section!
As can be seen, equation (1.77) is a summation of two terms. If we divide both sides of (1.77) by v we get,
As can be seen, the second term in (1.79) is,
Equating (1.80) to zero and solving t will give the uniform current expression derived earlier, which will give the tOPT0=S0.5 solution. It should be noted that (1.80) will be negative for t>S0.5 and positive for t<S0.5. Moreover (1.80) is zero for t=S0.5. The first term in (1.79) is product of two functions,
Since the second logarithmic term in (1.81) is always a positive number for any practical length l, all we have to do is find the behavior of the first term of (1.81) with respect to v to determine the sign of (1.81). In other words, if the first term in (1.81) is proven to be always positive for any v>0, the relation (1.81) will also become always positive for any length l where we can apply the inductor formula (1.4). This can be done graphically very easily.
For v=0 (ω=ƒ=0), (1.82) becomes a 0/0 type uncertainty, but it can be resolved by using L'Hospital's rule [26, 27]. Differentiating the dominator and denominator of it with respect to v and substituting v=0 in the expression, gives 0 for v=0. It can also be shown that (1.82) has a maximum for v>1 giving 0.2983 as its maximum value at v=1.8. Since it is proven that the first term of (1.79) is always positive for all v>0 values, (1.81) is also positive for any v, l, S and t. In this case the equation (1.79) can only be satisfied if its second term (1.80) is negative. This condition can mathematically given as,
If we rewrite (1.79) as,
where,
and some arithmetic manipulation on (1.84) gives,
a(S+t2)+(S−t2)=0. (1.86)
Finally, equation (1.84) becomes,
(a−1)t2+S(1+a)=0. (1.87)
Solving t from (1.87) gives,
As can be seen, a real solution to (1.88) is only possible if a<1 and can be given as,
The direct result of (1.89) gives,
which, proves our case without even solving the non-linear equation (1.77) at all! Since b>1 for a<1,
tOPT>√{square root over (S)} (1.91)
It also states that since a is a function of frequency ƒ, length l, which defines the desired inductance value L and resistivity ρ. As a result, the optimal thickness tOPT is a function of these three additional parameters, not a just a function of tOPT0=S0.5 as derived earlier for the constant current density assumption. It also has to be noted that (1.90) gives the same result for a=0 which corresponds to zero frequency and for this case b=1 and satisfies the tOPT0=S0.5 result!
Since the cross-sectional area is a given value of S, for tOPT we can also define the optimal width wOPT that satisfies,
S=wOPT·tOPT (1.92)
giving,
As a result of (1.90) and (1.93), the high-Q inductor rectangular cross-section has to be a high aspect ratio cross-section having larger thickness than width, or in other words t>w. This is one of the key insights of this invention.
The aspect ratio ΔOPT=t/w can be defined as,
The same fact could have been proven by writing (1.79) as a function of w instead of t giving,
As can be seen, equation (1.95) is a non-linear function of w. In this case (1.84) becomes,
The solution this time leads to the solution for w of,
giving,
which (1.98) gives the identical result of (1.93) satisfying S=wOPT·tOPT. Furthermore it can also be proven that WOPT<δ, or in other words the shorter dimension of the rectangular cross-sections will be less than the skin depth δ for all of the typical inductor values. Thus (1.97) gives the identical result of (1.93).
As a conclusion of this analysis we can state:
The QMAX for a rectangular cross-section by enforcing the constant area constraint S is a rectangular cross-section having a larger dimension along z axes, which is the thickness t, compared to its width (w). It is NOT a square. Furthermore, there is an optimal thickness tOPT that can be found exactly by solving (1.79) for any given frequency, inductor value and cross-sectional area of the spiral inductor windings. The exact thickness tOPT which is the solution of (1.79) has a weak dependency to resistivity, frequency of operation and the desired inductance value L due to the l dependency in (1.77), but it is a function of these parameters and does not appear in the previously derived tOPT0.
This conclusion is verified in
The top set of curves in each plot of these figures corresponds to the uniform current density assumption. As can be seen, the Q peaks are corresponding to thicknesses of the square root of S at 7.07μ, 15.81μ, 22.36μ and 31.62μ for S=50, 250, 500 and 1,000μ2, respectively, as derived earlier. These solutions are marked with a vertical dotted line in each plot. As can be seen, the thickness for the Q peaks are independent of the L values, but the peak Q value is a function of the desired inductance values taken as 20, 40, 60 and 80 nH as predicted analytically.
The case of forced uniform current density at the surface of the conductor gives two peaks, one below and the other one after tOPT0. It is noteworthy that in this case there is a double peak with a minimum at tOPT0. The reason for a double peak is that a scan of the thickness from 0.1μ to 500μ till t<S0.5 yields a width w that is higher than the thickness t, to satisfy the constant area S condition imposed, and after t>S0.5 the thickness t becomes larger than the width w. Forcing a uniform current density boundary condition at the surface of the conductor gives symmetric results with respect to S0.5.
In the case where constant current density along the thickness (along z axes) is assumed, the curves start with very low Q's for small thicknesses. This is due to the fact that for very small thickness t, will give very large widths, w to satisfy the constant area S condition. All the curves have single peaks, which matches the second peak in the earlier case, because as the thickness increases the surface current density at the surface of the conductor case applicable to the metal geometry. The optimal thicknesses tOPT where the QPEAK for all cases for S=50, 250, 500 and 1,000μ2, at 100 MHz are significantly higher than tOPT0 as predicted by the earlier analysis. However, as can be seen, none of these metal thicknesses shown in
The “Complete Solution Current Density Distribution” for Spiral Windings
In spiral inductor windings the current density distribution in the windings is different than the straight wire with a rectangular cross-section. The magnetic fields in the windings are also a function of the distance of the winding from the center (air core) of the spiral inductor, and also vary along the winding and its z coordinate. One can see this very easily by applying Ampere's law to the spiral cross-section. The magnetic field distribution in the winding is the cause of the all the combined eddy currents, skin and proximity effects. The solution requires three dimensional numerical simulation of the entire spiral inductor. The normalized magnitudes of the magnetic field in the windings for widths of 0.5δ, δ, 2δ, 3δ, 4δ, 5δ and 10δ are shown in
The short summary of the curves related to QPEAK vs tOPT at 100 MHz for different cross-section areas and inductor values is given in Table [2]. More detailed explanations and critical parameters for different inductor values of 20, 40, 60 and 80 nH at 100 and 200 MHz are shown in Tables [2.1-2.4] below.
Performing the analysis at any frequency gives similar results, indicating that a thick metal with widths in the order of the skin depth is needed to achieve a high-Q straight inductor. Spiral inductors can be thought of as straight lines which are coupled with desirable sign and highest possible mutual inductances. The following section is related to pointing out the inherent advantage of spacing the high aspect ratio thick metals, again with high aspect ratio spacing rules for making very high performance spiral inductors.
Since thick metal processes on the order of metal thicknesses shown in
Inner Space Dimension Optimization of the Spiral Inductor
Spiral air-core inductors have an inner space where there are no windings. The geometry of inner space can be almost anything, but in most practical applications they are circular, rectangular, square or octagonal areas. Among these four most commonly seen inner space geometries, probably the square inner space geometry is the most popular geometry due to many reasons, such as better packing density, ease of design and better performance compared to rectangular geometry from any design specification. The most critical part in area reduction in spiral inductor having a constant spacing s between windings is winding width w and the inner dimension dIN, where the spiral inductor windings start and winds outward from this square shaped inner geometry. Having thick metal and using the high aspect ratio metal rule as herein taught minimizes the spiral area very significantly and improves high frequency performance as shown above. Similar optimization is needed for optimizing the inner dimension of a square inner space, which can be extended to any type of inner space geometry. The present invention reveals that dIN optimization should have a minimum inner dimension greater than a mathematically defined dINMIN.
To make highly efficient high coupling metal structures, one needs to consider also the Q value of the individual structures, such as each leg, besides their highest possible mutual inductive coupling ratios with other legs, as explained above. The use of high coupling ratio legs with individually low Q structures increases the loss and does not contribute to the inductance value at elevated operating frequencies. The analytical expression for QLRAC (1.62) shows that QLRAC (l, S, t, ƒ) has a logarithmic length dependency. This is clearly shown in the QLRAC (l, S, t, ƒ) plot in
According to the invention there should be no inductive structure, such as any leg in a spiral inductor, having its individual QLRAC<1 for the operating frequency of the spiral inductor. The smallest leg length in a spiral inductor is determined by the inner dimension dIN as shown in
According to this invention, a minimum inner dimension dINMIN value is calculated with the analytical relation (1.62) having lengths supporting Q(dINMIN, S, t, ƒ)>1 for a selected cross-sectional area S and thickness t at the operating frequency. As can be seen in
Another advantage of a larger inner dimension dIN is seen in the reduction of mutual inductive coupling between inductor legs on both sides of the inner space of the spiral inductor. Since these inductors have coupling ratios of opposite signs, minimizing the coupling ratio will increase the inductance L and therefore increase the Q of the spiral inductor. Mathematically stating, the s<<dIN condition must also be satisfied! On the other hand increasing the inductive coupling between inductor legs on the same side of the inner empty space increases the inductance value L, thereby increasing the Q of the inductor. Since one generally is interested designing a specific L, one will achieve this design goal with shorter wire length, giving less resistance and capacitance resulting in higher Q.
Increase of Mutual Inductance by Using High Aspect Ratio Metal Giving Higher Q and Smaller Area for a Desired Inductance Value
It has now been mathematically proven that high aspect ratio rectangular cross-sectional geometry in the z dimension, facing their larger dimensional sides to each other, yields a definitive advantage in giving high Q spiral inductors, due to giving smaller RAC at any frequency of operation compared to placement as in prior art placement with the smaller dimension facing each other. Having rectangular cross-section conductor windings facing their larger dimensional sides to each other unexpectedly yields much higher mutual inductive coupling compared to facing the smaller sides together for the same spacing s. Having high inductive coupling between the legs increases the inductor value of the spiral inductor reducing the total length of the winding for a desired inductance value L and consequently reducing the resistance and giving higher Q. This fact is due to the geometric mean distance (g.m.d) reduction of the geometries if arranged as herein disclosed. The leg structures for spiral inductors according to the invention are shown in
Total Inductance Calculation of a Spiral Inductor Using Circuit Theory (Partial Inductance)
An easier way of explaining the total inductance calculation of a spiral inductor from its metal geometry is through circuit theory, rather than electromagnetics theory through the “Partial Inductance” concept [1, 10-24].
We can represent the width and spacing of windings as shown in
It is a good practice to have a quick method of estimating the number of turns needed to design for an inductor value L for a given t, w and s rule having the dIN as a parameter, assuming that each side will have the same number of turns. Although the final structure of a computed designed will end up different, this assumption will give a good initial approximation of the spiral size and idea of the inductance matrix terms, which is very important.
As can be seen the distance d, in the mutual inductances formulation given in (1.12) will be replaced by the geometric mean distances (g.m.d) between the cross-sectional metal windings. For any cross-sectional geometry and the numbering given in
The negative signs in the inductance matrix (1.99), which are for the leg inductors in the opposite sides of the inner space, originate from the current direction going in or out of the reference bubble placement on each mutually coupled inductor of the spiral inductor. In any case the inductance matrix will be a symmetric matrix. Since the leg width w and spacing between the legs s in each side are kept constant and dIN>s, the following relations between the magnitudes inductance matrix elements also holds for any winding aspect ratio having the same numbering as given in
Since the length of each leg (l) is greater than the inner lengths, one can also indicate that,
l3=l6>l2=l5>l1=l4=dIN L6,6=L3,3>L2,2=L5,5>L1,1=L4,4 (1.101)
The passivity requirement as given in (1.14) also holds between the diagonal and off-diagonals of the inductance matrix having coupling ratio K<1 between the diagonals and off-diagonals as stated before. For an equal length assumption, this will result in diagonal entries of the inductance matrix being always larger than any of the magnitude of the off-diagonals.
Identical relations can be given for the “x cut” of the spiral inductor in
where the Lxcut and Lycut are (6×6) sub-matrices having properties as given in (1.100)-(1.101).
The total effective inductance of the spiral inductor under the assumption of having the same current passing through each leg of it then becomes the sum of all terms of the (1.102), which is a (12×12) matrix. Since Lxcut and Lycut (6×6) are identical sub-matrices, the whole operation for calculating the effective spiral inductance of a spiral inductor having three complete turns can be reduced to,
where n=6 and Lij's are the Lxcut or Lycut are the (6×6) sub-matrix terms in (1.103). To increase the inductance of the spiral inductor then one must increase the positive coupling and reduce the negative coupling of the inductance matrix as given in (1.103) which is basically with properties given in (1.100) and (1.101) for a 3 turn spiral inductor. The negative couplings can be reduced as one increase the dIN and the positive couplings can be increased by reducing the spacing s, between the windings.
The geometric mean distance (g.m.d) between two physical rectangles, which has w>>t, increases with width w and is a weak function of spacing s, even for zero spacing s between them W. Therefore putting wide and thin rectangles closer does not increase the mutual inductive coupling between them significantly, which is not very obvious. This is illustrated in
The reason for selecting (for analysis) infinitely thin rectangles having w=0 is to show the (g.m.d) versus thickness relation to be reconstructed very easily by anyone by the use of tables given in [1]. The plot of the related table for calculating g.m.d as given in [1] is given in
The insight is reducing the geometric mean distance (g.m.d) between rectangular cross-sections of the windings by arranging them such that they have high aspect ratios and facing larger dimensions toward each other, as according to this invention. As shown in [1] the (g.m.d) versus thickness for high aspect ratio rectangles arranged as said will be a function of the aspect ratio of the metals themselves and weakly dependent to the spacing s between them. This is illustrated in
In summary, the advantage of placement according to the invention lies in optimizing mutual inductance and self inductance. One needs to plot the mutual and self inductances as a function of thickness. The (g.m.d) versus thickness plot explains the reason for the increase in mutual inductance that is shown; therefore it is important to have them presented before.
As a result the proposed metallization process in this invention is High Aspect Ratio Metallization along with High Aspect Ratio Metal Spacing, “HARMS.” This results in a “Tight Coupling Condition” between the windings which can be expressed only with an aspect ratio of metal ΔM and the adjacent winding aspect ratio between the spacing ΔS independent of metal thickness!
“Tight Coupling Condition”
The definition of “Tight Coupling Condition” as herein given according to the invention is such that not only the adjacent legs are tightly coupled with large coupling coefficients K, but also, where there is more than two legs or segments of windings, a number of the next closest legs are also coupled strongly with large coupling coefficients K. The advantage of this is clear from the inductance matrix and the total inductance formulation given in (1.99-1.103). Since the effective inductance of the spiral inductor is the sum of all of the inductances in the inductance matrix, increasing their coupling will increase the inductance value. Due to the passivity requirement, one can never increase the maximum mutual inductance value between any legs more than the value as given in (1.15).
One can represent the width and spacing of windings as shown in
and
where ΔM and ΔS are both significantly larger than 1. It is clear that the spacing aspect ratio of winding number 0 to 1 is,
The spacing aspect ratio of winding number 0 to 2 also becomes a function of the metal width w of the winding number 1
One point clearly evident from (2.4) is that the ΔS(2) can never be larger than ΔM! Therefore as long as ΔM<1, as in most of the prior art spiral inductors, ΔS(2) will always remain less than 1 for any spacing s>0 value. Therefore it is proper to call this condition of having ΔM>1, the “necessary condition of tight coupling.” The spacing aspect ratio of winding number 0 to 3 similarly becomes,
Recursively one can formulate that the spacing aspect ratio of winding number 0 to n becomes,
As can be seen in (2.6) ΔS(n) will get smaller with increasing n and again it will always be smaller than ΔM/(n-1) regardless how small s is taken! Substituting (2.1) and (2.2) in relation (2.6) can be written as,
Eliminating t from (2.7) gives,
As can be seen, (2.8) is only functions of metallization parameters ΔM and ΔS and can be simplified to,
The goal then becomes to find which combination of ΔM and ΔS values can give ΔS(n)>1 for n>1. With some simple arithmetic, (2.9) becomes,
One is interested in representing n which becomes larger than 1 from (2.10) having ΔM and ΔS as independent process parameters that we need to enforce. This requires the solution of n from (2.10) as,
Solving n from (2.11) is fairly straightforward, giving,
and resulting in,
As pointed out earlier as the “necessary condition of tight coupling” is ΔM>1, it is logical to plot (2.13) as a function of ΔM and as a family of curves for several ΔS.
The Total Inductance and Q Increase with “Tight Coupling Condition”
Although
The placement of such high aspect ratio spiral inductor windings ΔM along with high aspect ratio adjacent spacing ΔS according to the invention also results in several other additional important advantages over prior-art arrangement which need to be mentioned.
i) Area Reduction for Same Number of Turns and Inner Dimension dIN
Area reduction according to the invention is fairly straightforward and it is an evident advantage of the preferred arrangement of windings, but this has a very practical advantage. It is a geometry-driven advantage. There is no need for electromagnetic analysis. Simply stated, the spiral outer dimension will be smaller if one uses smaller width and spacing. As shown in
dOUT=dIN+2·dW. (2.14)
On the other hand, the winding width dW is related to w and spacing s as,
dW=s·(n−1)+w·n (2.15)
where n is the number of turns.
Even if there was no increase in the mutual inductive terms between legs as was shown earlier, according to the invention, a very significant reduction in the total spiral area can be achieved as shown in (2.14) and (2.15). As an example, if the cross-sectional area S is kept constant, for a thick and high aspect ratio metallization process (2.15) becomes,
Expression (2.15) can also be written in terms of ΔM and ΔS for a given metal thicknesses t=50, 100, 200 and 300μ for number of turns n=5 as a function of ΔM and the results are shown in
ii) Dead Area Generation Reduction, Reduction in R, C and Increase in L for Same Number of Turns and Inner Dimension dIN
The advantage obtained for this case of dead area reduction is not as straightforward and evident as in the previous case, but it has a significant effect on resistance and capacitance reduction along with area reduction in spiral inductors.
leff=l−w (2.17)
Again by using the constant S rule to maintain a desired cross-section, (2.17) becomes,
Assuming uniform current density along z axes, the additional “dead area” resistance is,
Where ρ is the resistivity of the metal winding. This dead area for each turn can be also given as,
This “dead area” will produce an undesired capacitance increase for each turn proportional to (2.20). As we can see in (2.17)-(2.20), according to the invention, increasing the thickness t increases the inductive portion of the spiral, reduces the “dead area” thus giving smaller parasitic capacitance and resistance and all this results in a smaller spiral with higher Q.
iii) Overall Capacitance Reduction
Unfortunately the above effect cannot be shown analytically as easily and as clearly as has been done for inductance increase and decrease in the resistance on a per-leg basis. Increasing thickness will also increase capacitance per length. Assuming a parallel plate approximation, each interior leg will have capacitance as,
As can be seen, the capacitance of each leg will increase with increase of the thickness t or the aspect ratio of the leg-to-leg spacing ΔS. Deciding what capacitance per leg is acceptable for an inductor value L is not analytically obtainable with reasonable and acceptable approximations. A possible solution is to plot each leg resonance frequency as a function of space s. By not making s smaller than the self resonance frequency compared to the desired frequency of operation looks like a solution, but that can be misleading. Therefore it is not presented in this work.
On the other hand the designer has control on the design parameter s in a rectangular structure which is not generally true in a stacked inductor structure. In stacked inductor cases, metal spacing between layers is determined by the process, which is not in the control of the spiral designer. On the other hand the designer in this thick metal large aspect ratio interposer structure has control on spacing s, which offers very useful design flexibility. However, the analysis must be done as a full spiral analysis, not a leg by leg basis. Using high aspect ratio metal spacing increases mutual coupling between legs; therefore the spiral inductor value L can be realized in a smaller area or a smaller number of turns, yielding desired smaller capacitance values per leg. The designer can design the spiral with a complete analysis using PowerSpiral software (a commercially available tool provided by OEA International of Morgan Hill, California). Therefore, the Q value at the frequency of interest can be plotted easily as a function of spacing, and space optimization can be done on an inductor-by-inductor basis as the last step.
iv) Much Better Inductance vs. Frequency Property
As can be analytically proven [24,25] for circular and as shown earlier for rectangular cross-sectional rectangular conductor geometries, the RAC/RDC will increase with the square root of the frequency after a corner frequency ƒC, defined as a ratio of the plane wave skin depth to some geometrical parameters related to the cross-section of the conductor. According to the invention, by making the windings high aspect ratio with the widths not exceeding skin depth one already increases the corner frequency ƒC very significantly compared to prior art spiral inductors, but still the RAC/RDC will increase with the square root of the frequency. Therefore if one merely takes into consideration only the square root increase of the RAC/RDC with frequency, the Q(ƒ) relation as given in (1.20) becomes proportional to the square root of the frequency instead of being a linear function of frequency!
The internal inductance LINT, of the conductor behaves in a completely opposite manner; the LACINT/LDCINT will decrease with the same ratio as the RAC/RDC with the increasing frequency. The Q(ƒ) relation as given in (1.20) then becomes approaching a finite value, not increasing as a linear function of frequency or proportional to the square root of the frequency by only taking the resistance increase with frequency! Luckily the total inductance has two components being the internal LINT and external inductance LENT. External inductance is due to the mutual coupling terms in the overall structure and is nearly independent of frequency. Therefore the total inductance does not decrease continuously as a square root function of frequency; it approaches to the external inductance value LENT and the Q(ƒ) relation as given in (1.20) then becomes again proportional to the square root of the frequency, which is a very good property as far as building inductors is concerned. According to the invention, by employing the tight coupling condition, the spiral inductor inherently has much larger external inductance LEXT component and therefore the decrease of the internal inductance with frequency is reduced significantly compared to the prior art spiral inductors. One may define a figure of merit ƒMERIT as,
This ratio in tight coupling condition is a larger value than 0.6 meaning that in any case the LAC/LDC ratio cannot be less than ƒMERIT at any frequency!
v) “Image Spiral” Coupling Reduction
In a typical application of spiral inductors there can be conductive regions on top or bottom of the spiral inductor such as ground/power planes, metallic lid of the package etc. in the z direction. At these highly conductive regions the intended spiral inductor can produce eddy currents and generate loss which is fairly difficult to simulate accurately. At the extreme case one can assume that these highly conductive regions acts like infinitely large perfect ground planes and there will be an “image spiral” formed with respect to these perfect conductive planes but carrying an opposite directional current flow in it with respect to the intended spiral inductor [24,25]. A proper approximate equivalent circuit simulation for this assumption will be simulating two coupled identical spiral structures separated by twice the distance dz to these highly conductive regions, where the input and output pins of the image spiral are shorted. Higher coupling between the legs of the intended and the image spiral will cause a larger reduction of the effective inductance of the intended spiral inductor. As shown earlier with the tight coupling condition, the inductive coupling between the windings in the (x,y) direction is kept very high. On the other hand the inductive coupling in the z direction is inversely proportional to the thickness t of the windings, not the distance dz between them! Having winding thicknesses tin the order of 100-300μ in accordance with the invention increases the critical distance where the unwanted image spiral effect can become significant. On the other hand, having wide spiral windings with adjacent windings of small thickness among each other, as prior art spirals, the z directional inductive coupling is very large, (parallel rectangular structures placed wider sides facing each other) as shown in the tight coupling condition. As a conclusion, the tight coupling condition defined herein—as having ΔM and ΔS on the order of 10 and larger—reduces this image spiral effect very effectively!
Full PowerSpiral Simulations Showing the Effectiveness of the Interposer Metal Thickness on Spiral Inductor Performance
Until now, the advantage of using a thick metal with large metallization and spacing aspect ratio for spiral inductor performance has been shown analytically under certain approximations to give clear understanding of the non-obvious issues. In this section is a description of full 3D electromagnetic simulation results for inductor specifications. This would not even have been thinkable with current metal processing rules for IC's, MCM's, PCB or any known advanced packaging technologies. The inductor values to be designed are taken as 5, 10, 20, 40, 60, 80, 100 and 200 nH. Anything above 10 nH is basically considered unrealistic values for any known process. To raise the design goal even further, the specification for DC resistance is kept to very small numbers as needed in FIVR work geared for 100 MHz switching frequencies. The results are given in self-explanatory tables in Table [3.1] to Table [6] for metal thicknesses of 50, 100, 200 and 300μ.
All of the simulated metal thickness, spacing and widths are possible in the existing interposer technology, so these are not fictitious metallization rules. As can be seen, the interposer technology with correctly suited metal thickness can deliver these heretofore unheard of large value inductors in the order of 1 mm by 1 mm size yielding heretofore unheard of performance, not even reported for small-value on-chip or in-chip inductors!
As can be seen in Tables[3.1] to Tables[6] for high efficiency, high current buck converter applications for a load current in the order of 2 A, the RDC<20 mΩ limit as given by (1.17) can be achieved with 300μ of metal thickness and up to 20 nH values giving maximum inductor current of 180 A realized in an approximately 1 mm by 1 mm area. This means that larger load currents can only be achieved by having multiple inductors driven by Poly-Phase architectures [3-9].
The small size of even unheard of large inductors allows many inductors to be integrated on the interposer and opens up large opportunities in FIVR and RFIC design space and even allows multiple FIVR architecture. This represents a major breakthrough achievable with miniaturization according to the invention.
In reality one cannot come up with a standard IC metallization process having any desired large values for ΔM and ΔS as shown and described in connection with
Even if we speculate that one develops an IC metallization thickness in the order of 20μ with the same etching rule presently giving ΔS=1.42, we still cannot meet the “tight coupling” condition. As a result we need to come up with a metallization etch process than can give the desired minimums of ΔM=10 and ΔS=5-10, which is probably not possible today and for some time in the future. Instead, the present invention provides an alternative technique for realizing such structures.
Silicon etch technologies offers such an alternative. Silicon etch technologies have improved very significantly over the years[34-35]. Si etch structures with aspect ratios (depth/width), exceeding even 25 have now been demonstrated. These processes are used in Silicon Through Via (STV) technologies, 3D stacked packaging, Micro-Electro-Mechanical Systems (MEMS) and many more other applications[36-41]. The present invention exploits the underlying processes in a whole new field of applications, giving what the present inventor has designated as the “HARMS” process. However, HARMS uses the high aspect ratio Si etch capability similar to Deep Reactive Silicon Etching (also known as Bosch processes)[33], in a reverse mode of trenching. Similarly, the method of metallization which is used in “HARMS” technology is derived from the totally opposite usage of the STV technology. In STV Si is etched, making a void or a deep trench and the void or the trench is filled with metal. In “HARMS” technology according to the invention, Si is etched creating a “wall” or a “column” herein called a “Si Core,” and the metal encapsulates the “Si Core,” creating the spiral windings and pads which will be the spiral inductor electrical connections to the external circuits. The encapsulating metal thickness is restrained to on the order of skin depth k×δ where k=1.6-3.85 as claimed before giving RAC/RDC<2 at the desired frequency of operation of the spiral inductor.
Current HARMS processing guidelines are outlined in Table [7] as shown below for several desired “final” dimensions.
i) As shown in
ii) If the desired thickness of spiral inductor windings is greater than 200μ, like in many applications shown earlier, there is no need for SOI wafer, a traditional Si wafer with a thermally grown thick (1μ-2μ) layer of SiO2 will be used as the interposer starting material. As hereinafter explained in connection with the final result,
Fully integrated IC applications (without interposer). Instead of building an interposer and connecting it to the IC with C4 bumps, the whole structure can be formed as one unit. The bottom of the buried oxide region is of standard wafer thickness, on the order of 300μ-500μ, and is not used for anything other than providing mechanical handling capability for the processing steps that follow. Therefore according to this invention the spiral inductors are built in the “unused” thick under portion below the buried oxide and connected to the active device area by etching holes in the buried oxide and connecting to the first layer metallization in the active device area. In both starting materials, which can be SOI or SIMOX wafers, the IC will be built with standard processing steps on one side of the buried oxide, which are designated in the following figures as the active layer. The results of three different but related processes are illustrated in
In the SIMOX processes, the active devices are built on top of a very thin silicon layer (typically on the order of 200 nm). The buried oxide is formed by deep oxygen implant and annealed after forming a buried oxide structures on the order of a thickness of 20 nm. This thickness of oxide will not act as a etch stop for deep silicon etch, which will be done in the substrate.
In all three noted processes, after the IC formation process is complete, the spiral inductors will be built below the active device and will be connected by etching the buried oxide and depositing metal from the other side connecting it to the previously deposited metal earlier in the active device formation step.
In
Step 7 (
To achieve a suitable interposer structure with C4 bumps, it is necessary to embed the inductor and its terminals in a dielectric material. Step 10 (
Pads in the HARMS process have two main functions and their geometry are preferably kept as a square with a dimension of WPAD, larger than spiral windings w, regardless of the total width of the spiral windings was shown in
The first function of the pad is to provide a low resistivity path from the solder bump on top of the interposer to the bottom of the thick spiral windings which is in the order of 300μ, while solder bump rules for electrical connectivity is maintained. Their placement and size are basically dictated by solder bump rules which have pad size which are in the order of 75-100p placed in a given periodic “pad array spacing rule”. Having pads in an array, rather than arbitrary placement, brings ease in the alignment between the interposer and the bumps on the IC.
Step 11 is the provision of a pad etch for a single pad. Having a pad with a single-square Si pad core as shown in
However, to further reduce resistance to the solder bump on top of the interposer to the bottom of the thick spiral winding and to create a better contact, the underlying structure can be built as an array of square Si Columns spaced more closely than the 2δEP that is typically used in array spacing as shown in
Referring to
Since electro-plating steps for spiral structures require an electrode used for electro-plating, all the spiral structures must connect to this electrode during the electro-plating process. The wafer-scale connections are formed by constructing a grid as in
As can be seen in
The second function of pads in a structure made according to the HARMS process is to create STVs. Making pads as an array of square Si columns with the spacing smaller than the 2δEP as shown in
The Scanning Electron Microscope (SEM) photos shown in
If there is a need for a larger current and/or lower DC resistance, then there are two parameters to adjust as shown in
In general since one defines the frequency of operation, to maintain the RAC/RDC<2 condition, the encapsulating electro-plating metal thickness δEP is already a set parameter, leaving only one parameter t3Si for setting the HARMS process.
Since a good yielding and controllable HARMS process can be realized with some set rules, such as a minimum Ta deposition width of 2μ, thickness of 0.5μ and Si Core aspect ratio ΔSiW<25 and the desired electro-plating metal thickness OEM, the relation between the desired finished dimensions of the spiral inductor and the Si Core dimensions will be non-linear as shown in
The processing difficulty in having STV's using a SiO wafer is clearly demonstrated in
Further Use and Application of the “HARMS” Interposer Technology:
Low Impedance Power/Ground Delivery Network for High Power IC's
As can be seen in
Shrinking IC process geometries results in increasing current density distribution per area in IC's and lower supply voltages dictated by scaling rules. Distributing these high currents with an acceptable voltage drop has always been a challenge, but now it is becoming an even a more difficult task. One of the main reasons of seeking FIVR is also related to find a solution to this problem, dropping 1.8V supply to 1V with high efficiency on the IC itself which also can be controlled by processor activity.
“HARMS” interposer can give a fairly easy solution to this problem. Considering a tSi=300μ and 8μ of Cu electro-plating giving total width of 32μ of spacing width as shown in
The effect of Si Core thickness on the inductance of a simple power/ground delivery network can be shown comparatively very clearly for cross-sections shown in
Table [8.1] illustrates that one can achieve over 3A current due to enlarged cross-sectional area with minimized resistance and inductance, whereas no one else today can come even close. The best that can be done today for 5 mm wire length (t=4μ, w=2.8μ, s=2.8μ and for JMAX=2×106A/cm2) is a maximum current of less than 225 mA. L11=7.792nH, L12=6.467nH, L13=5.79InH, LlooP=1.325nH, Rcu=7.7Ω, S=11.2μ2, IMAX=224 mA. Conclusion: Width needed for the same cross-sectional area S=153μ2is 38.25μ
The columns 3-4 in Table [8.1] show the first row of the 3 by 3 inductance matrix which corresponds to a VSS/VDD/VSS parallel power delivery network having a length of 5 mm (5,000μ) with a thickness of 50μ and width of 5μ of Cu width. The even spacing between the VSS/VDD/VSS parallel power delivery network is 10μ and 5μ as shown in rows 2 and 3 in Table [8.1]. Column 6 is the half of the loop inductance for just the VDD/VSS pair. Column 7 shows the ratio between the diagonal element of the inductance matrix to the half loop inductance, which is a measure of inductance reduction ratio compared to a loop having an infinitely far return path. As can be seen, the reduction of the inductance is very significant. Such figures cannot even be achieved in PCB's with ground planes!
The note below Table [8.1] compares the prior art using the thickest possible metal thickness of 4μ of Cu with space and width of 2.8μ. Inductance, resistance reduction and the increase of its current carrying capabilities of a power/ground delivery network using the inventive HARMS process, even with for a 50μ thick Si Core, as here, compared to the best suitable process for this application is simply off the charts! The last note below the table shows the needed metal width for achieving the same resistance and current carrying capability using the thickest metal process being 38.25μ compared to w=5μ used in the HARMS process with basically insignificant reduction in the half loop inductance value compared to the given value of 1.325 nH where the HARMS process can give a value of 0.402 nH!
Similarly columns 3-4 in Table [8.2] show the first row of the 3 by 3 inductance matrix which corresponds to a VSS/VDD/VSS parallel power delivery network having a length of 5 mm (5,000μ) with a thickness of 300μ of Cu width. The even spacing between the VSS/VDD/VSS parallel power delivery network are taken as 60 and 30μ as shown in rows 2 and 3 in Table [8.2]. The last note below Table [8.2] shows the needed metal width for achieving the same resistance and current carrying capability using the thickest metal process being 1,377μ compared to w=30μ used in the HARMS process with insignificant reduction in the half loop inductance value compared to the given value of 1.325 nH where the HARMS process can give a value of 0.388 nH!
Utilizing an interposer designed using the HARMS process as a VDD/VSS strapping is very clearly demonstrated with the Table [8.1] and Table [8.2] is a great advantage in any high-current-consuming IC VDD/VSS network design. Basically having the VSS shield in very close proximity to VDD, the very high mutual inductance obtained by this arrangement will generate a very small supply loop inductance, much less than VDD line self-inductance by itself. In addition to this the power delivery network will have a fairly large distributed capacitance with very small series resistance. The capacitance for 5 mm long VDD/VSS pair is given as the 7th column of Table [8.1] and Table [8.2] are significantly larger values that without this invention are not possible to realize in any conventional IC processes today. None of these desirable properties can even be achievable in any packaging, MCM, thin film, thick film or any PCB technologies available today. Hence this invention represents a significant advance.
Integrating Large Value Decoupling Capacitors Using PZT/PLZT Material as Dielectric in Selected Areas in the HARMS Process
In order to guard against large current spikes in any IC there is a need for placing high value decoupling capacitances as close as possible to the noise generating circuits in the IC. Low impedance VDD/VSS network design as explained above reduces this problem but due to high speed and small clock-skew requirements especially in processor designs, there is always a need for high-value on-chip decoupling capacitors. Placing large-value on-chip decoupling capacitors wastes a significant area. However, these can be integrated in the HARMS process which already has a very large distributed capacitance by depositing PZT/PLZT material as dielectric in selected areas between interdigitated fingers that form the capacitance plates. These materials are also known as ferroelectric materials (Lead Zirconate Titanate) [Chemically PbZrxTi(1-x)O3 (0≤x≤1)] and can have very large relative dielectric constants, on the order of 300 to 10,000 depending to their doping, which can completely eliminate the need for large value off-chip decoupling capacitors or large capacitor values needed in the circuit design. The capacitor structure according to the invention is as shown in
Integrated Controlled Impedance Transmission Lines in IC Technologies
Constructing controlled-impedance transmission lines in any semiconductor process is a challenge. For semi-insulating substrate semiconductor technologies such as in GaAs IC's it is a simpler problem but due to the requirement of low resistivity lines they occupy a large space. In silicon IC's, due to the finite conductivity of the silicon material the issue of “slow-wave” phenomenon is a serious issue in addition to the large area requirement.
The transmission line characteristic impedance Z0 can be given as,
where R, L, G, C and ω are resistance, inductance, conductance, capacitance per unit length and angular frequency respectively. As can be seen in (2.23) one needs small R and G values compared to Lω and Cω to produce a good transmission line. This condition gives nearly frequency independent Z0 with its well-known approximation as,
Since the Si Core technology disclosed herein gives very low resistance per unit length values of legs or segments in a much smaller footprint as shown in
Implementation of Spiral Structures in Flex Technology
In the absence of truly thick and high aspect ratio metal (HARMS) interposer technology, for test and verification purposes, spiral structures were built and tested using Flex PCB technology according to the present invention as hereinafter explained to access performance improvements and estimate performance gains when such an interposer metallization process became available. Flex PCB technology is well known as a flexible form of printed circuit board (PCB) technology wherein conductive layers insulated by a dielectric and formed flexible sheets or strips are used to form circuitry. Flex PCB technology has never before been applied to the present use. Since development of any IC metallization process with any non-standard requirements is an expensive and a long process, it is helpful to show performance results using a much cost effective way to justify the work. Nevertheless, it was determined that Flex structures are also useful in and of themselves and for this reason they are disclosed herein as a type of miniature inductor. Two types of Flex PCB-based spiral structures are disclosed and have been constructed for test purposes and possibly practical application, herein designated single-layer and folded single-layer, both forming stacked multiple-layer structures that come within the scope of the present invention.
The main purpose of the Flex structures disclosed herein is to be able to generate structures that are easy to build with very limited mechanical skill and resources and that verify theoretically derived “tight coupling” conditions. However, using miniature mechanical production equipment, all of the Flex structures herein describe can be miniaturized with ease.
Type 1 Flex Structure: Flex Spiral Structures:
The first type of Flex PCB-based spiral structure was constructed by using a standard Flex PCB technology with a number of different metal line widths wound around a dielectric core radius larger than the minimum radius of 32 mil (812.8μ) specified by the Flex technology parameters shown in
The thickness of rolled copper according to the standard Flex PCB technology process employed is shown in
A major issue to consider is the connection of Flex spiral structures to a PCB, where several arrangements have to be made for measurements. One obvious choice is to use a Flex-to-PCB connector, such as a Type 52015-3TE AMP. This 3-pin flat connector has a width of 493 mil (12,522.2μ) and a length of 273 mil (6,934.2μ). With connection dimensions as shown in
Since the connection to a PCB disposed below will be done as shown in
Having dIN=500 mil and the trying to meet the goal of achieving a spiral-inductor-dominated measurements, the minimum number of turns should be greater than five. A five-turn Flex spiral inductor will have spiral winding length of 9,500 mil (plus the needed extension sizes for connections as described above).
Using a three-pin connector, such as a Type 52015-3TE AMP connector, allows embedding three different trace widths for the same number of turns in the same Flex layout and brings space saving advantage in a measurement setup. Vertically stacked three-inductor Flex structures as shown in
The Flex spiral with three traces having 5, 10, 20 trace widths with 10-mil spacing and 10-mil clearance from the edges as shown in
The end points of the Flex-to-PCB connector extension region have stiffeners to assure good connectivity between the Flex traces and the connector. The PCB cutouts should be at least 500 mil high and wide enough for the Flex-plus-stiffener thickness to allow the Flex connection to connect to the underlying PCB. Having an underpass region at a distance of the PCB thickness away from the bottom of the Flex spiral for its B connection reduces the capacitive and inductive coupling to the windings, which also improves performance.
Type 1 Flex Spiral Structure for PCB Transformer and Balun Structures with A SINGLE NUMBER of Mechanical Winding Process for Desired Voltage/Current/Impedance Conversion Ratios
Many applications require small, high-performance custom transformers and baluns on a PCB.
The center area of such a wound structure can also have a magnetic core, which is another way of increasing the inductor values very significantly in the same area for miniature transformer/balun/inductor structures very easily.
Type 2 Flex Structure: Folded Flex Coil
The second type of Flex-based spiral structure, the folded Flex coil, also demonstrate the multi-layer stacked inductor structures with dimensions similar to type 1 Flex inductors. Since high via resistance and current redistribution in the via-to-trace transition region are major factors in performance limitation and area of a PCB, the inventive multi-layer Flex inductors may be built with no vias by folding a serpentine structure on itself. This way one can have a single layer flex structure with a serpentine pattern as shown in
The serpentine metallization track widths may be the same used in a Type 1 Flex structure, being 3, 6, 12, 13, 15 or 20 mil, drawn around the same inner space dIN=500 mil to make a fair experimental comparison between vertical and horizontal placement of the windings with same width and spacing. Such structures were built and tested. To make compatible inductor geometries with the Type 1 Flex Spiral structures, the Flex coil structures had l=500 mil and ƒ=100 mil, which is a number larger than the twice the minimum radius of curvature (32 mil) allowed. As an alternative, gold (Au) can be employed as the conductive material, which permits much thinner structures with a much smaller radius of curvature.
A Flex track width of 13 mil and 10 mil of extension from the track edges gives a Flex ribbon width of 546 mil. For 5-turn coils, 10 alternating folds of the periodic structure gives 6,130 mil of length, which is less than the Flex length of 9,500 mil as calculated in the Type 1 Flex spiral structure. The total thickness of a 5-turn coil is thus about 40 mil.
This fan folding technique can be used to generate any spiral geometry which has a point symmetry property in the center of the fold line noted as PSYM in
Comparing the manufacturability and performance of Type 1 and Type 2 Flex inductors the selection of a Type 1 Flex spiral is a better choice. The most important use of a Type 2 Flex structure was in the fair experimental comparison of very similar two different metal winding structures. The much better Q performance of a vertically placed high-aspect-ratio arrangement as in the HARMS process of constructing windings, compared to the stacked horizontal placements of windings, both having the same width, spacing and same aspect ratios giving the same inductance matrices, shows that the assumption made in the AC current density distribution is valid and gives much more uniform AC current distribution at high frequencies with significantly lower AC resistance. One naturally thinks that AC current density distribution and resulting AC resistance of a rectangular cross-sectional wire should be independent of its orientation in space. This assumption is entirely true for a free standing straight wire in space, but it is not true when it is formed as a spiral or a coil structure! It will be proper to say Maxwell's equations, Ampere's law and the Helmholtz wave equation is at work for this very practical and useful conclusion!
With the development of High Aspect Ratio Metallization (HARMS) interposer processes, there is a path for increasing the effective inductance of a spiral inductor, herein the “Tight Coupling Condition.” In a specific embodiment, four adjacent windings made according to the process couple more tightly, increasing the spiral inductance with the result of increasing the Q of the spiral inductance at all frequencies. This configuration corresponds to the Type 2 Flex structure and to the second of the aspect ratio parameters for metallization.
The interposer process is not only a thick metal process that is much thicker than is commercially available, it requires a high-aspect-ratio spacing rule as well. This is not the same as the known “thick metal process,” wherein the thickest metal evidently available today in IC processing is a mere 4μ thickness with 2.8μ width and 2.8μ spacing. Moreover, according to the calculations in support of the present invention, the width of the metal must be on the order of skin depth, but thicker than 50μ in most of the cases, to meet the desired DC resistance and electro-migration rules. If the metallization rules can deliver these metal width/thickness dimensions with only large spacings, more than the metal thickness, then a device will never be able to achieve the Tight Coupling Condition.
The invention has now been explained with reference to specific embodiments. Other embodiments will be evident to those of skill in the art. Therefore, it is not intended that this invention be limited to those specific embodiments. Rather the invention is to be defined by the appended claims.
This application is a Divisional of U.S. application Ser. No. 15/285,310, filed Oct. 4, 2016, the contents of which are incorporated herein by reference in their entirety for all purposes.
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| Number | Date | Country | |
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| 20230069135 A1 | Mar 2023 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15285310 | Oct 2016 | US |
| Child | 17978783 | US |
