Patent Application
20210082715
The present disclosure relates generally to solid-state devices, and more particularly, to multi-layer solid-state devices with offset electrodes and methods for forming the same.
Embodiments of the disclosed subject matter include multilayer solid-state devices and a method for fabricating such devices. The solid-state device includes a substrate with a stack of constituent thin-film layers that define an arrangement of electrodes and intervening layers. The constituent layers can conform to or follow a non-planar surface of the substrate, thereby providing a 3-D non-planar geometry to the stack. Among other substantial benefits, this non-planar surface of the substrate offers a higher surface area as compared to planar substrates, which translates into enhanced performance since there is more room for active functional structures.
Fabrication can employ a common shadow mask moved between lateral positions offset from each other to sequentially form at least some of the layers in the stack, whereby layers with a similar function (e.g., anode, cathode, etc.) can be electrically connected together at respective edge regions. Wiring layers can be coupled to the edge regions for making electrical connection to the respective subset of layers, thereby simplifying the fabrication process. By appropriate selection and deposition of the constituent layers, the multi-layer device can be configured as an energy storage device, such as a battery or capacitor, an electro-optic device, such as a light-emitting diode or solar cell, a sensing device, such as a piezoelectric sensor, or any other solid-state device.
In one or more embodiments, a method of forming a multi-layer solid-state device comprises (A1) depositing at least a portion of a first electrode over a first surface of a substrate using a first shadow mask in a first position with respect to the substrate. The method further comprises (E1) after (A1), displacing at least one of the substrate and the first shadow mask with respect to the other of the substrate and the first shadow mask, such that the first shadow mask is in a second position with respect to the substrate, and depositing a first intervening layer over the first electrode using the first shadow mask in the second position. The first position can be offset from the second position in at least one dimension in plan view.
The method further comprises (C1) after (E1), displacing at least one of the substrate and the first shadow mask with respect to the other of the substrate and the first shadow mask, such that the first shadow mask is in a third position with respect to the substrate, and depositing at least a portion of a second electrode over the first intervening layer using the first shadow mask in the third position. The second position can be offset from the third position in at least one dimension in plan view. The method further comprises (E2) after (C1), displacing at least one of the substrate and the first shadow mask with respect to the other of the substrate and the first shadow mask, such that the first shadow mask is in a fourth position with respect to the substrate, and depositing a second intervening layer over the second electrode using the first shadow mask in the fourth position. The fourth position can be aligned with the second position in plan view.
The method further comprises (A2) after (E2), displacing at least one of the substrate and the first shadow mask with respect to the other of the substrate and the first shadow mask, such that the first shadow mask is in a fifth position with respect to the substrate, and depositing at least a portion of a third electrode over the second intervening layer using the first shadow mask in the fifth position. The fifth position can be aligned with the first position in plan view. At least a portion of the first surface of the substrate is non-planar.
In one or more embodiments, a method comprises forming a first electrode over a substrate, forming a first layer over the first electrode and offset from the first electrode in at least one dimension in plan view, forming a second electrode over the first layer, forming a second layer over the second electrode and aligned with the first layer in plan view, and forming a third electrode over the second layer. The second electrode can be offset from the first layer and the first electrode in at least one dimension in plan view. The third electrode can be aligned with the first electrode in plan view. A surface of the substrate, over which the first electrode is formed, can be non-planar.
In one or more embodiments, a multi-layer solid-state device comprises a substrate, a first electrode, a first intervening layer, a second electrode, a second intervening layer, and a third electrode. The substrate can have a non-planar surface. The first electrode can be formed over the non-planar surface. The first intervening layer can be formed over the first electrode. The second electrode can be formed over the first intervening layer. The second intervening layer can be formed over the second electrode. The third electrode can be formed over the second intervening layer.
The first electrode can be aligned with the third electrode in plan view. The first intervening layer can be aligned with the second intervening layer in plan view. The first and third electrodes can be offset in at least one dimension from the first and second intervening layers in plan view. The second electrode can be offset in at least one dimension from the first and third electrodes and from the first and second intervening layers in plan view.
Objects and advantages of embodiments of the disclosed subject matter will become apparent from the following description when considered in conjunction with the accompanying drawings.
Embodiments will hereinafter be described with reference to the accompanying drawings, which have not necessarily been drawn to scale. Where applicable, some elements may be simplified, exaggerated, or otherwise not illustrated in order to assist in the illustration and description of underlying features. Throughout the figures, like reference numerals denote like elements.
In embodiments, a multi-layer solid-state device 100 includes a substrate 102 with a stack 120 of thin-film layers 104-108 formed on an upper surface 102t of the substrate 102, as illustrated in
Another intervening layer 108b is formed on and shifted laterally with respect to the second electrode 106a. The intervening layer 108b is substantially aligned with the underlying intervening layer 108a. An upper surface of the second electrode 106a is thus exposed from intervening layer 108b at a second edge region 114, while a portion of the intervening layer 108b on an opposite side from second edge region 114 extends past the second electrode 106a to contact an upper surface of the underlying intervening layer 108a. The intervening layer 108b terminates before first edge region 112, such that the upper surface of the first electrode 104a remains exposed within the first edge region 112.
A third electrode 104b (Type I) is formed on and shifted laterally with respect to the intervening layer 108b. The third electrode 104b is of the same type as the first electrode 104a and is shifted toward the first edge region 112 so as to be substantially aligned with the underlying first electrode 104a. A portion of the third electrode 104b extends past the intervening layer 108b to contact an upper surface of the underlying first electrode 104a in the first edge region 112. The first electrode 104a and third electrode 104b are thus electrically connected together by virtue of the offset layer arrangement.
Another intervening layer 108c is formed on and shifted laterally with respect to the third electrode 104b. The intervening layer 108c is substantially aligned with the underlying intervening layer 108b. An upper surface of the third electrode 104b is thus exposed from the intervening layer 108c at the first edge region 112, while a portion of the intervening layer 108c on an opposite side from the first edge region 112 extends past the third electrode 104b to contact an upper surface of intervening layer 108b.
A fourth electrode 106b (Type II) is formed on and shifted laterally with respect to intervening layer 108c. The fourth electrode 106b is of the same type as the second electrode 106a and is shifted toward the second edge region 114 so as to be substantially aligned with the underlying second electrode 106a. The upper surface of the third electrode 104b thus remains exposed within the first edge region 112, while a portion of the fourth electrode 106b extends past the intervening layer 108c to contact an upper surface of the underlying second electrode 106a in the second edge region 114. The second electrode 106a and fourth electrode 106b are thus electrically connected together by virtue of the offset layer arrangement.
Another intervening layer 108d is formed on and shifted laterally with respect to the fourth electrode 106b. The intervening layer 108d is substantially aligned with the underlying intervening layer 108c. An upper surface of the fourth electrode 106b is thus exposed from intervening layer 108d at the second edge region 114, while a portion of the intervening layer 108d on an opposite side from second edge region 114 extends past the fourth electrode 106b to contact an upper surface of the underlying intervening layer 108c. The intervening layer 108d terminates before first edge region 112, such that the upper surface of the third electrode 104b remains exposed within the first edge region 112.
A fifth electrode 104c (Type I) is formed on and shifted laterally with respect to the intervening layer 108d. The fifth electrode 104c is of the same type as the first and third electrodes 104a, 104b and is shifted toward the first edge region 112 so as to be substantially aligned with the underlying first electrode 104a. A portion of the fifth electrode 104c extends past the intervening layer 108d to contact an upper surface of the underlying third electrode 104b in the first edge region 112. The first electrode 104a, third electrode 104b, and fifth electrode 104c are thus electrically connected together by virtue of the offset layer arrangement.
The combination of first electrode 104a, intervening layer 108a, and second electrode 106a forms a first of many sub-devices in the stack 120 that are connected together in parallel. A second sub-device is comprised of the third electrode 104b, intervening layer 108b, and the second electrode 106a, with the second electrode 106a being shared by the first and second sub-devices. In each sub-device, the overlapping area 110 in plan view between the Type I and Type II electrodes can define an active area of the respective sub-device. The active area 110 is disposed between the first edge region 112 and second edge region 114, and is separated from each edge region 112, 114 by portions of the intervening layers 108a-108d.
Additional layers forming additional sub-devices can be added to the stack in a similar manner ad infinitum (or at least until a desired or practical number of sub-devices in the stack 120 has been achieved). For example, a third sub-device can be formed by fourth electrode 106b, intervening layer 108c, and third electrode 104c (with the third electrode 104c being shared by the second and third sub-devices) and has a similar configuration as the first sub-device. A fourth sub-device can be formed by fifth electrode 104c, intervening layer 108d, and fourth electrode 106b (with the fourth electrode 106b being shared by the third and fourth sub-devices) and has a similar configuration as the second sub-device.
Although four sub-devices are described in
As
In some embodiments, the constituent layers of the stack 120 all have substantially the same shape (i.e., geometry and dimensions) in plan view. Such a configuration may facilitate the use of a common shadow mask for each of the constituent layers. For example, the Type I electrodes 104a-104c, intervening layers 108a-108d, and Type II electrodes 106a-106b all have the same rectangular shape in plan view. In some embodiments, the layers can be offset from each other in one dimension, for example, as shown in the plan view of
Although
Although illustrated as flat in
For example,
Various shapes for the projections 202 and/or recesses 208 are possible. For example, the projections 202 can have dimensions in plan view that are roughly the same so as to form a pillar (e.g., as with feature 210 of
The projections 202 and/or recesses 208 of the substrate 102 thus define a three-dimensional profile for surface 102t, with some portions of the surface 102t being at different levels. Each of the layers 104a-108d (although, for clarity purposes, only a portion of the layer stack 120 of
In some embodiments, the layers formed over portions of surface 102t at one level may exhibit different properties as compared to those layers formed over portions of surface 102t at another level. For example, when a physical vapor deposition method is used to form layers 104a-108d, respective thicknesses of layers at higher levels (e.g., between adjacent recesses 208 or at the top of projections 202) may be greater than respective thicknesses of layers at lower levels (e.g., at the bottom of recesses 208 or between adjacent projections 202). When the layers are constructed to form a battery, these differences in layer thicknesses may yield higher power characteristics for the lower level layers and higher energy density characteristics for the higher level layers. Alternatively, when a conformal deposition method (e.g., chemical vapor deposition) is used to form layers 104a-108d, variations in the respective thicknesses of layers may be avoided.
In some embodiments, the substrate can have a curved upper surface in addition to, or in place of, projections and/or recesses. For example,
A material and structure of the substrate 102 can be selected based on a particular application for multi-layer solid-state device 100. For example, the substrate 102 may be formed of a substantially insulating material, such as semiconductor or dielectric material, to avoid electrically connecting layers 104a and 106a through the substrate 102. The substrate 102 can be rigid or flexible. In some embodiments, the substrate 102 can have a back surface 102b that follows the profile of the upper surface 102t. For example, the substrate 102 may be a molded scaffold, such as a convoluted aluminum foil. In some embodiments, the substrate 102 may be formed of a material that acts as one of the electrodes 104 or 106 of the stack 120, in which case the layer arrangement of the stack 120 is modified to account for the additional electrode. For example, the substrate 102 may be formed of a solid or thin-film cathode patterned to form a three-dimensional topography. Alternatively or additionally, the substrate 102 and/or a surface geometry thereof may be formed by one or more of anodization of aluminum, silicon, or other materials to form nanopores, patterning by dry anisotropic etching, nanowire growth, and folding of thin foils.
Similarly, the materials and structure of the electrode and intervening layers can be selected based on a particular application for multi-layer solid-state device 100. For example,
In the battery configuration of
Each set of anode current collector 303, anodic electrode layer 304, solid electrolyte 308, cathodic electrode layer 306, and cathode current collector 305 that are adjacent to each other in the stack form a single thin-film battery of the device 300, with the overlapping area 310 in plan view of the anodic electrode layer 304 and cathodic electrode layer 306 defining an active area of each battery. For example,
Adjacent batteries in the stack can share a current collector, such that the respective electrode is constituted by a pair of anodic or cathodic electrode layers sandwiching the current collector layer. Electrodes at an end of the stack 120, e.g., the lowermost electrode adjacent the substrate 102 or an uppermost electrode of the stack may omit one of the pair of anodic or cathodic electrode layers, for example, such that the respective current collector is adjacent to the substrate 102 or is exposed at the top of the stack 120. In
The anodic electrode layers 304, the cathodic electrode layers 306, and solid electrolyte layers 308 all have a similar shape in plan view, as defined by a common shadow mask pattern used to form the offset layers. In some embodiments, the anode current collector 303 can have the same shape as and be aligned with the anodic electrode layers 304, and/or the cathode current collector 305 can have the same shape as and be aligned with the cathodic electrode layers 306. Thus, the same shadow mask pattern (e.g., of the same shadow mask or identical patterns on different shadow masks) can be used to form each of the layers 303-308 of the multi-battery stack 120 by simply shifting the shadow mask pattern laterally (and vertically to accommodate increasing layer thicknesses) and changing source material for deposition. In other embodiments, the anode current collector 303 and/or the cathode current collector 305 can have a different pattern or shape from their corresponding electrode layers 304, 306, in which case, a second shadow mask pattern (e.g., on the same shadow mask or a different pattern on different shadow masks) can be used to form the current collectors 303 and/or 305.
The offset arrangement of layers allows for direct contact between the anodic electrode layers 304 and anode current collectors 303 of adjacent batteries within the stack 120 at anode contact region 312 (similar to first edge region 112). The offset arrangement also allows for direct contact between the cathodic electrode layers 306 and cathode current collectors 306 of adjacent batteries within the stack at cathode contact region 314 (similar to second edge region 114). As a result, the batteries within the stack are connected together in parallel in situ. Electrical contact between the electrodes structures is good, involving only the thickness of the thin layers of electrode materials between accompanying current collector layers, which provides for fast electron transport to the active battery region 310, thereby enabling high power.
Moreover, the offset arrangement of layers exposes the uppermost electrodes—the anode current collector 303 and the cathodic electrode layer 306—while simultaneously being in contact with the underlying layers. Electrical contact can thus be made to the exposed electrodes for wiring to connect the multi-battery stack to other devices. For example, an anode wiring layer 322 can be formed over the uppermost electrode (i.e., anode current collector 303) in the anode contact region 312 while a cathode wiring layer 324 can be formed over the uppermost electrode (i.e., cathodic electrode layer 306) in the cathode contact region 314, as illustrated in
The contact area between the wiring layer and the underlying electrode layers may be substantially larger (e.g., at least two orders of magnitude) than the respective thickness of each electrode layer. For example, while anodic electrode layers 304, cathodic electrode layers 306, anode current collector layers 303, and cathode current collector layers 305 each have a thickness on the order of tens of nanometers (e.g., 30-80 nm), each wiring layer 322, 324 extends over a much greater dimension (e.g., ˜1 mm in plan view) in the respective contact region 312, 314.
In some embodiments, the anode wiring layer 322 and/or the cathode wiring layer 324 can be formed using another shadow mask (e.g., different from the one used to form the different battery layers 303-308) to deposit electrically-conductive material (e.g., copper) on the respective contact regions 312, 314. In some embodiments, deposition of the anode and cathode wiring layers may employ the same shadow mask and occur simultaneously. Alternatively, deposition of the anode and cathode wiring layers may employ the same shadow mask but occur at different times, for example, by depositing the anode wiring layer and then moving the shadow mask to deposit the cathode wiring layer. In still another alternative, deposition of the anode and cathode wiring layers may employ different shadow masks and occur at different times.
In some embodiments, the wiring layers can be formed after additional processing at the respective contact regions 312, 314, for example, to improve electrical contact or to allow electrical connection to underlying structures by the same wiring layer formation. For example, the anodes 304 and anode current collectors 303 within anode contact region 312 can be processed to expose respective edges thereof, and anode wiring layer 326 can be deposited over and in electrical contact with the exposed edges, as illustrated in
Although
The uppermost and lowermost electrode layers in the stack can be offset from the intermediate layers for making electrical connections at respective edge contact regions. For example, anode current collector 303b and anodic electrode layer 304b, which constitute the lowermost layer, are offset so as to be exposed from the intermediate layers of the stack, thereby allowing anode wiring layer 352 to directly connect thereto. Similarly, cathode current collector 305u and cathodic electrode layer 306u, which constitute the uppermost layer, are offset from the intermediate layers of the stack, thereby allowing cathode wiring layer 354 to directly connect thereto along an edge region opposite to the anode wiring layer 352.
In some embodiments, it may be unnecessary to offset the uppermost electrode layer from the intermediate layers, in which case, the wiring layer connecting to the uppermost electrode layer (e.g., cathode current collector 305u in
As referenced above, the arrangement of multi-battery 350 can be combined with the arrangement of multi-battery 300, such that some of the batteries within a stack 120 on substrate 102 are connected in parallel while others are connected in series. For example, the lowermost current collector 303b of multi-battery 350 may constitute the uppermost current collector 303 of multi-battery 300, with the intervening layers of
Although
As referenced above, the multi-battery can be wired to other devices or structures of the substrate via appropriate wiring layers. For example, as illustrated in
Alternatively or additionally, electrical connection from the battery to the electronic device can be made through a terminal and circuit trace under the passivation film. For example, as illustrated in
Configurations for wiring between multi-battery 300 and electronic device 404 through passivation film 406 are not limited to those illustrated in
Although only a single multi-battery 300 and a single electronic device 404 are illustrated in
For multi-batteries of relatively smaller planar size, a consideration in the device arrangement is the size/area required to make the anode and cathode contacts (e.g., wiring layers 322, 324 in
Other electronic devices can also be integrated with the multi-batteries on a common substrate. For example, as noted above, the selection of materials for the constituent layers of the stack over the substrate can determine operation of the multi-layer solid-state device. As such, another shadow mask can be used to form another multi-layer device on the substrate in a manner similar to the multi-batteries of
Referring to
The fabrication process 800 can begin at 802, where a non-planar substrate 102 is provided. For example, 802 can include forming the substrate 102 to have a non-planar surface 102t over which the various layers of multi-layer solid-state device will be formed. The forming the non-planar surface can include etching or machining to form one or more projection or recesses, as described above. Alternatively or additionally, specialized processes for creating non-planar surface structures can be employed, such as but not limited to, self-assembled nanopore synthesis by electrochemical anodization and use of colloidal templates. Alternatively or additionally, the forming can include manipulating (e.g., bending, casting, molding, or pressing) the substrate to have a desired shape for the non-planar surface, for example, by shaping a metal foil (e.g., forming a convoluted aluminum foil).
The fabrication process 800 can proceed to 804, where shadow mask 502 is moved to a first lateral position relative to the substrate 102 for forming a Type I electrode, as shown in
For example, when the Type I electrodes are anodes of a battery (e.g., battery 300 illustrated in
Returning to
The fabrication process 800 can then proceed to 812, where shadow mask 502 is moved from the second lateral position of
For example, when the Type II electrodes are cathodes of a battery (e.g., battery 300 illustrated in
When the Type I electrodes are cathodes and the Type II electrodes are anodes,
The fabrication process 800 can proceed to 816, where shadow mask 502 is moved from the third lateral position of FIG. SI back to the second lateral position relative to the substrate 102 for forming another intervening layer, as illustrated in
The fabrication process 800 can proceed to 824, where it is determined if additional sub-devices, and thus additional electrode and intervening layers, are desired. If additional layers are desired, the process 800 can repeat steps 808-822 to form the additional devices, for example, third electrode 106b, fourth electrode 104c, and intervening layers 108c-108d of
During deposition, the shadow mask 502 is disposed in close proximity to or touching the substrate 102. However, when being moved between positions, the shadow mask 502 and the substrate 102 may be spaced from each other to avoid damaging already deposited layers. The above description focuses on moving the shadow mask 502. However, in an alternative, it is also possible for the shadow mask 502 to be held stationary and the substrate 102 instead to be moved to provide the relative displacement between first through third positions. In still another alternative, both the shadow mask 502 and the substrate 102 may move to effect displacement between the first through third positions.
Although steps 802-828 of process 800 have been illustrated separate from each other and in a specific order, embodiments of the disclosed subject matter are not limited to that particular arrangement. Indeed, in practical embodiments, certain steps may be combined or rearranged. For example, the electrical connection of 828 may occur before or contemporaneously with the electrical connection of 826. Alternatively or additionally, the first deposited electrode may be a Type II electrode rather than a Type I electrode. Moreover, additional non-illustrated process steps may be included between or after the illustrated process steps. For example, in between or after parallel configured layers, layers may be deposited without moving the shadow mask so as to form a serial configuration (e.g., as in
In some embodiments, the process steps of
The first shadow mask can include apertures in battery formation regions only, such that no material is deposited in the capacitor formation regions during deposition using the first shadow mask. Similarly, the third shadow mask can include apertures in capacitor formation regions only, such that no material is deposited in the battery formation regions during deposition using the third shadow mask. Alternatively, the first and third shadow masks can be combined together, and a mechanism (e.g., moving shutter or moving fourth mask) can be provided for blocking off apertures in the capacitor formation region during deposition of materials for the battery, and vice-versa.
In some embodiments, even though the current collector layer and the capacitor electrode employ the second shadow mask, the aperture patterns therein may be the same (or substantially the same) as the respective patterns of the first and third shadow masks. In other words, the aperture pattern of the first shadow mask that defines the electrode and electrolyte layers of the battery may be the same in plan view as the aperture pattern of the second shadow mask that defines the current collector layer. Similarly, the aperture pattern of the third shadow mask that defines the dielectric of the capacitor may be the same in plan view as the aperture pattern of the second shadow mask that defines the capacitor electrodes. Thus, the above description with respect to offsetting of the common shadow mask can also apply to the offset of similarly-shaped aperture patterns to form the different constituent layers of a multi-layer solid-state device, even if those aperture patterns are on different shadow masks.
In some embodiments, the process steps of
Alternatively or additionally, the first and second multi-layer batteries can be built at a same using a common shadow mask, where a mechanism (e.g., moving shutter or moving mask) blocks apertures for the first battery once a desired thickness is reached but allows deposition to continue for the second battery. In another example, the first and second multi-layer batteries can have similar layer thicknesses but a different pattern in plan view (e.g., the first having the pattern of
Other combinations of devices and/or process variations beyond those specifically discussed above are also possible by appropriate control of deposition materials and mask patterns. Indeed, although the examples above discuss batteries and/or capacitors, the teachings of those examples are equally applicable to the other multi-layer solid-state devices, such as but not limited to, sensors, electro-optic devices, and energy storage devices. Moreover, although the examples above focus on combining two devices, the teachings of those examples are equally applicable to combining more than two devices, such as, but not limited to, forming batteries, capacitors, and solar cells on a common substrate.
In some embodiments, at least process steps 804-824 occur while maintaining vacuum conditions (e.g., under a continuous vacuum). For example, the substrate 102 may be arranged in an evacuated volume 602 of a vacuum-based deposition chamber 600, as illustrated in
The substrate 102 can be held by a support 604, which may be capable of displacing in two-dimensions (preferably in three-dimensions) and/or of heating the substrate 102 during or after deposition. Depositions of individual materials occur with shadow mask 502 in place in front of the substrate 102, either in close proximity or touching the substrate. The shadow mask 502 can be supported by a stage 606 that can move laterally in two dimensions with respect to the substrate 102. Preferably, the stage 606 can also move in a third direction to adjust spacing between the shadow mask 502 and the substrate 102. In some embodiments, only one of the support 604 and the mask stage 606 is capable of motion. In other embodiments, both of the support 604 and the mask stage 606 are capable of motion in at least one dimension. The relative movement between the substrate 102 and the shadow mask 502 allows for the deposition of different materials in different places on the substrate 102, where such materials correspond to Type I electrodes, intervening layers, or Type II electrodes.
In some embodiments, the formation of the wiring layers in process steps 826-828 may also occur in the same deposition chamber 600 while maintaining vacuum conditions by using a second shadow mask. In some embodiments, the second shadow mask may be used to form a constituent layer of the Type I or Type II electrodes, for example, when the current collector has a different pattern than the associated anodic or cathodic electrode layers, or when a layer for a separate device is to be deposited on the substrate at a same time as the current collector. In such embodiments, the mask stage 606 may be configured to switch from the first shadow mask 502 to a second shadow mask 608. Alternatively or additionally, the mask stage 606 may have an array of different shadow masks and can select a particular shadow mask for a particular layer, for example, a first wiring shadow mask to electrically connect to the Type I electrodes and a second wiring shadow mask to electrically connect to the Type II electrodes. Alternatively or additionally, the vacuum chamber 600 can include an airlock that allows for introduction of a new shadow mask to the mask stage 606 while maintaining vacuum conditions.
In another example illustrated in
In some embodiments, the deposition of one or more of process steps 804-822 is a physical vapor deposition or physical liquid deposition technique. For example, when the features of the non-planar surface have an aspect ratio of at least 0.5:1 (e.g., less than 5:1, or less than 3:1), physical deposition techniques can be employed. Physical vapor deposition techniques can include at least one of sputtering, evaporation, pulsed laser deposition, and molecular-beam epitaxy. Physical liquid deposition techniques include at least one of sol-gel coating, polymer solution coating, aerosol deposition, and inkjet printing.
As referenced above, physical deposition of layer 704 occurs with shadow mask 502 in place in front of the substrate 102, with a bottom surface 502b of the mask either in close proximity to or touching the upper surface 102t of substrate 102, as illustrated in
In some embodiments, the deposition of one or more of process steps 804-822 is a chemical deposition technique. For example, when the features of the non-planar surface have an aspect ratio greater than 3:1, chemical deposition techniques can be employed as they provide a greater of conformal coating than physical deposition techniques. Chemical deposition techniques can include at least one of electrochemical (e.g., electroplating) or chemical solution deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), and molecular layer deposition, as well as plasma enhanced versions thereof. Electrodeposition can use an electric field to form a layer of metals, oxides, or conductive polymers, while chemical solution deposition can use a chemical reaction without an electric field to form layers. For example, the chemical solution deposition can involve a chemical reduction or oxidation of metals or polymerization.
In some embodiments, different techniques can be applied to different layers, for example, by using chemical deposition for solid electrolyte layers and physical deposition for current collector layers. In some embodiments, the various deposition techniques can be combined to form one or more layers. For example, a metal layer may be deposited by electrodeposition followed by thermal oxidation to yield a metal oxide. In another example, a metal layer may be deposited by electrodeposition followed by treatment with H2S gas to yield a metal sulfide. In still another example, a metal layer may be deposited by electrodeposition on a current collector previously formed by physical or chemical deposition in order to improve electrical contact characteristics. Other variations and combinations of deposition techniques are also possible according to one or more contemplated embodiments.
As referenced above, chemical deposition of layer 704 also occurs with shadow mask 502 in place in front of substrate 102, with a bottom surface 502b of the mask either in close proximity to or touching the upper surface 102t of substrate 102, as illustrated in
Alternatively or additionally, an inert gas flow can be provided to the shadow mask to sweep away any encroachment under the shadow mask during chemical deposition. For example,
In some embodiments, the shadow mask can be disposed sufficiently close to the substrate during deposition such that at least a portion of the substrate is within an aperture of the shadow mask, i.e., a portion of the substrate is at a level between a bottom surface of the shadow mask and a top surface of the shadow mask in cross-sectional view. For example, when the substrate 102 includes protrusions 202 as illustrated in
In other embodiments, the shadow mask is disposed sufficiently close to an uppermost surface of the substrate during deposition, but without any portion of the substrate being within the aperture of the shadow mask. For example, the shadow mask may be flexible so as to conform to the curved surface 102t of the substrate. In such a configuration, the curved portion may be considered to lie below the curved bottom surface of the shadow mask and thus outside the shadow mask aperture. In another example, when the substrate 102 includes recesses 208 as illustrated in
Numerous variations in the fabrication processes described above are also possible according to one or more contemplated embodiments. For example, different deposition process types can be employed in the sequence of layers, e.g., using sputter deposition of the electrodes (or constituent layers thereof) while using CVD or ALD for the intervening layer (e.g., electrolyte). Alternatively or additionally, the shadow mask can be removed or omitted when depositing the intervening layer (e.g., electrolyte). When employing high conformality processes like CVD and ALD for the deposition, the intervening layer can be deposited over the entire substrate surface. In such a configuration, the wiring approach of
Although particular components and wiring configuration have been illustrated in the figures and discussed in detail herein, embodiments of the disclosed subject matter are not limited thereto. Indeed, one of ordinary skill in the art will readily appreciate that different components or wiring configurations can be selected and/or components added to provide the same effect. In practical implementations, embodiments may include additional components or other variations beyond those illustrated, for example, additional wiring layers to connect different components on the same substrate. Accordingly, embodiments of the disclosed subject matter are not limited to the particular configurations specifically illustrated and described herein.
In one or more first embodiments, a method of forming a multi-layer solid-state device, the method comprises depositing at least a portion of a first electrode over a first surface of a substrate using a first shadow mask in a first position with respect to the substrate. In the method, after the depositing, at least one of the substrate and the first shadow mask is displaced with respect to the other of the substrate and the first shadow mask, such that the first shadow mask is in a second position with respect to the substrate. The method also comprises depositing a first intervening layer over the first electrode using the first shadow mask in the second position, where the first position is offset from the second position in at least one dimension in plan view.
In the method, after the depositing, at least one of the substrate and the first shadow mask is displaced with respect to the other of the substrate and the first shadow mask, such that the first shadow mask is in a third position with respect to the substrate. The method also comprises depositing at least a portion of a second electrode over the first intervening layer using the first shadow mask in the third position, where the second position is offset from the third position in at least one dimension in plan view.
In the method, after the depositing, at least one of the substrate and the first shadow mask is displaced with respect to the other of the substrate and the first shadow mask, such that the first shadow mask is in a fourth position with respect to the substrate. The method also comprises depositing a second intervening layer over the second electrode using the first shadow mask in the fourth position, where the fourth position is aligned with the second position in plan view.
In the method, after the depositing, at least one of the substrate and the first shadow mask is displaced with respect to the other of the substrate and the first shadow mask, such that the first shadow mask is in a fifth position with respect to the substrate. The method also comprises depositing at least a portion of a third electrode over the second intervening layer using the first shadow mask in the fifth position, where the fifth position is aligned with the first position in plan view.
In the first embodiments or any other embodiment, at least a portion of the first surface is non-planar. The deposited layers forming the first through third electrodes and the first and second intervening layers can conform to or follow the non-planar first surface so as to have a three-dimensional non-planar geometry. Available deposition surface area of the non-planar first surface can be greater than an area of the deposition area of the first shadow mask in plan view.
In the first embodiments or any other embodiment, parts of the first and third electrodes are in direct contact with each other in a first edge region, and each intervening layer is spaced from the first edge region in plan view.
In the first embodiments or any other embodiment, the method further comprises displacing at least one of the substrate and the first shadow mask with respect to the other of the substrate and the first shadow mask, such that the first shadow mask is in a sixth position with respect to the substrate, and depositing a third intervening layer over the third electrode using the first shadow mask in the sixth position, the sixth position being aligned with the second position in plan view. In the method, after the depositing, at least one of the substrate and the first shadow mask is displaced with respect to the other of the substrate and the first shadow mask, such that the first shadow mask is in a seventh position with respect to the substrate. The method also includes depositing at least a portion of a fourth electrode over the third intervening layer using the first shadow mask in the seventh position, where the seventh position is aligned with the third position in plan view.
In the first embodiments or any other embodiment, parts of the second and fourth electrodes are in direct contact with each other in a second edge region, the first edge region does not overlap with the second edge region in plan view, and each intervening layer is between the first edge region and the second edge region in plan view.
In the first embodiments or any other embodiment, the method further comprises forming a first wiring layer on an uppermost electrode in the first edge region so as to electrically connect to the first and third electrodes, and forming a second wiring layer on an uppermost electrode in the second edge region so as to electrically connect to the second and fourth electrodes. In the first embodiments or any other embodiment, at least one of the first and second wiring layers is formed by depositing using a second shadow mask different from the first shadow mask. In the first embodiments or any other embodiment, at least one of the first and second wiring layers is formed by one or more of photolithography, vacuum deposition, metal spraying through a mask, and 3D printing.
In the first embodiments or any other embodiment, the method further comprises removing material in the first and second edge regions, respectively, forming a first wiring layer in the first edge region so as to electrically connect to the first and third electrodes, and forming a second wiring layer in the second edge region so as to electrically connect to the second and fourth electrodes. In the first embodiments or any other embodiment, the removing material comprises one or more of reactive ion etching, plasma etching, ion milling, wet etching, laser etching, and grinding.
In the first embodiments or any other embodiment, the multi-layer solid-state device comprises a battery, each of the first and third electrodes comprises one of an anode and a cathode, the second electrode comprises the other of an anode and a cathode, and each intervening layer comprises a solid electrolyte. In the first embodiments or any other embodiment, each of the first through third electrodes comprises a respective current collector layer for electron transport.
In the first embodiments or any other embodiment, the first electrode includes at least a first current collector layer and a first electrode layer, and the depositing the first electrode includes depositing the first current collector layer over the first surface of the substrate, and depositing the first electrode layer over the first current collector layer.
In the first embodiments or any other embodiment, the second electrode includes at least second and third electrode layers and a second current collector layer, and the depositing the second electrode includes depositing the second electrode layer over the first intervening layer, depositing the second current collector layer over the second electrode layer, and depositing the third electrode layer over the second current collector layer.
In the first embodiments or any other embodiment, the third electrode includes at least a fourth electrode layer and a third current collector layer, and the depositing the third electrode includes depositing the fourth electrode layer over the second intervening layer, and depositing the third current collector layer over the fourth electrode layer.
In the first embodiments or any other embodiment, the depositing of the first electrode layer and the first current collector layer can use the first shadow mask in the first position. In the first embodiments or any other embodiment, the depositing of the second electrode layer, the second current collector layer, and the third electrode layer can use the first shadow mask in the third position. In the first embodiments or any other embodiment, the depositing of the fourth electrode layer and the third current collector layer can use the first shadow mask in the fifth position.
In the first embodiments or any other embodiment, the third electrode includes at least fourth and fifth electrode layers and a third current collector layer, and the depositing the third electrode includes depositing the fourth electrode layer over the second intervening layer, and depositing the third current collector layer over the fourth electrode layer, and depositing the fifth electrode layer over the third current collector layer.
In the first embodiments or any other embodiment, the depositing of the fourth electrode layer, the third current collector layer, and the fifth electrode layer use the first shadow mask in the fifth position.
In the first embodiments or any other embodiment, the depositing of first current collector layer uses a second shadow mask, the depositing of the first electrode layer uses the first shadow mask in the first position, and the first shadow mask has a different pattern than the second shadow mask.
In the first embodiments or any other embodiment, the depositing of the second current collector layer uses a third shadow mask, the depositing of the second electrode layer and the third electrode layer use the first shadow mask in the third position, and the first shadow mask has a different pattern than the third shadow mask.
In the first embodiments or any other embodiment, the depositing of the third current collector layer uses a fourth shadow mask, the depositing of the fourth electrode layer uses the first shadow mask in the fifth position, and the first shadow mask has a different pattern than the fourth shadow mask.
In the first embodiments or any other embodiment, an overlapping area between the first through third electrodes in plan or cross-sectional view defines an active area of the multi-layer battery.
In the first embodiments or any other embodiment, each of the first through third electrodes comprises an upper electrode layer, a current collector layer for electron transport, and a lower electrode layer, and the current collector layer is disposed between the upper and lower electrode layers in cross-sectional view.
In the first embodiments or any other embodiment, the second position is offset from the first position in at least two orthogonal dimensions in plan view, and/or the third position is offset from the second position in at least two orthogonal dimensions in plan view.
In the first embodiments or any other embodiment, said portion of the first surface has a non-zero curvature in cross-sectional view.
In the first embodiments or any other embodiment, the first shadow mask is flexible, and a shape of the first shadow mask in cross-sectional view during the depositing of at least one of the first through third electrodes and first through second intervening layers follows the curvature of the portion of the first surface.
In the first embodiments or any other embodiment, the first shadow mask has a top surface, a bottom surface, and an aperture extending between the top and bottom surfaces, respective materials are deposited over the substrate through said aperture, and at least a portion of the substrate within said aperture is between the top and bottom surfaces of the first shadow mask in cross-sectional view during the depositing of at least the first electrode.
In the first embodiments or any other embodiment, the substrate includes at least one projection or recess that has side, bottom, or top surface portions defining said first surface, and each of the electrodes and intervening layers is formed over the at least one projection or recess.
In the first embodiments or any other embodiment, the projection or recess has an aspect ratio of height to width of at least 0.5:1, and the depositing of at least one of first through third electrodes and first through second intervening layers comprises a physical vapor deposition or physical liquid deposition technique. In the first embodiments or any other embodiment, the physical vapor deposition technique comprises at least one of sputtering, evaporation, pulsed laser deposition, and molecular-beam epitaxy, and the physical liquid deposition technique comprises at least one of sol-gel deposition, aerosol deposition, and inkjet printing.
In the first embodiments or any other embodiment, the projection or recess has an aspect ratio of height to width of at least 0.5:1, and the depositing of at least one of first through third electrodes and first through third intervening layers comprises a chemical deposition technique. In the first embodiments or any other embodiment, the chemical deposition technique comprises at least one of chemical vapor deposition (CVD), atomic layer deposition (ALD), and molecular layer deposition.
In the first embodiments or any other embodiment, the first surface includes portions at different levels in cross-sectional view, and a thickness of at least one of the electrodes and intervening layers deposited over one portion of the first surface is different from a thickness of said at least one of the electrodes and intervening layers deposited over another portion of the first surface.
In the first embodiments or any other embodiment, during the depositing of at least one of first through third electrodes and first through second intervening layers, a first portion of the first surface is closer to the first shadow mask than a second portion of the first surface, and the thickness of at least one of the electrodes and intervening layers deposited over the first portion is greater than the thickness of the corresponding electrode or intervening layer deposited over the second portion.
In the first embodiments or any other embodiment, the projection or recess has an aspect ratio of height to width of at least 3:1. In the first embodiments or any other embodiment, the projection or recess is formed by anodization of a substrate material to form nanopores therein, patterned dry anisotropic etching of the substrate, nanowire growth, or folding of thin films.
In the first embodiments or any other embodiment, the first surface includes portions at different levels in cross-sectional view, and a thickness of at least one of the electrodes and intervening layers deposited over one portion of said first surface is substantially the same as a thickness of said at least one of the electrodes and intervening layers deposited over another portion of said first surface.
In the first embodiments or any other embodiment, the method comprises, prior to depositing the first electrode, subjecting the substrate to vacuum, wherein the depositing the first through third electrodes and the first through second intervening layers (and the corresponding displacement of the first shadow mask) are performed while maintaining vacuum conditions.
In the first embodiments or any other embodiment, the depositing the first through third electrodes and the first through second intervening layers (and the corresponding displacement of the first shadow mask) are performed in a single vacuum-based deposition chamber.
In the first embodiments or any other embodiment, during the depositing of at least one of the first through third electrodes and the first through second intervening layers, a portion of the substrate is in contact with the first shadow mask.
In the first embodiments or any other embodiment, the first shadow mask comprises a sealing member surrounding an aperture of the first shadow mask, and the substrate contacts the sealing member during the depositing of at least one of the first through third electrodes and the first through second intervening layers.
In the first embodiments or any other embodiment, during the depositing of at least one of the first through third electrodes and the first through second intervening layers, each part of the first shadow mask is spaced from the substrate. In the first embodiments or any other embodiment, the method comprises, during the depositing of the at least one of the first through third electrodes and the first through second intervening layers, flowing an inert gas along a surface of the first shadow mask.
In the first embodiments or any other embodiment, the method comprises after depositing the third electrode, depositing a third intervening layer over the substrate using the first shadow mask in a sixth position aligned with the fifth position in plan view, and after depositing the third intervening layer, depositing at least a portion of a fourth electrode over the third intervening layer using the first shadow mask in a seventh position aligned with the sixth position in plan view. In the first embodiments or any other embodiment, the second through fourth electrodes may not be in direct contact with each other.
In the first embodiments or any other embodiment, the multi-layer solid-state device comprises a capacitor, each of the first through third electrodes comprises an electrically conductive layer, and each intervening layer comprises a dielectric. In the first embodiments or any other embodiment, the multi-layer solid-state device comprises a solar cell, each of the first through third electrodes comprises an electrically conductive layer, and each intervening layer comprises semiconductor active layers forming a p-n junction. In the first embodiments or any other embodiment, the multi-layer solid-state device comprises a sensor, each of the first through third electrodes comprises an electrically-conductive layer, and each intervening layer comprises a piezo-electric material. In the first embodiments or any other embodiment, the multi-layer solid-state device comprises a light-emitting diode, each of the first through third electrodes comprises an optically-transparent, electrically-conductive layer, and each intervening layer comprises semiconductor active layers forming a p-n junction.
In the first embodiments or any other embodiment, the first shadow mask includes multiple apertures spaced apart from each other, and the depositing of the first through third electrodes and first through second intervening layers forms respective portions of multiple separate multi-layer solid-state batteries on the substrate at a same time using the multiple apertures of the first shadow mask.
In the first embodiments or any other embodiment, the method comprises forming a multi-layer solid-state capacitor on the substrate with a multi-layer solid-state battery.
In the first embodiments or any other embodiment, the substrate comprises an electronic device and a passivation film formed over at least part of the electronic device, the first surface comprises a surface of the passivation film, and the passivation film is between the first electrode and the electronic device along a thickness direction of the solid-state device. In the first embodiments or any other embodiment, the electronic device is a complementary metal-oxide-semiconductor (CMOS) device. In the first embodiments or any other embodiment, the method includes electrically connecting at least one of the first through third electrodes with the electronic device. In the first embodiments or any other embodiment, the electrically connecting comprises forming a via extending through the passivation film and forming a wiring layer in said via, and at least a portion of said wiring layer connects to a portion of at least one of the electrodes.
In the first embodiments or any other embodiment, the method comprises forming a first wiring layer in first and second portions of the first edge region. The first portion of the first edge region extends in a first direction in plan view, the second portion of the first edge region extends in a second direction crossing the first direction in plan view, the first portion of the first edge region is adjacent to a first edge of the first intervening layer in plan view, and the second portion of the first edge region is adjacent to a second edge of the first intervening layer, different from the first edge, in plan view.
In one or more second embodiments, a method comprises forming a first electrode over a substrate, forming a first layer over the first electrode and offset from the first electrode in at least one dimension in plan view, forming a second electrode over the first layer, the second electrode being offset from the first layer and the first electrode in at least one dimension in plan view, forming a second layer over the second electrode, and forming a third electrode over the second layer. A surface of the substrate, over which the first electrode is formed, is non-planar.
In the second embodiments or any other embodiment, in plan view, the first and third electrodes do not overlap with the second electrode, the first layer, and the second layer in a first edge region, and parts of the first and third electrodes are in direct contact with each other in said first edge region.
In the second embodiments or any other embodiment, the method comprises forming a third layer over the third electrode and aligned with the first layer in plan view, and forming a fourth electrode over the third layer. The fourth electrode is aligned with the second electrode in plan view, the second and fourth electrodes do not overlap with the first electrode, the third electrode, and the first through third layers in a second edge region in plan view, and parts of the second and fourth electrodes are in direct contact with each other in said second edge region.
In the second embodiments or any other embodiment, the method comprises forming a first wiring layer in or overlapping with the first edge region in plan view so as to electrically connect to the first and third electrodes, and forming a second wiring layer in or overlapping with the second edge region in plan view so as to electrically connect to the second and fourth electrodes.
In the second embodiments or any other embodiment, the first through third electrodes have the same pattern, and the forming of the first through third electrodes employ the same shadow mask. In the second embodiments or any other embodiment, the first through third electrodes and the first and second layers have the same pattern, and the forming of the first through third electrodes and the first and second layers employ the same shadow mask.
In the second embodiments or any other embodiment, each of the first and third electrodes comprises one of an anode and a cathode of a multi-layer solid-state battery, the second electrode comprises the other of an anode and a cathode of the multi-layer solid-state battery, and each of the first and second layers comprises a solid electrolyte. In the second embodiments or any other embodiment, each of the first through third electrodes comprises a respective current collector layer for electron transport.
In the second embodiments or any other embodiment, the forming the first electrode includes forming a first current collector layer over the substrate, and forming a sublayer of the first electrode over the first current collector layer. In the second embodiments or any other embodiment, forming a sublayer of the second electrode over the first layer, forming a second current collector layer over the sublayer of the second electrode, and forming another sublayer of the second electrode over the second current collector layer. In the second embodiments or any other embodiment, forming a sublayer of the third electrode over the second layer, and depositing a third current collector layer over the sublayer of the third electrode.
In the second embodiments or any other embodiment, the first current collector layer and the sublayer of the first electrode have the same pattern and are aligned with each other in plan view, the second current collector layer and the sublayers of the second electrode have the same pattern and are aligned with each other in plan view, and/or the third current collector layer and the sublayer of the third electrode have the same pattern and are aligned with each other in plan view.
In the second embodiments or any other embodiment, the forming of the first through third current collector layers and the sublayers of the first through third electrodes employ the same shadow mask. In the second embodiments or any other embodiment, the first current collector layer has a pattern different from that of the sublayer of the first electrode, the second current collector layer has a pattern different from that of the sublayers of the second electrode, and/or the third current collector layer has a pattern different from that of the sublayer of the third electrode.
In the second embodiments or any other embodiment, each of the first through third electrodes comprises an upper sublayer, a current collector layer for electron transport, and a lower sublayer, and the current collector layer is disposed between the upper and lower sublayers in cross-sectional view.
In the second embodiments or any other embodiment, the first layer is offset from the first electrode in at least two orthogonal dimensions in plan view, and/or the second electrode is offset from the first layer and the first electrode in at least two orthogonal dimensions in plan view.
In the second embodiments or any other embodiment, each of first through third electrodes and the first and second layers are formed over respective three-dimensional features formed on the substrate. In the second embodiments or any other embodiment, each of first through third electrodes and the first and second layers are formed over respective three-dimensional features of the substrate, so as to conform or follow a cross-sectional profile of the three-dimensional features.
In the second embodiments or any other embodiment, the three-dimensional features comprise an electronic device separated from the first electrode by at least a passivation film. In the second embodiments or any other embodiment, said three-dimensional features include at least one of a projection and a recess.
In the second embodiments or any other embodiment, an aspect ratio of height to width of the three-dimensional features is less than 5:1, and the forming of at least one of first through third electrodes and first and second layers comprises a physical vapor deposition or physical liquid deposition technique.
In the second embodiments or any other embodiment, an aspect ratio of height to width of said three-dimensional features is at least 3:1, and the forming of at least one of first through third electrodes and first and second layers comprises a chemical deposition technique.
In the second embodiments or any other embodiment, thicknesses of each of the first through third electrodes and the first and second layers over one portion of the substrate are different from the thicknesses of each of the first through third electrodes and the first and second layers, respectively, over another portion of the substrate.
In the second embodiments or any other embodiment, the forming of at least one of the first through third electrodes and first and second layers comprises at least one of vacuum deposition and sol-gel application. In the second embodiments or any other embodiment, the forming of the first through third electrodes and first and second layers are performed under a continuous vacuum. In the second embodiments or any other embodiment, at least a portion of the non-planar surface of the substrate has a non-zero curvature in cross-sectional view.
In the second embodiments or any other embodiment, each of the first through third electrodes comprises an electrically conductive layer of a multi-layer capacitor, and each of the first and second layers comprises a dielectric. In the second embodiments or any other embodiment, each of the first through third electrodes comprises an electrically conductive layer of a multi-layer solar cell, and each of the first and second layers comprises semiconductor active layers forming a p-n junction. In the second embodiments or any other embodiment, each of the first through third electrodes comprises an electrically conductive layer of a multi-layer sensor, and each of the first and second layers comprises a piezo-electric material. In the second embodiments or any other embodiment, each of the first through third electrodes comprises an electrically conductive layer of a multi-layer light-emitting diode, and each of the first and second layers comprises semiconductor active layers forming a p-n junction.
In one or more third embodiments, a multi-layer solid-state device is fabricated by the method of any of the first and second embodiments. In the third embodiments or any other embodiment, the solid-state device includes at least one of a multi-layer battery, a multi-layer sensor, a multi-layer light-emitting diode, a multi-layer solar cell, or a multi-layer capacitor.
In one or more fourth embodiments, a multi-layer solid-state device comprises a substrate, first through third electrodes, and first through second intervening layers. The substrate has a non-planar surface. The first electrode is formed over the non-planar surface of the substrate. The first intervening layer is formed over the first electrode. The second electrode is formed over the first intervening layer. The second intervening layer is formed over the second electrode. The third electrode is formed over the second intervening layer. In plan view, the first electrode is aligned with the third electrode, the first intervening layer is aligned with the second intervening layer, the first and third electrodes are offset in at least one dimension from the first and second intervening layers, and the second electrode is offset in at least one dimension from the first and third electrodes and from the first and second intervening layers.
In the fourth embodiments or any other embodiment, parts of the first and third electrodes are in direct contact with each other in a first edge region that does not overlap with the second electrode and the first and second intervening layers in plan view, and each intervening layer is spaced from the first edge region.
In the fourth embodiments or any other embodiment, the solid-state device comprises a third intervening layer formed over the third electrode, and a fourth electrode formed over the third intervening layer. In the fourth embodiments or any other embodiment, in plan view, the fourth electrode is aligned with the second electrode, the third intervening layer is aligned with the first intervening layer, the second and fourth electrodes are offset in at least one dimension from the first and third electrodes and from the first through third intervening layers, and parts of the second and fourth electrodes are in direct contact with each other in a second edge region that does not overlap with the first and third electrodes and the first through third intervening layers.
In the fourth embodiments or any other embodiment, the solid-state device comprises a first wiring layer formed on an uppermost electrode in the first edge region, the first wiring layer being electrically connected to the first and third electrodes, and a second wiring layer formed on an uppermost electrode in the second edge region, the second wiring layer being electrically connected to the second and fourth electrodes.
In the fourth embodiments or any other embodiment, the solid-state device comprises a first wiring layer formed in direct contact with respective edges of the first and third electrodes in the first edge region, the first wiring layer being electrically connected to the first and third electrodes, and a second wiring layer formed in direct contact with respective edges of the second and fourth electrodes, the second wiring layer being electrically connected to the second and fourth electrodes.
In the fourth embodiments or any other embodiment, the first wiring layer and the second wiring layer are on opposite sides of the first intervening layer in plan view.
In the fourth embodiments or any other embodiment, the solid-state device comprises a housing with a pair of contact terminals. In the fourth embodiments or any other embodiment, the first wiring layer connects to one of the contact terminals and the second wiring layer connects to another of the contact terminals.
In the fourth embodiments or any other embodiment, the device is constructed as a battery, each of the first and third electrodes comprises one of an anode and a cathode, the second electrode comprises the other of an anode and a cathode, and each intervening layer comprises a solid electrolyte.
In the fourth embodiments or any other embodiment, each of the first through third electrodes comprises a respective current collector layer for electron transport. In the fourth embodiments or any other embodiment, the first electrode comprises a first electrode layer disposed over a first current collector layer, the second electrode comprises a second current collector layer disposed between a second electrode layer and a third electrode layer in a thickness direction, and the third electrode comprises a third current collector layer disposed over a fourth electrode layer. In the fourth embodiments or any other embodiment, the third electrode comprises a fifth electrode layer over the third current collector layer, such that the third current collector layer is between the fourth and fifth electrode layers in the thickness direction.
In the fourth embodiments or any other embodiment, each of the first through electrodes comprises an upper electrode layer, a current collector layer for electron transport, and a lower electrode layer, and the current collector layer is disposed between the upper and lower electrode layers in cross-sectional view.
In the fourth embodiments or any other embodiment, the first electrode, the second electrode, and the third electrode have a same shape in plan view. In the fourth embodiments or any other embodiment, the first electrode, the second electrode, the third electrode, the first intervening layer, and the second intervening layer have the same shape in plan view. In the fourth embodiments or any other embodiment, the shape of the first electrode is non-rectangular or irregular.
In the fourth embodiments or any other embodiment, in plan view, the first and third electrodes are offset in two orthogonal dimensions from the first and second intervening layers, and the second electrode is offset in two orthogonal dimensions from the first and third electrodes and from the first and second intervening layers.
In the fourth embodiments or any other embodiment, the substrate has at least one protrusion or at least one recess that define said non-planar surface, and the first through third electrodes and the first through second intervening layers are formed over surfaces of the at least one protrusion or at least one recess. In the fourth embodiments or any other embodiment, the at least one protrusion or at least one recess has an aspect ratio of height to width of at least 0.5:1. In the fourth embodiments or any other embodiment, the at least one protrusion or at least one recess has an aspect ratio of height to width of at least 3:1. In the fourth embodiments or any other embodiment, the substrate has multiple protrusions and/or recesses, and the first through third electrodes and the first through second intervening layers are formed over surfaces of each protrusion and/or recess.
In the fourth embodiments or any other embodiment, thicknesses of the first through third electrodes and the first through second intervening layers at a top surface of the protrusion or at a bottom surface of the recess are different from corresponding thicknesses of the first through third electrodes and the first through second intervening layers on a surface of the substrate adjacent to said protrusion or recess. In the fourth embodiments or any other embodiment, thicknesses of the first through third electrodes and the first through second intervening layers at a top surface of the protrusion or at a bottom surface of the recess are substantially the same as corresponding thicknesses of the first through third electrodes and the first through second intervening layers on a surface of the substrate adjacent to said protrusion or recess.
In the fourth embodiments or any other embodiment, the device is constructed as a capacitor, each of the first through third electrodes comprises an electrically conductive layer, and each intervening layer comprises a dielectric. In the fourth embodiments or any other embodiment, the device is constructed as one of a solar cell and a light-emitting diode, each of the first through third electrodes comprises an electrically conductive layer, and each intervening layer comprises semiconductor active layers forming a p-n junction. In the fourth embodiments or any other embodiment, the device is constructed as a sensor, each of the first through third electrodes comprises an electrically-conductive layer, and each intervening layer comprises a piezo-electric material.
In the fourth embodiments or any other embodiment, the substrate comprises a 3-D scaffold with numerous surface features over which the first electrode is formed. In the fourth embodiments or any other embodiment, the substrate comprises a semiconductor substrate. In the fourth embodiments or any other embodiment, the substrate comprises a shaped metal foil. In the fourth embodiments or any other embodiment, the shaped metal foil is a convoluted aluminum foil. In the fourth embodiments or any other embodiment, the substrate comprises another electrode of the device.
In the fourth embodiments or any other embodiment, the substrate comprises an electronic device. In the fourth embodiments or any other embodiment, the electronic device is electrically connected to at least one of the first through third electrodes. In the fourth embodiments or any other embodiment, the electronic device comprises a complementary metal-oxide-semiconductor (CMOS) device. In the fourth embodiments or any other embodiment, the substrate includes a passivation film disposed between the electronic device and the first electrode in cross-sectional view. In the fourth embodiments or any other embodiment, a wiring layer extends through the passivation film to electrically connect the electronic device with at least one of the first through third electrodes.
In one or more fifth embodiments, a system comprises multiple multi-layer solid-state batteries according to any of the third and fourth embodiments, or formed according to the method of any of the first and second embodiments. Each of the batteries can be formed on a common substrate, and at least some of the batteries being electrically connected together in series, in parallel, or in combinations of series and parallel.
In the fifth embodiments or any other embodiment, the system comprises a power management chip disposed on the common substrate and configured to control operation of the batteries. In the fifth embodiments or any other embodiment, the system comprises at least one electronic device formed on the common substrate.
In the fifth embodiments or any other embodiment, the system comprises at least one of a multi-layer solid-state capacitor formed on the common substrate, a multi-layer sensor formed on the common substrate, a multi-layer solar cell formed on the common substrate, and a multi-layer light-emitting diode formed on the common substrate. In the fifth embodiments or any other embodiment, said multi-layer solid-state capacitor, said multi-layer sensor, said multi-layer solar cell, or said multi-layer light-emitting diode can be according to any of the third and fourth embodiments, or formed according to the method of any of the first and second embodiments
It will be appreciated that the aspects of the disclosed subject matter, for example, control of the deposition process to form the multi-layer solid-state device, can be implemented, fully or partially, in hardware, hardware programmed by software, software instruction stored on a computer readable medium (e.g., a non-transitory computer readable medium), or any combination of the above.
For example, components of the disclosed subject matter, including components such as a control unit, controller, processor, or any other feature, can include, but are not limited to, a personal computer or workstation or other such computing system that includes a processor, microprocessor, microcontroller device, or is comprised of control logic including integrated circuits such as, for example, an application specific integrated circuit (ASIC).
Features discussed herein can be performed on a single or distributed processor (single and/or multi-core), by components distributed across multiple computers or systems, or by components co-located in a single processor or system. For example, aspects of the disclosed subject matter can be implemented via a programmed general purpose computer, an integrated circuit device, (e.g., ASIC), a digital signal processor (DSP), an electronic device programmed with microcode (e.g., a microprocessor or microcontroller), a hard-wired electronic or logic circuit, a programmable logic circuit (e.g., programmable logic device (PLD), programmable logic array (PLA), field-programmable gate array (FPGA), programmable array logic (PAL)), software stored on a computer-readable medium or signal, an optical computing device, a networked system of electronic and/or optical devices, a special purpose computing device, a semiconductor chip, a software module or object stored on a computer-readable medium or signal.
When implemented in software, functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The steps of a method or algorithm disclosed herein may be embodied in a processor-executable software module, which may reside on a computer-readable medium. Instructions can be compiled from source code instructions provided in accordance with a programming language. The sequence of programmed instructions and data associated therewith can be stored in a computer-readable medium (e.g., a non-transitory computer readable medium), such as a computer memory or storage device, which can be any suitable memory apparatus, such as, but not limited to read-only memory (ROM), programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), flash memory, disk drive, etc.
As used herein, computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. Thus, a storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer.
Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a transmission medium (e.g., coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave), then the transmission medium is included in the definition of computer-readable medium. Moreover, the operations of a method or algorithm may reside as one of (or any combination of) or a set of codes and/or instructions on a machine-readable medium and/or computer-readable medium, which may be incorporated into a computer program product.
One of ordinary skill in the art will readily appreciate that the above description is not exhaustive, and that aspects of the disclosed subject matter may be implemented other than as specifically disclosed above. Indeed, embodiments of the disclosed subject matter can be implemented in hardware and/or software using any known or later developed systems, structures, devices, and/or software by those of ordinary skill in the applicable art from the functional description provided herein.
In this application, unless specifically stated otherwise, the use of the singular includes the plural, and the separate use of “or” and “and” includes the other, i.e., “and/or.” Furthermore, use of the terms “including” or “having,” as well as other forms such as “includes,” “included,” “has,” or “had,” are intended to have the same effect as “comprising” and thus should not be understood as limiting.
Any range described herein will be understood to include the endpoints and all values between the endpoints. Whenever “substantially,” “approximately,” “essentially,” “near,” or similar language is used in combination with a specific value, variations up to and including 10% of that value are intended, unless explicitly stated otherwise.
It is thus apparent that there is provided, in accordance with the present disclosure, multi-layer solid-state devices and methods for forming the same. Many alternatives, modifications, and variations are enabled by the present disclosure. While specific examples have been shown and described in detail to illustrate the application of the principles of the present invention, it will be understood that the invention may be embodied otherwise without departing from such principles. For example, disclosed features may be combined, rearranged, omitted, etc. to produce additional embodiments, while certain disclosed features may sometimes be used to advantage without a corresponding use of other features. Accordingly, Applicant intends to embrace all such alternative, modifications, equivalents, and variations that are within the spirit and scope of the present invention.
The present application claims the benefit of U.S. Provisional Application No. 62/613,861, filed Jan. 5, 2018, which is hereby incorporated by reference herein in its entirety.
This invention was made with government support under DESC0001160 awarded by the Department of Energy (DOE). The government has certain rights in the invention.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US19/12180 | 1/3/2019 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 62613861 | Jan 2018 | US |
