MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR

Abstract

A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of embodiments of the invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings in which:

FIG. 1 illustrates access paths of a conventional semiconductor memory device having four memory banks and a single input/output port;

FIG. 2 is a schematic block diagram illustrating a multi-port semiconductor memory device according to an embodiment of the invention;

FIG. 3 is a block diagram illustrating a select control unit 400a and first and second port control units 200a and 300a for an A bank in FIG. 2;

FIG. 4 is a circuit diagram of a first command multiplexer of FIG. 3;

FIG. 5 is a circuit diagram illustrating a row address multiplexer of FIG. 3;

FIG. 6 is a circuit diagram illustrating a first data sense amplifier of FIG. 3;

FIG. 7 is a circuit diagram illustrating a first data driver of FIG. 3;

FIG. 8 is a circuit diagram illustrating a first data multiplexer of FIG. 3; and

FIGS. 9 to 15 illustrate an example of an access path control operation in a semiconductor memory device according to an embodiment of the invention.

Claims

1. A semiconductor memory device comprising: a plurality of input/output ports;a memory array divided into a plurality of memory areas; anda select control unit to establish variable access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

2. The device according to claim 1, wherein the select control unit establishes the variable access paths in response to external command signals.

3. The device according to claim 2, wherein the external command signals are generated based on a mode register set (MRS) code signal or by a combination of any command signals.

4. The device according to claim 2, wherein the select control unit controls a data path and an address path between the input/output ports and the memory areas in response to the external command signals.

5. The device according to claim 2, wherein the select control unit operates in a normal operation mode in response to external command signals for a normal operation and operates in a test mode in response to external command signals for a test operation.

6. The device according to claim 3, wherein the external command signals are separate, independent signals that each correspond to the memory areas.

7. A semiconductor memory device comprising: First and second input/output ports;a memory array divided into a plurality of memory areas; anda select control unit to establish variable access paths between the memory areas and the first and second input/output ports such that each memory area is variably allocated as one of a first input/output port dedicated access area, a second input/output port dedicated access area, and a shared access area.

8. The device according to claim 7, wherein the select control unit variably allocates the memory areas in response to external command signals.

9. The device according to claim 8, wherein the external command signals are generated based on an MRS code signal or by a combination of any command signals.

10. The device according to claim 9, wherein the select control unit comprises: a command multiplexer to generate select control signals in response to the external command signals, wherein the select control signals allocate each memory area as one of the first input/output port dedicated access area, the second input/output port dedicated access area, and the shared access area;a data multiplexer to control data paths between the input/output ports and the memory areas in response to the select control signals; andan address multiplexer to control address paths between the input/output ports and the memory areas in response to the select control signals.

11. The device according to claim 10, wherein the select control unit operates in a normal operation mode in response to external command signals based on an MRS code signal for a normal operation and operates in a test mode in response to external command signals based on an MRS code signal for a test operation.

12. The device according to claim 11, wherein the external command signals are separate, independent signals that each correspond to the memory areas.

13. In a semiconductor memory device comprising a plurality of input/output ports and a memory array divided into a plurality of memory areas, a method for variably accessing the memory areas, comprising: applying external command signals to allocate the memory areas for access through at least one of the input/output ports;establishing data and address paths between the memory areas and corresponding input/output ports according to the memory area allocation;re-applying the external command signals to re-allocate the memory areas for access through different input/output ports; andestablishing new data and address paths between the memory areas and the corresponding different input/output ports according to the memory area re-allocation.

14. The method according to claim 13, wherein when the semiconductor memory device has first and second input/output ports, each memory area is variably allocated as one of a first input/output port dedicated access area, a second input/output port dedicated access area, and a shared access area.

15. The method according to claim 13, wherein the external command signals are generated based on an MRS code signal or by a combination of any command signals.

16. The method according to claim 13, wherein the external command signals are separate, independent signals that each correspond to the memory areas for memory area allocation.

17. A method for testing a multi-port semiconductor memory device comprising a plurality of input/output ports and a memory array divided into a plurality of memory areas, comprising: allocating the memory areas to each input/output port, so that each memory area is accessed through at least one of the input/output ports;testing the allocated memory areas through each corresponding input/output port;re-allocating the memory areas, so that each memory area is access through different input/output ports; andtesting the re-allocated memory areas through the corresponding different input/output ports.

18. The method according to claim 17, wherein allocating the memory areas to each input/output port is performed in response to external command signals corresponding to a test environment.

19. The method according to claim 18, wherein the external command signal is based on an MRS code signal for testing.

20. The method according to claim 18, wherein when the semiconductor memory device has first and second input/output ports, each memory area is allocated as a first input/output port dedicated access area or a second input/output port dedicated access area.