Multi-rank memory module that emulates a memory module having a different number of ranks

Abstract

A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

Description

FIELD OF THE INVENTION

The present invention relates to computer memory. More particularly, the present invention relates to a four rank memory module.

BACKGROUND OF THE INVENTION

Computers use memory devices for the storage and retrieval of information. These memory devices are often mounted on a memory module to expand the memory capacity of a computer. Sockets on a main board accommodate those memory modules also known as SIMMs or DIMMs.

FIG. 1 is a diagram schematically illustrating a standard memory interface system overview in accordance with a prior art. The system 100 includes a processor 102, a memory controller 104, and a memory module 106. The processor 102 communicates with the memory controller 104 with an address bus 108, a control signal bus 110, and a data bus 112. The memory controller 104 communicates with the memory module 106 with a controller address bus 114, a controller control signal bus 116, and a controller data bus 118. Common system implementations 100 have typically two memory chip selects routed per socket. Common memory module 106 may have two chip selects (one per rank) or four chip selects (two per rank). In one implementation, each chip select from the controller is connected to the corresponding chip select on the memory module. In the second implementation, each chip select from the controller is connected to the two chip selects (those that control one rank) on the memory module. The system chip select signals control individual memory modules ranks. The memory module 106 is coupled to the memory controller 104 through a memory socket.

Standard memory modules such as memory module 106 have either one rank or two rank of memory devices. Each memory device comes in a variety of configurations and families such as 128 Mbit, 256 Mbit, 512 Mbit, and 1024 Mbit DDR SDRAM families. Each of these families is further divided into three distinct flavors such as ×4, ×8, and ×16 data bits. For example, a single 128 Mbit DDR SDRAM family comes in three flavors of:

• • 32M×4 (32 Mega cell of 4-bit each=32M×4-bit=128 Mbit)
  • 16M×8 (16 Mega cell of 8-bit each=16M×8-bit=128 Mbit)
  • 8M×16 (8 Mega cell of 16-bit each=8M×16-bit=128 Mbit)

The example above illustrates that all three different data bits flavors result in the same density of 128 Mbit. As the number of data bits doubles the cell numbers decrease by half. One can build memory modules with similar densities using different data bits flavors.

One method of building a 512M Byte standard memory module with ECC (64-bit data plus 8-bit ECC=72-bit) include using 256 Mbit density families of 32M×8 to achieve the density of 512M Byte as follow:

• Rank 0=9×(32M×8) devices=32M×72-bit which equates to 32M×8 Bytes+1 Byte of ECC. This yields a total density of 32M×8 Bytes=256M Byte.
• Rank 1=9×(32M×8) devices=32M×72-bit which equates to 32M×8 Bytes+1 Byte of ECC. This yields a total density of 32M×8 Bytes=256M Byte.

Therefore, a two rank memory module with 18 device placements will achieve the 512M Byte density. Furthermore, it should be noted that a standard DDR 184-pin memory module can only fit nine TSSOP placements per side, or a total of 18 placements of TSSOP per module, considering both front and back sides based on a standard defined height limits by JEDEC.

Because memory devices with lower densities are cheaper and more readily available, it may be advantageous to build the above same density memory module using lower densities devices. However, in order to achieve a density of, for example, 512M Bytes using 128 Mbit density of 16M×8 instead, the memory module needs four ranks configured as follows:

• Rank 0=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128M Byte.
• Rank 1=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128M Byte.
• Rank 2=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128M Byte.
• Rank 3=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128M Byte.

In order to achieve the above configuration, 4 rows of 9 devices each, totaling 36 placements, are required. As mentioned above, on a standard 184-pin DDR memory module, there is only enough space for 18 TSSOP devices.

The only solution would be, to stack two memory devices together to achieve an extra rank on the same placement space. Although this would solve the placement problem of 36 TSSOP devices, the memory module would still possess four memory ranks. As explained earlier, all standard memory modules have only two chip select signals per memory socket routed. Therefore, such memory module would not be viable.

A need therefore exists for a transparent four rank memory module fitting into a memory socket having two chip select signals routed. A primary purpose of the present invention is to solve these needs and provide further, related advantages.

BRIEF DESCRIPTION OF THE INVENTION

A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present invention and, together with the detailed description, serve to explain the principles and implementations of the invention.

In the drawings:

FIG. 1 is a block diagram schematically illustrating a standard memory interface system in accordance with a prior art.

FIG. 2 is a diagram schematically illustrating a stacked DDR device in accordance with one embodiment of the present invention.

FIG. 3 is a diagram schematically illustrating a transparent four rank DDR memory module in accordance with one embodiment of the present invention.

FIG. 4A is a diagram schematically illustrating the front side of a transparent 72-bit registered DDR module in accordance with one embodiment of the present invention.

FIG. 4B is a diagram schematically illustrating the back side of a transparent 72-bit registered DDR module in accordance with one embodiment of the present invention.

FIG. 5 is a truth table for a transparent four rank memory module in accordance with one embodiment of the present invention.

FIG. 6A is a block diagram schematically illustrating a row address decoding system for a transparent four rank memory module in accordance with one embodiment of the present invention.

FIG. 6B is a block diagram schematically illustrating a column address decoding system for a transparent four rank memory module in accordance with one embodiment of the present invention.

FIG. 7 is a flow diagram schematically illustrating a method for emulating a two rank memory module.

FIG. 8 is a block diagram schematically illustrating a CPLD in a transparent four rank DDR memory module in accordance with one embodiment of the present invention

DETAILED DESCRIPTION

Embodiments of the present invention are described herein in the context of a memory module. Those of ordinary skill in the art will realize that the following detailed description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.

In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

In accordance with one embodiment of the present invention, the components, process steps, and/or data structures may be implemented using various types of operating systems (OS), computing platforms, firmware, computer programs, computer languages, and/or general-purpose machines. The method can be run as a programmed process running on processing circuitry. The processing circuitry can take the form of numerous combinations of processors and operating systems, or a stand-alone device. The process can be implemented as instructions executed by such hardware, hardware alone, or any combination thereof. The software may be stored on a program storage device readable by a machine.

In addition, those of ordinary skill in the art will recognize that devices of a less general purpose nature, such as hardwired devices, field programmable logic devices (FPLDs), including field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), application specific integrated circuits (ASICs), or the like, may also be used without departing from the scope and spirit of the inventive concepts disclosed herein.

FIG. 2 is a block diagram of an example of a standard stacked DDR 8 bit memory device 200 used in a memory module in accordance with one embodiment of the present invention. The memory device 200 interfaces with a memory controller (not shown) with three buses: an address bus 202, a control bus 204, and a data bus 206. A differential clock bus 208 is also coupled to the DDR memory device 200.

The address bus 202 conveys the following signals: address[n:0] 210 and BA[1:0] 212.

The control bus 204 conveys the following signals: RAS 214, CAS 216, WE 218, DQM 220, CS[1:0] 222, and CKE[1:0] 224.

The data bus 206 conveys the following signals: data signals [7:0] 226 and DQS 228.

The differential clock bus 208 includes two signals: clk 230, and clk_n 232.

FIG. 3 illustrates a block diagram of stacked 8 bit memory devices on the front and back side of a memory module 300 in accordance with one embodiment of the present invention. The memory module's front side 302 includes a first rank 304 of memory devices 306 (U1 through U9). The first rank 304 is stacked with a third rank 308 of memory devices 306 (U19 through U27). As illustrated in FIG. 3, data bus [7:0] is connected to both ranks' memory devices 306 (U1 and U19). The remaining data buses are connected to their respective ranks' memory devices 306. A chip select signal is coupled to each rank of memory devices. As illustrated in FIG. 3, chip select signal cs0 is connected to the first rank 304 (from U1 to U9) and chip select signal cs2 is connected to the third rank 308 (from U19 to U27).

The memory module's back side 310 includes a second rank 312 of memory devices 306 (U10 through U18). The second rank 312 is stacked with a fourth rank 314 of memory devices 306 (U28 through U36). As illustrated in FIG. 3, data bus [7;0] is connected to both ranks' memory devices 306 (U10 and U28). The remaining data buses are connected to their respective ranks' memory devices 306. A chip select signal is coupled to each rank of memory devices. As illustrated in FIG. 3, chip select signal cs1 is connected to the second rank 312 (from U10 to U18) and chip select signal cs3 is connected to the fourth rank 314 (from U28 to U36).

FIG. 3 also illustrates a total of four chip select signals (cs0, cs1, cs2, and cs3). As illustrated in FIG. 2, the stacked memory device 200 has only two chip select signals: cs[1:0] 222. In accordance with one embodiment of the invention, the present invention allows the four rank memory modules to communicate with a memory socket having only two chip select signals routed.

FIG. 4A illustrates a schematic diagram of the front side of a transparent 72 bit registered DDR module 400 in accordance with one embodiment of the present invention. The memory module 400 includes 92 contact pins 402 on the front side for connecting with a memory socket (not shown). The memory module 400 as illustrated in FIG. 4A includes nine 8 bit stacked memory devices 404, nine corresponding Resistor Network (Rn) 406, a register 408, a CPLD 410, a PLL 412, and a SPD 414. The stacking of the 8 bit stacked memory devices 404 was previously illustrated in FIG. 3. Memory devices 404 (U1 through U9) are mounted on a surface of the front side of the memory module 400. Memory devices 404 (U19 through U27) are respectively stacked on memory devices 404 (U1 through U9). Therefore the front side of the four rank memory modules 400 includes two ranks (rank 0 and rank 2).

The register 408 is used to synchronize the incoming address and control signals with respect to differential clock signals 208 (clk and clk_n). Also, the register 408 may eliminate the loading of 36 devices in case of stacking or loading of 18 devices in case of monolithic memory devices from the main controller by separating the controller side signaling with memory side signal loading fan-out.

The PLL 412 is used to generate a zero-delay buffer off of system side input differential clock signals 208 (clk and clk_n). By using a PLL, the system side will not see the loading effect of either 18 differential clock loads or 36 differentials clock loads in the case of stacking memory devices.

The SPD 414 is a simple I2C interface EEPROM to hold information regarding memory module for BIOS during the power-up sequence.

The CPLD 410 emulates a two rank memory module on the four rank memory module 400. CPLD 410 allows a system having a memory socket with only two chip select signals routed to interface with a four rank memory module where typically a two rank memory module couples with the memory socket. The CPLD 410 determines which rank from the four ranks to activate based upon the address and command signals from a memory controller coupled to the memory module 410. The algorithm of CPLD 410 is further described in FIGS. 5 and 7.

FIG. 4B illustrates a schematic diagram of the back side of the transparent 72 bit registered DDR module 400 in accordance with one embodiment of the present invention. The memory module 400 includes 92 contact pins 416 on the back side for connecting with a memory socket (not shown). Therefore, memory module 400 has a total of 184 different contact pins on the front and back side. The memory module 400 as illustrated in FIG. 4B includes nine 8 bit stacked memory devices 404, nine corresponding Resistor Network (Rn) 406, another register 418. The stacking of the 8 bit stacked memory devices 404 was previously illustrated in FIG. 3. Memory devices 404 (U10 through U18) are mounted on a surface of the back side of the memory module 400. Memory devices 404 (U28 through U36) are respectively stacked on memory devices 404 (U10 through U18). Therefore the back side of the four rank memory module 400 includes two ranks (rank 1 and rank 3).

FIG. 5 illustrates a truth table used in the process of the CPLD 410 to determine which rank is active (rank 0, rank 1, rank 2, or rank 3). CPLD 410 utilized three variables to determine the active rank: the highest address number Add(n), a first chip select signal (CS0), and a second chip select signal (CS1). As previously mentioned, each memory socket includes two active chip select signals (CS0 and CS1). CPLD 410 combines these two variables (CS0 and CS1) with the address number signal 210 from the address bus 202 to determine the active rank. Add(n) includes the highest binary digit from the address number signal 210. For example, the highest address number Add(n) when the address signal 210 is 10010 would be the first digit to the left: “1”.

As illustrated in FIG. 5, rank 0 is active when the Add(n) is 0, CS1 is 1, and CS0 is 0. Rank 1 is active when the Add(n) is 0, CS1 is 0, and CS0 is 1. Rank 2 is active when the Add(n) is 1, CS1 is 1, and CS0 is 0. Rank 3 is active when the Add(n) is 1, CS1 is 0, and CS0 is 1.

Because the row address and column address may differ between different memory device densities, the CPLD may employ two different decoding schemes: a Row Address Decoding scheme, and a Column Address Decoding scheme. The following non-limiting example is used for illustration purposes.

A 512 MByte memory module may be build with either two rank of 256 MByte density per rank or four ranks of 128 MByte density per rank. However, a 128 Mbit DDR SDRAM has different characteristics from a 256 Mbit DDR SDRAM device.

A 128 Mbit DDR SDRAM (16M×8) has the following characteristics:

Configuration  4 M × 8 × 4
Refresh Rate   4K
Row Address    A0-A11
Column Address A0-A9

A 256 Mbit DDR SDRAM (32M×8) has the following characteristics:

Configuration  8 M × 8 × 4
Refresh Rate   8K
Row Address    A0-A12
Column Address A0-A9

The size of the column addresses (A0-A9) for both 128 Mbit DDR SDRAM and 256 Mbit DDR SDRAM devices match. However, the size of the row address for the 128 Mbit DDR SDRAM differs by one row address line from the 256 Mbit DDR SDRAM (A12). The CPLD 410 uses a Row Address Decoding scheme to emulate a two rank based on 256 Mbit DDR SDRAM Device Technology memory module with a four rank based on 128 Mbit DDR SDRAM Device Technology memory module. Under this scheme, address lines A0-A11 go to module register 408 and 418 and address lines A12 goes into CPLD 410 along with CS0 and CS1 for proper decoding. Therefore, the extra address line A12 is used by the CPLD to determine which rank (from the four ranks) is active. The decoding is performed as previously illustrated in FIG. 5 above. For example, if address bus (A12-A0) has “1000010101010” and CS0 is “0” and CS1 is “1”, then rank 2 is activated. In this present example, Add(n) for A12 is “1”. The Row Address Decoding scheme is further illustrated in FIG. 6A.

FIG. 6A illustrates a method for decoding row addresses in accordance with one embodiment of the present invention. A module connector 602 (for example, the contact pins 402 and 416) sends signals to the CPLD 604, PLL 606, and register 608. The signals sent to CPLD 604 include cs0, cs1, Add(n), CAS, RAS, WE, CLK0, and CLK0_N. The signals sent to PLL 606 include CLK0, and CLK0_N. PLL relays the CLK0 and CLK0_N signals to register 608 and memory devices 306. Register 608 also receives the following signals from module connector 602: Add[n−1;0], RAS, CAS, WE, BA[1:0], CKE.

As illustrated in the example above, the 256 Mbit memory devices has an extra row address line (A12) when compared to the 128 Mbit memory devices. Register 608 of a four rank memory module emulating a two bank memory module receives an address with an address size matching the address size of the lower density memory devices (128 Mbit), i.e. A0-A11. In other words, the address signal from the module connector 608 does not include the extra row address line A12.

CPLD 604 also ensures that all commands for a two rank memory module conveyed by the module connector 602 are also performed on the four rank memory modules. For example, CPLD 604 generates rcs2 and rcs3, besides rcs0 and rcs1 off of CS0, CS1 and Add(n) from the memory controller side. CPLD 604 also generates rcs2 when CS0 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs2 when CS0 Auto Refresh Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Refresh Commands are issued. CPLD 604 also generates rcs2 when CS0 Load Mode Register Commands are issued. CPLD 604 also generates rcs3 when CS1 Load Mode Register Commands are issued.

However, as previously mentioned, a memory module may also be built using two device families which only differs in their column address size, and have the same row address size. The following example illustrates this situation and describes the Column Decoding Scheme.

A 1024 Mbyte memory module may be build with either two rank of 512 MByte density per rank or four ranks of 256 MByte density per rank. However, the 256 Mbit DDR SDRAM has different characteristics from a 512 Mbit DDR SDRAM.

A 256 Mbit DDR SDRAM (32M×8) has the following characteristics:

Configuration  8 M × 8 × 4
Refresh Rate   8K
Row Address    A0-A12
Column Address A0-A9

A 512 Mbit DDR SDRAM (64M×8) has the following characteristics:

Configuration  16 M × 8 × 4
Refresh Rate   8K
Row Address    A0-A12
Column Address A0-A9, A11

The size of the row addresses (A0-A9) for both 256 Mbit DDR SDRAM and 512 Mbit DDR SDRAM devices match. However, the size of the column address for the 256 Mbit DDR SDRAM differ by one address line from the 512 Mbit DDR SDRAM (A11). The CPLD 410 uses the Column Address Decoding scheme to emulate a two ranks 512 Mbit based DDR SDRAM device Technology memory module with a four ranks 256 Mbit based DDR SDRAM device Technology memory module. Under this scheme, address lines A0-A12 go to module register 408 and 418 and address lines A11 goes into CPLD 410 along with CS0 and CS1 for proper decoding. Therefore, the address line A11 is used by the CPLD to determine which rank (from the four ranks) is active. The decoding is performed as previously illustrated in FIG. 5 above. For example, if address bus (A11, A9-A0) has “100110101010” and CS0 is “0” and CS1 is “1”, then rank 2 is activated. In this present example, Add(n) for A11 is “1”. The Column Address Decoding scheme is further illustrated in FIG. 6B.

FIG. 6B illustrates a method for decoding column addresses in accordance with one embodiment of the present invention. A module connector 602 (for example, the contact pins 402 and 416) sends signals to the CPLD 604, PLL 606, and register 608. The signals sent to CPLD 604 include CS0, CS1, Add(n−1), CAS, RAS, WE, CLK0, and CLK0_N. The signals sent to PLL 606 include CLK0, and CLK0_N. PLL relays CLK0 and CLK0_N signals to register 608 and memory devices 306. Register 608 also receives the following signals from module connector 602: Add[n;0], RAS, CAS, WE, BA[1:0], CKE.

As illustrated in the example above, the 512 Mbit memory devices has an extra column address line (A11) when compared to the 256 Mbit memory devices.

Register 608 of a four rank memory module emulating a two rank memory module receives an address with an address size matching the address size of the lower density memory devices (256 Mbit), i.e. A0-A12.

CPLD 604 also ensures that all commands for a two rank memory module conveyed by the module connector 602 are also performed on the four rank memory modules. For example, CPLD 604 generates rcs2 and rcs3, besides rcs0 and rcs1 off of CS0, CS1 and Add(n) from the memory controller side. CPLD 604 also generates rcs2 when CS0 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs2 when CS0 Auto Refresh Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Refresh Commands are issued. CPLD 604 also generates rcs2 when CS0 Load Mode Register Commands are issued. CPLD 604 also generates rcs3 when CS1 Load Mode Register Commands are issued.

It should be noted that the internal circuitry in the CPLD 410 for Row Address Decoding and Column Address Decoding are different. In particular, in the Column Address Decoding scheme, a unique decoding circuitry is required because in a standard DDR memory module there is only one set of address lines and memory organized as a matrix in such that in order to access an ×4, ×8 or ×16 cell, two set of addresses needs to be provided. First, the Row address needs to be provided with the proper control and command signals then on a separate cycle, the Column address needs to be provided with its proper control and command signals in order to read or write to that particular cell.

FIG. 7 illustrates a method for emulating a two rank memory module with a four rank memory module in accordance with one embodiment of the present invention. At 702, the memory module receives a command signal and address signal from a memory controller. The memory controller addressed the command signal and address signal to a two rank memory module. The command signal includes CS0, CS1, CKE, CAS, RAS, and WE. The address signal includes Add(n). At 704, the CPLD of the four rank memory module determines which rank should be active based on the address and command signals (cs0, cs1, and Add(n)). This determination was previously described using the truth table illustrated in FIG. 5. At 706, the CPLD performs either a Row Address Decoding scheme or a Column Address Decoding scheme as previously described to relay the command signals.

It should be noted that the physical address lines and logical address lines are different in this methodology. This is a non-linear addressing versus SRAM which uses linear addressing. In this methodology, a much lower number of pins are used to access the same amount of memory locations as a SRAM device with longer latency due to multiple cycle of providing the Row and Column logical addresses.

FIG. 8 is a block diagram schematically illustrating the internal circuitry of a CPLD used in the transparent four rank DDR memory module. CS0 signal and CS1 signal generate a CS internal signal through logical device 802. The CS signal is transmitted to Load mode register 804, auto refresh 806, and auto precharge detection 808 sub circuitries.

The Load Mode Register circuitry 804 also receives Chip Select (CS) signal, Row Address Strobe (RAS) signal, Column Address Strobe (CAS) signal, and Write Enable signal (WE). This module 804 detects load mode register cycle if inputs are asserted properly to indicate LMR command.

The Auto Refresh circuitry 806 receives Chip Select (CS) signal, Row Address Strobe (RAS) signal, Column Address Strobe (CAS) signal, and Write Enable signal (WE). This module 806 detects auto refresh cycle if inputs are asserted properly to indicate Auto Refresh command.

The Auto Precharge circuitry 808 receives Chip Select (CS) signal, Row Address Strobe (RAS) signal, Column Address Strobe (CAS) signal, and Write Enable (WE) signal. This module 808 detects auto precharge cycle if inputs are asserted properly to indicate auto precharge command.

The output of all three sub circuitries (LMR 804, auto refresh 806 and auto precharge 808) will go to a logical device OR 810 which will drive another level of OR logic 812 and 814 along with either highest address line (814) or it's inverted state (812).

The inverted state drives both MUX wcs0 and wcs1 blocks 816 and 818 which goes to a respective register 820 and 822 and gets fan-out into rcs0a and rcs0b or rcs1a or res1b eventually.

The non-inverted state will drive both MUX wcs2 and wcs3 blocks 824 and 826 which goes to a respective register 828 and 830 and gets fan-out into rcs2a and rcs2b or rcs3a or rcs3b eventually.

Many other families of memory devices or densities of memory devices (not shown) may be used to build the four rank memory module. Those of ordinary skill in the art will appreciate that the example of four rank memory module described above is not intended to be limiting and that other configuration can be used without departing from the inventive concepts herein disclosed.

While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art having the benefit of this disclosure that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Claims

1. A memory module connectable to a computer system, the memory module comprising: a board;a plurality of double-data-rate (DDR) memory devices mounted to the board, the plurality of DDR memory devices arranged in multiple ranks; anda circuit that includes an emulator and an input register, wherein the circuit is coupled to said board, and wherein the circuit receives from the computer system a set of input control signals that includes: a first chip select signal, a second chip select signal, an address signal, RAS, CAS, and WE;wherein the emulator receives from the computer system at least a portion of the set of input control signals that includes: RAS, CAS, WE, the first chip select signal, the second chip select signal, and a portion of the address signal;wherein the emulator includes a first output register coupled to a first rank;wherein the emulator includes a second output register coupled to a second rank;wherein the emulator includes a third output register coupled to a third rank;wherein the emulator includes a fourth output register coupled to a fourth rank;wherein the emulator includes command detection circuitry configured to, provide at least one command detection signal having a first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a command requiring selection of more than one rank of the multiple ranks, andprovide the at least one command detection signal having a second value indicating a command not requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a command not requiring selection of more than one rank of the multiple ranks;wherein the emulator includes logic circuitry responsive to the at least one command detection signal and to the portion of the address signal, configured to, provide at least one first selection signal having a value to indicate selection of the first and second chip select signals for provision to the first and second output registers, respectively, in response to the at least one command detection signal indicating a command requiring selection of more than one rank of the multiple ranks and in response to the portion of the address signal having a first logical value, andprovide at least one second selection signal having a value to indicate selection of the first and second chip select signals for provision to the third and fourth output registers, respectively, in response to the at least one command detection signal indicating a command requiring selection of more than one rank of the multiple ranks and in response to the portion of the address signal having a second logical value;wherein the emulator includes multiplex circuitry configured to, provide the first chip select signal to the first output register and to provide the second chip select signal to the second output register in response at least in part to the at least one first selection signal having the value to indicate selection of the first and second chip select signals for provision to the first and second output registers, andprovide the first chip select signal to the third output register and to provide the second chip select signal to the fourth output register in response at least in part to the at least one second selection signal having the value to indicate selection of the first and second chip select signals for provision to the third and fourth output registers;wherein the input register receives at least another portion of the set of input control signals that includes RAS, CAS, WE, and the remaining portion of the address signal; andwherein the input register provides one or more signals of the set of input control signals received by the input register to at least one of the plurality of DDR memory devices.

2. The memory module of claim 1, wherein the command detection circuitry is configured to provide the at least one command detection signal having the second value indicating a command not requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a read access operation or a write access operation.

3. The memory module of claim 2, wherein the received first and second chip select signals have opposite digital values during a read access operation and during a write access operation.

4. The memory module of claim 1, wherein the multiplex circuitry includes first multiplex circuitry configured to provide the first chip select signal to the first output register and to provide the second chip select signal to the second output register in response at least in part to the at least one first selection signal having the value to indicate selection of the first and second chip select signals for provision to the first and second output registers; andwherein the multiplex circuitry includes second multiplex circuitry configured to provide the first chip select signal to the third output register and to provide the second chip select signal to the fourth output register in response at least in part to the at least one second selection signal having the value to indicate selection of the first and second chip select signals for provision to the third and fourth output registers.

5. The memory module of claim 1, wherein the multiplex circuitry is configured to, select at least between providing a logic signal configured to have a value to not cause a selection of the first rank to the first output register and providing the first chip select signal to the first output register,select at least between providing the logic signal configured to have a value to not cause a selection of the second rank to the second output register and providing the second chip select signal to the second output register,select at least between providing the logic signal configured to have a value to not cause a selection of the third rank to the third output register and providing the first chip select signal to the third output register, andselect at least between providing the logic signal configured to have a value to not cause a selection of the fourth rank to the fourth output register and providing the second chip select signal to the fourth output register.

6. The memory module of claim 1, wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a refresh cycle.

7. The memory module of claim 6, wherein the command detection circuitry includes refresh cycle detection circuitry.

8. The memory module of claim 7, wherein the command detection circuitry includes logic circuitry configured to produce the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the refresh cycle detection circuitry detecting a refresh cycle.

9. The memory module of claim 1, wherein the command detection circuitry includes refresh cycle detection circuitry and wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the refresh cycle detection circuitry detecting a refresh cycle.

10. The memory module of claim 1, wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a precharge cycle.

11. The memory module of claim 10, wherein the command detection circuitry includes precharge cycle detection circuitry.

12. The memory module of claim 11, wherein the command detection circuitry includes logic circuitry configured to produce the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the precharge cycle detection circuitry detecting a precharge cycle.

13. The memory module of claim 1, wherein the command detection circuitry includes precharge cycle detection circuitry and wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the precharge cycle detection circuitry detecting a refresh cycle.

14. The memory module of claim 1, wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a load mode cycle.

15. The memory module of claim 14, wherein the command detection circuitry includes load mode cycle detection circuitry.

16. The memory module of claim 15, wherein the command detection circuitry includes logic circuitry configured to produce the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the load mode cycle detection circuitry detecting a load mode cycle.

17. The memory module of claim 1, wherein the command detection circuitry includes load mode cycle detection circuitry and wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the load mode cycle detection circuitry detecting a refresh cycle.

18. The memory module of claim 1, wherein the command detection circuitry is configured to provide the at least one command detection signal having the second value indicating a command not requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a read access operation or the write access operation; andwherein the command detection circuitry includes refresh cycle detection circuitry and wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the refresh cycle detection circuitry detecting a refresh cycle.

19. The memory module of claim 1, wherein the command detection circuitry is configured to provide the at least one command detection signal having the second value indicating a command not requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a read access operation or the write access operation; andwherein the command detection circuitry includes precharge cycle detection circuitry and wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the precharge cycle detection circuitry detecting a precharge cycle.

20. The memory module of claim 1, wherein the command detection circuitry is configured to provide the at least one command detection signal having the second value indicating a command not requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a read access operation or the write access operation; andwherein the command detection circuitry includes load mode cycle detection circuitry and wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the load mode cycle detection circuitry detecting a load mode cycle.

21. The memory module of claim 1, wherein the command detection circuitry is configured to provide the at least one command detection signal having the second value indicating a command not requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a read access operation or the write access operation; andwherein the command detection circuitry includes refresh cycle detection circuitry and includes precharge cycle detection circuitry and wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in response to the refresh cycle detection circuitry detecting a refresh cycle and in response to the precharge cycle detection circuitry detecting a precharge cycle.

22. The memory module of claim 1, wherein the command detection circuitry is configured to provide the at least one command detection signal having the second value indicating a command not requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a read access operation or the write access operation; andwherein the command detection circuitry includes refresh cycle detection circuitry and includes precharge cycle detection circuitry and includes load mode detection circuitry and wherein the command detection circuitry is configured to provide the at least one command detection signal having the first value indicating a command requiring selection of more than one rank of the multiple ranks, in to the refresh cycle detection circuitry detecting a refresh cycle and in response to the precharge cycle detection circuitry detecting a precharge cycle and in response to the load mode detection circuitry detecting a load mode cycle.

23. The memory module of claim 1, wherein the first logical value of the address signal has a value that is a logical complement of the second logical value.

24. A memory module connectable to a computer system, the memory module comprising: a board;a plurality of double-data-rate (DDR) memory devices mounted to the board, the plurality of DDR memory devices arranged in multiple ranks; anda circuit that includes an emulator and an input register, wherein the circuit is coupled to said board, and wherein the circuit receives from the computer system a set of input control signals that includes: a first chip select signal, a second chip select signal, an address signal, RAS, CAS, and WE;wherein the emulator receives from the computer system at least a portion of the set of input control signals that includes: RAS, CAS, WE, the first chip select signal, the second chip select signal, and the portion of the address signal;wherein the emulator includes a first output register coupled to a first rank;wherein the emulator includes a second output register coupled to a second rank;wherein the emulator includes a third output register coupled to a third rank;wherein the emulator includes a fourth output register coupled to a fourth rank;wherein the emulator includes means for providing an indication of detection of a command requiring selection of more than one rank of the multiple ranks, in response to the portion of the set of input control signals received by the emulator indicating a command requiring selection of more than one rank of the multiple ranks;wherein the emulator includes means responsive to an indication of detection of a command requiring selection of more than one rank of the multiple ranks and to the portion of the address signal, for providing an indication to select the first and second chip select signals for provision to the first and second output registers, respectively, in response to an indication of detection of a command requiring selection of more than one rank of the multiple ranks and in response to the portion of the address signal having a first logical value, andfor providing an indication to select the first and second chip select signals for provision to the third and fourth output registers, respectively, in response to an indication of detection of a command requiring selection of more than one rank of the multiple ranks and in response to the portion of the address signal having a second logical value;wherein the emulator includes multiplex circuitry configured to, provide the first chip select signal to the first output register and to provide the second chip select signal to the second output register in response at least in part to an indication to select the first and second chip select signals for provision to the first and second output registers, respectively, andprovide the first chip select signal to the third output register and to provide the second chip select signal to the fourth output register in response at least in part to an indication to select the first and second chip select signals for provision to the third and fourth output registers, respectively;wherein the input register receives at least another portion of the set of input control signals that includes RAS, CAS, WE, and the remaining portion of the address signal; andwherein the input register provides one or more signals of the set of input control signals received by the input register to at least one of the plurality of DDR memory devices.

25. The memory module of claim 24, wherein the means for providing an indication of detection of a command requiring selection of more than one rank of the multiple ranks includes means for detecting a refresh cycle in response to the portion of the set of input control signals received by the emulator indicating a refresh cycle.

26. The memory module of claim 24, wherein the means for providing an indication of detection of a command requiring selection of more than one rank of the multiple ranks includes means for detecting a precharge cycle in response to the portion of the set of input control signals received by the emulator indicating a precharge cycle.

27. The memory module of claim 24, wherein the means for providing an indication of detection of a command requiring selection of more than one rank of the multiple ranks includes means for detecting a load mode cycle in response to the portion of the set of input control signals received by the emulator indicating a load mode cycle.

28. The memory module of claim 24, wherein the means for providing an indication of detection of a command requiring selection of more than one rank of the multiple ranks includes, means for detecting a refresh cycle in response to the portion of the set of input control signals received by the emulator indicating a refresh cycle, andmeans for detecting a precharge cycle in response to the portion of the set of input control signals received by the emulator indicating a precharge cycle.

29. The memory module of claim 24, wherein the means for providing an indication of detection of a command requiring selection of more than one rank of the multiple ranks includes, means for detecting a refresh cycle in response to the portion of the set of input control signals received by the emulator indicating a refresh cycle,means for detecting a precharge cycle in response to the portion of the set of input control signals received by the emulator indicating a precharge cycle, andmeans for detecting a load mode cycle in response to the portion of the set of input control signals received by the emulator indicating a load mode cycle.