The present invention relates to computer memory. More particularly, the present invention relates to a four rank memory module.
Computers use memory devices for the storage and retrieval of information. These memory devices are often mounted on a memory module to expand the memory capacity of a computer. Sockets on a main board accommodate those memory modules also known as single inline memory modules (“SIMMs”) or dual in-line memory modules (“DIMMs”).
Standard memory modules such as memory module 106 have either one rank or two rank of memory devices. Each memory device comes in a variety of configurations and families such as 128 Mbit, 256 Mbit, 512 Mbit, and 1024 Mbit double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) families. Each of these families is further divided into three distinct flavors such as x4, x8, and x16 data bits. For example, a single 128 Mbit DDR SDRAM family comes in three flavors of:
32M×4 (32 Mega cell of 4-bit each=32M×4-bit=128 Mbit)
16M×8 (16 Mega cell of 8-bit each=16M×8-bit=128 Mbit)
8M×16 (8 Mega cell of 16-bit each=8M×16-bit=128 Mbit)
The example above illustrates that all three different data bits flavors result in the same density of 128 Mbit. As the number of data bits doubles the cell numbers decrease by half. One can build memory modules with similar densities using different data bits flavors.
One method of building a 512 M Byte standard memory module with error correction code (“ECC”) (64-bit data plus 8-bit ECC=72-bit) includes using 256 Mbit density families of 32M×8 to achieve the density of 512 M Byte as follow:
Rank 0=9×(32M×8) devices=32M×72-bit which equates to 32M×8 Bytes+1 Byte of ECC. This yields a total density of 32M×8 Bytes=256 M Byte.
Rank 1=9×(32M×8) devices=32M×72-bit which equates to 32M×8 Bytes+1 Byte of ECC. This yields a total density of 32M×8 Bytes=256 M Byte.
Therefore, a two rank memory module with 18 device placements will achieve the 512 M Byte density. Furthermore, it should be noted that a standard DDR 184-pin memory module can only fit nine thin shrink small outline package (“TSSOP”) placements per side, or a total of 18 placements of TSSOP per module, considering both front and back sides based on a standard defined height limits by Joint Electron Device Engineering Council (“JEDEC”).
Therefore, a two rank memory module with 18 device placements will achieve the 512M Byte density. Furthermore, it should be noted that a standard DDR 184-pin memory module can only fit nine TSSOP placements per side, or a total of 18 placements of TSSOP per module, considering both front and back sides based on a standard defined height limits by JEDEC.
Because memory devices with lower densities are cheaper and more readily available, it may be advantageous to build the above same density memory module using lower densities devices. However, in order to achieve a density of, for example, 512 M Bytes using 128 Mbit density of 16M×8 instead, the memory module needs four ranks configured as follows:
Rank 0=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.
Rank 1=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.
Rank 2=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.
Rank 3=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.
In order to achieve the above configuration, 4 rows of 9 devices each, totaling 36 placements, are required. As mentioned above, on a standard 184-pin DDR memory module, there is only enough space for 18 TSSOP devices.
The only solution would be, to stack two memory devices together to achieve an extra rank on the same placement space. Although this would solve the placement problem of 36 TSSOP devices, the memory module would still possess four memory ranks. As explained earlier, all standard memory modules have only two chip select signals per memory socket routed. Therefore, such memory module would not be viable.
A need therefore exists for a transparent four rank memory module fitting into a memory socket having two chip select signals routed. A primary purpose of the present invention is to solve these needs and provide further, related advantages.
A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.
The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present invention and, together with the detailed description, serve to explain the principles and implementations of the invention.
In the drawings:
Embodiments of the present invention are described herein in the context of a memory module. Those of ordinary skill in the art will realize that the following detailed description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.
In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.
In accordance with one embodiment of the present invention, the components, process steps, and/or data structures may be implemented using various types of operating systems (OS), computing platforms, firmware, computer programs, computer languages, and/or general-purpose machines. The method can be run as a programmed process running on processing circuitry. The processing circuitry can take the form of numerous combinations of processors and operating systems, or a stand-alone device. The process can be implemented as instructions executed by such hardware, hardware alone, or any combination thereof. The software may be stored on a program storage device readable by a machine.
In addition, those of ordinary skill in the art will recognize that devices of a less general purpose nature, such as hardwired devices, field programmable logic devices (FPLDs), including field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), application specific integrated circuits (ASICs), or the like, may also be used without departing from the scope and spirit of the inventive concepts disclosed herein.
The address bus 202 conveys the following signals: address[n:0] 210 and BA[1:0] 212.
The control bus 204 conveys the following signals: RAS 214, CAS 216, WE 218, DQM 220, CS[1:0] 222, and CKE[1:0] 224.
The data bus 206 conveys the following signals: data signals [7:0] 226 and DQS 228.
The differential clock bus 208 includes two signals: clk 230, and clk_n 232.
The memory module's back side 310 includes a second rank 312 of memory devices 306 (U10 through U18). The second rank 312 is stacked with a fourth rank 314 of memory devices 306 (U28 through U36). As illustrated in
The register 408 is used to synchronize the incoming address and control signals with respect to differential clock signals 208 (clk and clk_n). Also, the register 408 may eliminate the loading of 36 devices in case of stacking or loading of 18 devices in case of monolithic memory devices from the main controller by separating the controller side signaling with memory side signal loading fan-out.
The PLL 412 is used to generate a zero-delay buffer off of system side input differential clock signals 208 (clk and clk_n). By using a PLL, the system side will not see the loading effect of either 18 differential clock loads or 36 differentials clock loads in the case of stacking memory devices.
The SPD 414 is a simple I2C interface EEPROM to hold information regarding memory module for BIOS during the power-up sequence.
The CPLD 410 emulates a two rank memory module on the four rank memory module 400. CPLD 410 allows a system having a memory socket with only two chip select signals routed to interface with a four rank memory module where typically a two rank memory module couples with the memory socket. The CPLD 410 determines which rank from the four ranks to activate based upon the address and command signals from a memory controller coupled to the memory module 410. The algorithm of CPLD 410 is further described in
As illustrated in
Because the row address and column address may differ between different memory device densities, the CPLD may employ two different decoding schemes: a Row Address Decoding scheme, and a Column Address Decoding scheme. The following non-limiting example is used for illustration purposes.
A 512 MByte memory module may be build with either two rank of 256 MByte density per rank or four ranks of 128 MByte density per rank. However, a 128 Mbit DDR SDRAM has different characteristics from a 256 Mbit DDR SDRAM device.
A 128 Mbit DDR SDRAM (16M×8) has the following characteristics:
A 256 Mbit DDR SDRAM (32M×8) has the following characteristics:
The size of the column addresses (A0-A9) for both 128 Mbit DDR SDRAM and 256 Mbit DDR SDRAM devices match. However, the size of the row address for the 128 Mbit DDR SDRAM differs by one row address line from the 256 Mbit DDR SDRAM (A12). The CPLD 410 uses a Row Address Decoding scheme to emulate a two rank based on 256 Mbit DDR SDRAM Device Technology memory module with a four rank based on 128 Mbit DDR SDRAM Device Technology memory module. Under this scheme, address lines A0-A11 go to module register 408 and 418 and address lines A12 goes into CPLD 410 along with CS0 and CS1 for proper decoding. Therefore, the extra address line A12 is used by the CPLD to determine which rank (from the four ranks) is active. The decoding is performed as previously illustrated in
As illustrated in the example above, the 256 Mbit memory devices has an extra row address line (A12) when compared to the 128 Mbit memory devices. Register 608 of a four rank memory module emulating a two bank memory module receives an address with an address size matching the address size of the lower density memory devices (128 Mbit), i.e. A0-A11. In other words, the address signal from the module connector 608 does not include the extra row address line A12.
CPLD 604 also ensures that all commands for a two rank memory module conveyed by the module connector 602 are also performed on the four rank memory modules. For example, CPLD 604 generates rcs2 and rcs3, besides rcs0 and rcs1 off of CS0, CS1 and Add(n) from the memory controller side. CPLD 604 also generates rcs2 when CS0 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs2 when CS0 Auto Refresh Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Refresh Commands are issued. CPLD 604 also generates rcs2 when CS0 Load Mode Register Commands are issued. CPLD 604 also generates rcs3 when CS1 Load Mode Register Commands are issued.
However, as previously mentioned, a memory module may also be built using two device families which only differs in their column address size, and have the same row address size. The following example illustrates this situation and describes the Column Decoding Scheme.
A 1024 Mbyte memory module may be build with either two rank of 512 MByte density per rank or four ranks of 256 MByte density per rank. However, the 256 Mbit DDR SDRAM has different characteristics from a 512 Mbit DDR SDRAM.
A 256 Mbit DDR SDRAM (32M×8) has the following characteristics:
A 512 Mbit DDR SDRAM (64M×8) has the following characteristics:
The size of the row addresses (A0-A9) for both 256 Mbit DDR SDRAM and 512 Mbit DDR SDRAM devices match. However, the size of the column address for the 256 Mbit DDR SDRAM differ by one address line from the 512 Mbit DDR SDRAM (A11). The CPLD 410 uses the Column Address Decoding scheme to emulate a two ranks 512 Mbit based DDR SDRAM device Technology memory module with a four ranks 256 Mbit based DDR SDRAM device Technology memory module. Under this scheme, address lines A0-A12 go to module register 408 and 418 and address lines A11 goes into CPLD 410 along with CS0 and CS1 for proper decoding. Therefore, the address line A11 is used by the CPLD to determine which rank (from the four ranks) is active. The decoding is performed as previously illustrated in
As illustrated in the example above, the 512 Mbit memory devices has an extra column address line (A11) when compared to the 256 Mbit memory devices. Register 608 of a four rank memory module emulating a two rank memory module receives an address with an address size matching the address size of the lower density memory devices (256 Mbit), i.e. A0-A12.
CPLD 604 also ensures that all commands for a two rank memory module conveyed by the module connector 602 are also performed on the four rank memory modules. For example, CPLD 604 generates rcs2 and rcs3, besides rcs0 and rcs1 off of CS0, CS1 and Add(n) from the memory controller side. CPLD 604 also generates rcs2 when CS0 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs2 when CS0 Auto Refresh Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Refresh Commands are issued. CPLD 604 also generates rcs2 when CS0 Load Mode Register Commands are issued. CPLD 604 also generates rcs3 when CS1 Load Mode Register Commands are issued.
It should be noted that the internal circuitry in the CPLD 410 for Row Address Decoding and Column Address Decoding are different. In particular, in the Column Address Decoding scheme, a unique decoding circuitry is required because in a standard DDR memory module there is only one set of address lines and memory organized as a matrix in such that in order to access an x4, x8 or x16 cell, two set of addresses needs to be provided. First, the Row address needs to be provided with the proper control and command signals then on a separate cycle, the Column address needs to be provided with its proper control and command signals in order to read or write to that particular cell.
It should be noted that the physical address lines and logical address lines are different in this methodology. This is a non-linear addressing versus SRAM which uses linear addressing. In this methodology, a much lower number of pins are used to access the same amount of memory locations as a SRAM device with longer latency due to multiple cycle of providing the Row and Column logical addresses.
The Load Mode Register circuitry 804 also receives Chip Select (CS) signal, Row Address Strobe (RAS) signal, Column Address Strobe (CAS) signal, and Write Enable signal (WE). This module 804 detects load mode register cycle if inputs are asserted properly to indicate LMR command.
The Auto Refresh circuitry 806 receives Chip Select (CS) signal, Row Address Strobe (RAS) signal, Column Address Strobe (CAS) signal, and Write Enable signal (WE). This module 806 detects auto refresh cycle if inputs are asserted properly to indicate Auto Refresh command.
The Auto Precharge circuitry 808 receives Chip Select (CS) signal, Row Address Strobe (RAS) signal, Column Address Strobe (CAS) signal, and Write Enable (WE) signal. This module 808 detects auto precharge cycle if inputs are asserted properly to indicate auto precharge command.
The output of all three sub circuitries (LMR 804, auto refresh 806 and auto precharge 808) will go to a logical device OR 810 which will drive another level of OR logic 812 and 814 along with either highest address line (814) or it's inverted state (812).
The inverted state drives both MUX wcs0 and wcs1 blocks 816 and 818 which goes to a respective register 820 and 822 and gets fan-out into rcs0a and rcs0b or rcs1a or rcs1b eventually.
The non-inverted state will drive both MUX wcs2 and wcs3 blocks 824 and 826 which goes to a respective register 828 and 830 and gets fan-out into rcs2a and rcs2b or rcs3a or rcs3b eventually.
Many other families of memory devices or densities of memory devices (not shown) may be used to build the four rank memory module. Those of ordinary skill in the art will appreciate that the example of four rank memory module described above is not intended to be limiting and that other configuration can be used without departing from the inventive concepts herein disclosed.
While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art having the benefit of this disclosure that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
4368515 | Nielsen | Jan 1983 | A |
4392212 | Miyasaka et al. | Jul 1983 | A |
4633429 | Lewandowski et al. | Dec 1986 | A |
4670748 | Williams | Jun 1987 | A |
4866603 | Chiba | Sep 1989 | A |
4958322 | Kosugi et al. | Sep 1990 | A |
4961172 | Shubat et al. | Oct 1990 | A |
4980850 | Morgan | Dec 1990 | A |
5247643 | Shottan | Sep 1993 | A |
5345412 | Shiratsuchi | Sep 1994 | A |
5426753 | Moon | Jun 1995 | A |
5483497 | Mochizuki et al. | Jan 1996 | A |
5495435 | Sugahara | Feb 1996 | A |
5581498 | Ludwig et al. | Dec 1996 | A |
5590071 | Kolor et al. | Dec 1996 | A |
5699542 | Mehta et al. | Dec 1997 | A |
5702984 | Bertin et al. | Dec 1997 | A |
5703826 | Hush et al. | Dec 1997 | A |
5745914 | Connolly et al. | Apr 1998 | A |
5802395 | Connolly et al. | Sep 1998 | A |
5805520 | Anglada et al. | Sep 1998 | A |
5822251 | Bruce et al. | Oct 1998 | A |
RE36229 | Cady | Jun 1999 | E |
5926827 | Dell et al. | Jul 1999 | A |
5959930 | Sakurai | Sep 1999 | A |
5963464 | Dell et al. | Oct 1999 | A |
5966736 | Gittinger et al. | Oct 1999 | A |
6018787 | Ip et al. | Jan 2000 | A |
6044032 | Li et al. | Mar 2000 | A |
6070217 | Connolly et al. | May 2000 | A |
6070227 | Rokicki | May 2000 | A |
6097652 | Roh | Aug 2000 | A |
6108745 | Gupta et al. | Aug 2000 | A |
6134638 | Olarig et al. | Oct 2000 | A |
6151271 | Lee | Nov 2000 | A |
6154418 | Li | Nov 2000 | A |
6154419 | Shakkarwar | Nov 2000 | A |
6185654 | Van Doren | Feb 2001 | B1 |
6205516 | Usami | Mar 2001 | B1 |
6209074 | Dell et al. | Mar 2001 | B1 |
6226709 | Goodwin et al. | May 2001 | B1 |
6226736 | Niot | May 2001 | B1 |
6233650 | Johnson | May 2001 | B1 |
6247088 | Seo et al. | Jun 2001 | B1 |
6317352 | Halbert et al. | Nov 2001 | B1 |
6400637 | Akamatsu et al. | Jun 2002 | B1 |
6408356 | Dell | Jun 2002 | B1 |
6414868 | Wong et al. | Jul 2002 | B1 |
6415374 | Faue et al. | Jul 2002 | B1 |
6438062 | Curtis et al. | Aug 2002 | B1 |
6446158 | Karabatsos | Sep 2002 | B1 |
6446184 | Dell et al. | Sep 2002 | B2 |
6453381 | Yuan et al. | Sep 2002 | B1 |
6470417 | Kolor et al. | Oct 2002 | B1 |
6487102 | Halbert et al. | Nov 2002 | B1 |
6502161 | Perego et al. | Dec 2002 | B1 |
6518794 | Coteus et al. | Feb 2003 | B2 |
6526473 | Kim | Feb 2003 | B1 |
6530007 | Olarig et al. | Mar 2003 | B2 |
6530033 | Raynham et al. | Mar 2003 | B1 |
6553450 | Dodd et al. | Apr 2003 | B1 |
6618320 | Hasegawa et al. | Sep 2003 | B2 |
6621496 | Ryan | Sep 2003 | B1 |
6625081 | Roohparvar et al. | Sep 2003 | B2 |
6625687 | Halbert et al. | Sep 2003 | B1 |
6636935 | Ware et al. | Oct 2003 | B1 |
6639820 | Khandekar et al. | Oct 2003 | B1 |
6646949 | Ellis et al. | Nov 2003 | B1 |
6658509 | Bonella et al. | Dec 2003 | B1 |
6674684 | Shen | Jan 2004 | B1 |
6681301 | Mehta et al. | Jan 2004 | B1 |
6683372 | Wong et al. | Jan 2004 | B1 |
6697888 | Halbert et al. | Feb 2004 | B1 |
6705877 | Li et al. | Mar 2004 | B1 |
6717855 | Underwood et al. | Apr 2004 | B2 |
6738880 | Lai et al. | May 2004 | B2 |
6742098 | Halbert et al. | May 2004 | B1 |
6754797 | Wu et al. | Jun 2004 | B2 |
6785189 | Jacobs et al. | Aug 2004 | B2 |
6788592 | Nakata et al. | Sep 2004 | B2 |
6807125 | Coteus et al. | Oct 2004 | B2 |
6807650 | Lamb et al. | Oct 2004 | B2 |
6813196 | Park et al. | Nov 2004 | B2 |
6834014 | Yoo et al. | Dec 2004 | B2 |
6854042 | Karabatsos | Feb 2005 | B1 |
6880094 | LaBerge | Apr 2005 | B2 |
6889304 | Perego et al. | May 2005 | B2 |
6912615 | Nicolai | Jun 2005 | B2 |
6912628 | Wicki et al. | Jun 2005 | B2 |
6925028 | Hosokawa et al. | Aug 2005 | B2 |
6944694 | Pax | Sep 2005 | B2 |
6950366 | Lapidus et al. | Sep 2005 | B1 |
6961281 | Wong et al. | Nov 2005 | B2 |
6968440 | Brueggen | Nov 2005 | B2 |
6970968 | Holman | Nov 2005 | B1 |
6981089 | Dodd et al. | Dec 2005 | B2 |
6982892 | Lee et al. | Jan 2006 | B2 |
6982893 | Jakobs | Jan 2006 | B2 |
6990043 | Kuroda et al. | Jan 2006 | B2 |
6996686 | Doblar et al. | Feb 2006 | B2 |
7007130 | Holman | Feb 2006 | B1 |
7007175 | Chang et al. | Feb 2006 | B2 |
7046538 | Kinsley | May 2006 | B2 |
7054179 | Cogdill et al. | May 2006 | B2 |
7065626 | Schumacher et al. | Jun 2006 | B2 |
7073041 | Dwyer et al. | Jul 2006 | B2 |
7078793 | Ruckerbauer | Jul 2006 | B2 |
7120727 | Lee et al. | Oct 2006 | B2 |
7124260 | LaBerge et al. | Oct 2006 | B2 |
7127584 | Thompson et al. | Oct 2006 | B1 |
7130952 | Nanki et al. | Oct 2006 | B2 |
7133960 | Thompson et al. | Nov 2006 | B1 |
7133972 | Jeddeloh | Nov 2006 | B2 |
7142461 | Janzen | Nov 2006 | B2 |
7149841 | LaBerge | Dec 2006 | B2 |
7155627 | Matsui | Dec 2006 | B2 |
7167967 | Bungo et al. | Jan 2007 | B2 |
7181591 | Tsai et al. | Feb 2007 | B2 |
7200021 | Raghuram | Apr 2007 | B2 |
7227910 | Lipka | Jun 2007 | B2 |
7266634 | Ware et al. | Sep 2007 | B2 |
7266639 | Raghuram | Sep 2007 | B2 |
7272709 | Zitlaw et al. | Sep 2007 | B2 |
7281079 | Bains et al. | Oct 2007 | B2 |
7286436 | Bhakta et al. | Oct 2007 | B2 |
7289386 | Bhakta et al. | Oct 2007 | B2 |
7346750 | Ishikawa et al. | Mar 2008 | B2 |
7356639 | Perego et al. | Apr 2008 | B2 |
7363422 | Perego et al. | Apr 2008 | B2 |
7370238 | Billick et al. | May 2008 | B2 |
7437591 | Wong | Oct 2008 | B1 |
7461182 | Fukushima et al. | Dec 2008 | B2 |
7471538 | Hofstra | Dec 2008 | B2 |
7532537 | Solomon et al. | May 2009 | B2 |
7619912 | Bhakta et al. | Nov 2009 | B2 |
7636274 | Solomon et al. | Dec 2009 | B2 |
7864627 | Bhakta et al. | Jan 2011 | B2 |
7881150 | Solomon et al. | Feb 2011 | B2 |
20010003198 | Wu | Jun 2001 | A1 |
20010004753 | Dell et al. | Jun 2001 | A1 |
20010052057 | Lai et al. | Dec 2001 | A1 |
20020039323 | Tokutome et al. | Apr 2002 | A1 |
20020088633 | Kong et al. | Jul 2002 | A1 |
20030063514 | Faue | Apr 2003 | A1 |
20030090879 | Doblar et al. | May 2003 | A1 |
20030191995 | Abrosimov et al. | Oct 2003 | A1 |
20030210575 | Seo et al. | Nov 2003 | A1 |
20040037158 | Coteus et al. | Feb 2004 | A1 |
20040201968 | Tafolla | Oct 2004 | A1 |
20050036378 | Kawaguchi et al. | Feb 2005 | A1 |
20050138267 | Bains et al. | Jun 2005 | A1 |
20050281096 | Bhakta et al. | Dec 2005 | A1 |
20060044860 | Kinsley et al. | Mar 2006 | A1 |
20060117152 | Amidi et al. | Jun 2006 | A1 |
20060126369 | Raghuram | Jun 2006 | A1 |
20060129755 | Raghuram | Jun 2006 | A1 |
20060179206 | Brittain et al. | Aug 2006 | A1 |
20060267172 | Nguyen et al. | Nov 2006 | A1 |
20060277355 | Ellsberry et al. | Dec 2006 | A1 |
20100128507 | Solomon | May 2010 | A1 |
20110016250 | Lee et al. | Jan 2011 | A1 |
20110016269 | Lee et al. | Jan 2011 | A1 |
20110125966 | Amidi et al. | May 2011 | A1 |
Number | Date | Country |
---|---|---|
WO-9202879 | Feb 1992 | WO |
WO-9407242 | Mar 1994 | WO |
WO-9534030 | Dec 1995 | WO |
WO-02058069 | Jul 2002 | WO |
WO-03017283 | Feb 2003 | WO |
WO-03069484 | Aug 2003 | WO |
WO-2006055497 | May 2006 | WO |
Number | Date | Country | |
---|---|---|---|
20060117152 A1 | Jun 2006 | US |