Multi-rank memory module that emulates a memory module having a different number of ranks

Abstract

A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

Description

FIELD OF THE INVENTION

The present invention relates to computer memory. More particularly, the present invention relates to a four rank memory module.

BACKGROUND OF THE INVENTION

Computers use memory devices for the storage and retrieval of information. These memory devices are often mounted on a memory module to expand the memory capacity of a computer. Sockets on a main board accommodate those memory modules also known as SIMMs or DIMMs.

FIG. 1 is a diagram schematically illustrating a standard memory interface system overview in accordance with a prior art. The system 100 includes a processor 102, a memory controller 104, and a memory module 106. The processor 102 communicates with the memory controller 104 with an address bus 108, a control signal bus 110, and a data bus 112. The memory controller 104 communicates with the memory module 106 with a controller address bus 114, a controller control signal bus 116, and a controller data bus 118. Common system implementations 100 have typically two memory chip selects routed per socket. Common memory module 106 may have two chip selects (one per rank) or four chip selects (two per rank). In one implementation, each chip select from the controller is connected to the corresponding chip select on the memory module. In the second implementation, each chip select from the controller is connected to the two chip selects (those that control one rank) on the memory module. The system chip select signals control individual memory modules ranks. The memory module 106 is coupled to the memory controller 104 through a memory socket.

Standard memory modules such as memory module 106 have either one rank or two rank of memory devices. Each memory device comes in a variety of configurations and families such as 128 Mbit, 256 Mbit, 512 Mbit, and 1024 Mbit DDR SDRAM families. Each of these families is further divided into three distinct flavors such as ×4, ×8, and ×16 data bits. For example, a single 128 Mbit DDR SDRAM family comes in three flavors of:

32M×4 (32 Mega cell of 4-bit each=32M×4-bit=128 Mbit)

16M×8 (16 Mega cell of 8-bit each=16M×8-bit=128 Mbit)

8M×16 (8 Mega cell of 16-bit each=8M×16-bit=128 Mbit)

The example above illustrates that all three different data bits flavors result in the same density of 128 Mbit. As the number of data bits doubles the cell numbers decrease by half. One can build memory modules with similar densities using different data bits flavors.

One method of building a 512 M Byte standard memory module with ECC (64-bit data plus 8-bit ECC=72-bit) includes using 256 Mbit density families of 32M×8 to achieve the density of 512 M Byte as follow:

Rank 0=9×(32M×8) devices=32M×72-bit which equates to 32M×8 Bytes+1 Byte of ECC. This yields a total density of 32M×8 Bytes=256M Byte.

Rank 1=9×(32M×8) devices=32M×72-bit which equates to 32M×8 Bytes+1 Byte of ECC. This yields a total density of 32M×8 Bytes=256M Byte.

Therefore, a two rank memory module with 18 device placements will achieve the 512M Byte density. Furthermore, it should be noted that a standard DDR 184-pin memory module can only fit nine TSSOP placements per side, or a total of 18 placements of TSSOP per module, considering both front and back sides based on a standard defined height limits by JEDEC.

Because memory devices with lower densities are cheaper and more readily available, it may be advantageous to build the above same density memory module using lower densities devices. However, in order to achieve a density of, for example, 512 M Bytes using 128 Mbit density of 16M×8 instead, the memory module needs four ranks configured as follows:

Rank 0=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.

Rank 1=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.

Rank 2=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.

Rank 3=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.

In order to achieve the above configuration, 4 rows of 9 devices each, totaling 36 placements, are required. As mentioned above, on a standard 184-pin DDR memory module, there is only enough space for 18 TSSOP devices.

The only solution would be, to stack two memory devices together to achieve an extra rank on the same placement space. Although this would solve the placement problem of 36 TSSOP devices, the memory module would still possess four memory ranks. As explained earlier, all standard memory modules have only two chip select signals per memory socket routed. Therefore, such memory module would not be viable.

A need therefore exists for a transparent four rank memory module fitting into a memory socket having two chip select signals routed. A primary purpose of the present invention is to solve these needs and provide further, related advantages.

BRIEF DESCRIPTION OF THE INVENTION

A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present invention and, together with the detailed description, serve to explain the principles and implementations of the invention.

In the drawings:

FIG. 1 is a block diagram schematically illustrating a standard memory interface system in accordance with a prior art.

FIG. 2 is a diagram schematically illustrating a stacked DDR device in accordance with one embodiment of the present invention.

FIG. 3 is a diagram schematically illustrating a transparent four rank DDR memory module in accordance with one embodiment of the present invention.

FIG. 4A is a diagram schematically illustrating the front side of a transparent 72-bit registered DDR module in accordance with one embodiment of the present invention.

FIG. 4B is a diagram schematically illustrating the back side of a transparent 72-bit registered DDR module in accordance with one embodiment of the present invention.

FIG. 5 is a truth table for a transparent four rank memory module in accordance with one embodiment of the present invention.

FIG. 6A is a block diagram schematically illustrating a row address decoding system for a transparent four rank memory module in accordance with one embodiment of the present invention.

FIG. 6B is a block diagram schematically illustrating a column address decoding system for a transparent four rank memory module in accordance with one embodiment of the present invention.

FIG. 7 is a flow diagram schematically illustrating a method for emulating a two rank memory module.

FIG. 8 is a block diagram schematically illustrating a CPLD in a transparent four rank DDR memory module in accordance with one embodiment of the present invention

DETAILED DESCRIPTION

Embodiments of the present invention are described herein in the context of a memory module. Those of ordinary skill in the art will realize that the following detailed description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.

In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

In accordance with one embodiment of the present invention, the components, process steps, and/or data structures may be implemented using various types of operating systems (OS), computing platforms, firmware, computer programs, computer languages, and/or general-purpose machines. The method can be run as a programmed process running on processing circuitry. The processing circuitry can take the form of numerous combinations of processors and operating systems, or a stand-alone device. The process can be implemented as instructions executed by such hardware, hardware alone, or any combination thereof. The software may be stored on a program storage device readable by a machine.

In addition, those of ordinary skill in the art will recognize that devices of a less general purpose nature, such as hardwired devices, field programmable logic devices (FPLDs), including field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), application specific integrated circuits (ASICs), or the like, may also be used without departing from the scope and spirit of the inventive concepts disclosed herein.

FIG. 2 is a block diagram of an example of a standard stacked DDR 8 bit memory device 200 used in a memory module in accordance with one embodiment of the present invention. The memory device 200 interfaces with a memory controller (not shown) with three buses: an address bus 202, a control bus 204, and a data bus 206. A differential clock bus 208 is also coupled to the DDR memory device 200.

The address bus 202 conveys the following signals: address[n:0] 210 and BA[1:0] 212.

The control bus 204 conveys the following signals: RAS 214, CAS 216, WE 218, DQM 220, CS[1:0] 222, and CKE[1:0] 224.

The data bus 206 conveys the following signals: data signals [7:0] 226 and DQS 228.

The differential clock bus 208 includes two signals: clk 230, and clk_n 232.

FIG. 3 illustrates a block diagram of stacked 8 bit memory devices on the front and back side of a memory module 300 in accordance with one embodiment of the present invention. The memory module's front side 302 includes a first rank 304 of memory devices 306 (U1 through U9). The first rank 304 is stacked with a third rank 308 of memory devices 306 (U19 through U27). As illustrated in FIG. 3, data bus [7:0] is connected to both ranks' memory devices 306 (U1 and U19). The remaining data buses are connected to their respective ranks' memory devices 306. A chip select signal is coupled to each rank of memory devices. As illustrated in FIG. 3, chip select signal cs0 is connected to the first rank 304 (from U1 to U9) and chip select signal cs2 is connected to the third rank 308 (from U19 to U27).

The memory module's back side 310 includes a second rank 312 of memory devices 306 (U10 through U18). The second rank 312 is stacked with a fourth rank 314 of memory devices 306 (U28 through U36). As illustrated in FIG. 3, data bus [7;0] is connected to both ranks' memory devices 306 (U10 and U28). The remaining data buses are connected to their respective ranks' memory devices 306. A chip select signal is coupled to each rank of memory devices. As illustrated in FIG. 3, chip select signal cs1 is connected to the second rank 312 (from U10 to U18) and chip select signal cs3 is connected to the fourth rank 314 (from U28 to U36).

FIG. 3 also illustrates a total of four chip select signals (cs0, cs1, cs2, and cs3). As illustrated in FIG. 2, the stacked memory device 200 has only two chip select signals: cs[1:0] 222. In accordance with one embodiment of the invention, the present invention allows the four rank memory modules to communicate with a memory socket having only two chip select signals routed.

FIG. 4A illustrates a schematic diagram of the front side of a transparent 72 bit registered DDR module 400 in accordance with one embodiment of the present invention. The memory module 400 includes 92 contact pins 402 on the front side for connecting with a memory socket (not shown). The memory module 400 as illustrated in FIG. 4A includes nine 8 bit stacked memory devices 404, nine corresponding Resistor Network (Rn) 406, a register 408, a CPLD 410, a PLL 412, and a SPD 414. The stacking of the 8 bit stacked memory devices 404 was previously illustrated in FIG. 3. Memory devices 404 (U1 through U9) are mounted on a surface of the front side of the memory module 400. Memory devices 404 (U19 through U27) are respectively stacked on memory devices 404 (U1 through U9). Therefore the front side of the four rank memory modules 400 includes two ranks (rank 0 and rank 2).

The register 408 is used to synchronize the incoming address and control signals with respect to differential clock signals 208 (clk and clk_n). Also, the register 408 may eliminate the loading of 36 devices in case of stacking or loading of 18 devices in case of monolithic memory devices from the main controller by separating the controller side signaling with memory side signal loading fan-out.

The PLL 412 is used to generate a zero-delay buffer off of system side input differential clock signals 208 (clk and clk_n). By using a PLL, the system side will not see the loading effect of either 18 differential clock loads or 36 differentials clock loads in the case of stacking memory devices.

The SPD 414 is a simple I2C interface EEPROM to hold information regarding memory module for BIOS during the power-up sequence.

The CPLD 410 emulates a two rank memory module on the four rank memory module 400. CPLD 410 allows a system having a memory socket with only two chip select signals routed to interface with a four rank memory module where typically a two rank memory module couples with the memory socket. The CPLD 410 determines which rank from the four ranks to activate based upon the address and command signals from a memory controller coupled to the memory module 410. The algorithm of CPLD 410 is further described in FIGS. 5 and 7.

FIG. 4B illustrates a schematic diagram of the back side of the transparent 72 bit registered DDR module 400 in accordance with one embodiment of the present invention. The memory module 400 includes 92 contact pins 416 on the back side for connecting with a memory socket (not shown). Therefore, memory module 400 has a total of 184 different contact pins on the front and back side. The memory module 400 as illustrated in FIG. 4B includes nine 8 bit stacked memory devices 404, nine corresponding Resistor Network (Rn) 406, another register 418. The stacking of the 8 bit stacked memory devices 404 was previously illustrated in FIG. 3. Memory devices 404 (U10 through U18) are mounted on a surface of the back side of the memory module 400. Memory devices 404 (U28 through U36) are respectively stacked on memory devices 404 (U10 through U18). Therefore the back side of the four rank memory module 400 includes two ranks (rank 1 and rank 3).

FIG. 5 illustrates a truth table used in the process of the CPLD 410 to determine which rank is active (rank 0, rank 1, rank 2, or rank 3). CPLD 410 utilized three variables to determine the active rank: the highest address number Add(n), a first chip select signal (CS0), and a second chip select signal (CS1). As previously mentioned, each memory socket includes two active chip select signals (CS0 and CS1). CPLD 410 combines these two variables (CS0 and CS1) with the address number signal 210 from the address bus 202 to determine the active rank. Add(n) includes the highest binary digit from the address number signal 210. For example, the highest address number Add(n) when the address signal 210 is 10010 would be the first digit to the left: “1”.

As illustrated in FIG. 5, rank 0 is active when the Add(n) is 0, CS1 is 1, and CS0 is 0. Rank 1 is active when the Add(n) is 0, CS1 is 0, and CS0 is 1. Rank 2 is active when the Add(n) is 1, CS1 is 1, and CS0 is 0. Rank 3 is active when the Add(n) is 1, CS1 is 0, and CS0 is 1.

Because the row address and column address may differ between different memory device densities, the CPLD may employ two different decoding schemes: a Row Address Decoding scheme, and a Column Address Decoding scheme. The following non-limiting example is used for illustration purposes.

A 512 MByte memory module may be build with either two rank of 256 MByte density per rank or four ranks of 128 MByte density per rank. However, a 128 Mbit DDR SDRAM has different characteristics from a 256 Mbit DDR SDRAM device.

A 128 Mbit DDR SDRAM (16M×8) has the following characteristics:

Configuration  4M × 8 × 4
Refresh Rate   4K
Row Address    A0-A11
Column Address A0-A9

A 256 Mbit DDR SDRAM (32M×8) has the following characteristics:

Configuration  8M × 8 × 4
Refresh Rate   8K
Row Address    A0-A12
Column Address A0-A9

The size of the column addresses (A0-A9) for both 128 Mbit DDR SDRAM and 256 Mbit DDR SDRAM devices match. However, the size of the row address for the 128 Mbit DDR SDRAM differs by one row address line from the 256 Mbit DDR SDRAM (A12). The CPLD 410 uses a Row Address Decoding scheme to emulate a two rank based on 256 Mbit DDR SDRAM Device Technology memory module with a four rank based on 128 Mbit DDR SDRAM Device Technology memory module. Under this scheme, address lines A0-A11 go to module register 408 and 418 and address lines A12 goes into CPLD 410 along with CS0 and CS1 for proper decoding. Therefore, the extra address line A12 is used by the CPLD to determine which rank (from the four ranks) is active. The decoding is performed as previously illustrated in FIG. 5 above. For example, if address bus (A12-A0) has “1000010101010” and CS0 is “0” and CS1 is “1”, then rank 2 is activated. In this present example, Add(n) for A12 is “1”. The Row Address Decoding scheme is further illustrated in FIG. 6A.

FIG. 6A illustrates a method for decoding row addresses in accordance with one embodiment of the present invention. A module connector 602 (for example, the contact pins 402 and 416) sends signals to the CPLD 604, PLL 606, and register 608. The signals sent to CPLD 604 include cs0, cs1, Add(n), CAS, RAS, WE, CLK0, and CLK0_N. The signals sent to PLL 606 include CLK0, and CLK0_N. PLL relays the CLK0 and CLK0_N signals to register 608 and memory devices 306. Register 608 also receives the following signals from module connector 602: Add[n−1;0], RAS, CAS, WE, BA[1:0], CKE.

As illustrated in the example above, the 256 Mbit memory devices has an extra row address line (A12) when compared to the 128 Mbit memory devices. Register 608 of a four rank memory module emulating a two bank memory module receives an address with an address size matching the address size of the lower density memory devices (128 Mbit), i.e. A0-A11. In other words, the address signal from the module connector 608 does not include the extra row address line A12.

CPLD 604 also ensures that all commands for a two rank memory module conveyed by the module connector 602 are also performed on the four rank memory modules. For example, CPLD 604 generates rcs2 and rcs3, besides rcs0 and rcs1 off of CS0, CS1 and Add(n) from the memory controller side. CPLD 604 also generates rcs2 when CS0 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs2 when CS0 Auto Refresh Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Refresh Commands are issued. CPLD 604 also generates rcs2 when CS0 Load Mode Register Commands are issued. CPLD 604 also generates rcs3 when CS1 Load Mode Register Commands are issued.

However, as previously mentioned, a memory module may also be built using two device families which only differs in their column address size, and have the same row address size. The following example illustrates this situation and describes the Column Decoding Scheme.

A 1024 Mbyte memory module may be build with either two rank of 512 MByte density per rank or four ranks of 256 MByte density per rank. However, the 256 Mbit DDR SDRAM has different characteristics from a 512 Mbit DDR SDRAM.

A 256 Mbit DDR SDRAM (32M×8) has the following characteristics:

Configuration  8M × 8 × 4
Refresh Rate   8K
Row Address    A0-A12
Column Address A0-A9

A 512 Mbit DDR SDRAM (64M×8) has the following characteristics:

Configuration  16M × 8 × 4
Refresh Rate   8K
Row Address    A0-A12
Column Address A0-A9, A11

The size of the row addresses (A0-A9) for both 256 Mbit DDR SDRAM and 512 Mbit DDR SDRAM devices match. However, the size of the column address for the 256 Mbit DDR SDRAM differ by one address line from the 512 Mbit DDR SDRAM (A11). The CPLD 410 uses the Column Address Decoding scheme to emulate a two ranks 512 Mbit based DDR SDRAM device Technology memory module with a four ranks 256 Mbit based DDR SDRAM device Technology memory module. Under this scheme, address lines A0-A12 go to module register 408 and 418 and address lines A11 goes into CPLD 410 along with CS0 and CS1 for proper decoding. Therefore, the address line A11 is used by the CPLD to determine which rank (from the four ranks) is active. The decoding is performed as previously illustrated in FIG. 5 above. For example, if address bus (A11, A9-A0) has “100110101010” and CS0 is “0” and CS1 is “1”, then rank 2 is activated. In this present example, Add(n) for A11 is “1”. The Column Address Decoding scheme is further illustrated in FIG. 6B.

FIG. 6B illustrates a method for decoding column addresses in accordance with one embodiment of the present invention. A module connector 602 (for example, the contact pins 402 and 416) sends signals to the CPLD 604, PLL 606, and register 608. The signals sent to CPLD 604 include CS0, CS1, Add(n−1), CAS, RAS, WE, CLK0, and CLK0_N. The signals sent to PLL 606 include CLK0, and CLK0_N. PLL relays CLK0 and CLK0_N signals to register 608 and memory devices 306. Register 608 also receives the following signals from module connector 602: Add[n;0], RAS, CAS, WE, BA[1:0], CKE.

As illustrated in the example above, the 512 Mbit memory devices has an extra column address line (A11) when compared to the 256 Mbit memory devices. Register 608 of a four rank memory module emulating a two rank memory module receives an address with an address size matching the address size of the lower density memory devices (256 Mbit), i.e. A0-A12.

CPLD 604 also ensures that all commands for a two rank memory module conveyed by the module connector 602 are also performed on the four rank memory modules. For example, CPLD 604 generates rcs2 and rcs3, besides rcs0 and rcs1 off of CS0, CS1 and Add(n) from the memory controller side. CPLD 604 also generates rcs2 when CS0 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Precharge all Banks Commands are issued. CPLD 604 also generates rcs2 when CS0 Auto Refresh Commands are issued. CPLD 604 also generates rcs3 when CS1 Auto Refresh Commands are issued. CPLD 604 also generates rcs2 when CS0 Load Mode Register Commands are issued. CPLD 604 also generates rcs3 when CS1 Load Mode Register Commands are issued.

It should be noted that the internal circuitry in the CPLD 410 for Row Address Decoding and Column Address Decoding are different. In particular, in the Column Address Decoding scheme, a unique decoding circuitry is required because in a standard DDR memory module there is only one set of address lines and memory organized as a matrix in such that in order to access an ×4, ×8 or ×16 cell, two set of addresses needs to be provided. First, the Row address needs to be provided with the proper control and command signals then on a separate cycle, the Column address needs to be provided with its proper control and command signals in order to read or write to that particular cell.

FIG. 7 illustrates a method for emulating a two rank memory module with a four rank memory module in accordance with one embodiment of the present invention. At 702, the memory module receives a command signal and address signal from a memory controller. The memory controller addressed the command signal and address signal to a two rank memory module. The command signal includes CS0, CS1, CKE, CAS, RAS, and WE. The address signal includes Add(n). At 704, the CPLD of the four rank memory module determines which rank should be active based on the address and command signals (cs0, cs1, and Add(n)). This determination was previously described using the truth table illustrated in FIG. 5. At 706, the CPLD performs either a Row Address Decoding scheme or a Column Address Decoding scheme as previously described to relay the command signals.

It should be noted that the physical address lines and logical address lines are different in this methodology. This is a non-linear addressing versus SRAM which uses linear addressing. In this methodology, a much lower number of pins are used to access the same amount of memory locations as a SRAM device with longer latency due to multiple cycle of providing the Row and Column logical addresses.

FIG. 8 is a block diagram schematically illustrating the internal circuitry of a CPLD used in the transparent four rank DDR memory module. CS0 signal and CS1 signal generate a CS internal signal through logical device 802. The CS signal is transmitted to Load mode register 804, auto refresh 806, and auto precharge detection 808 sub circuitries.

The Load Mode Register circuitry 804 also receives Chip Select (CS) signal, Row Address Strobe (RAS) signal, Column Address Strobe (CAS) signal, and Write Enable signal (WE). This module 804 detects load mode register cycle if inputs are asserted properly to indicate LMR command.

The Auto Refresh circuitry 806 receives Chip Select (CS) signal, Row Address Strobe (RAS) signal, Column Address Strobe (CAS) signal, and Write Enable signal (WE). This module 806 detects auto refresh cycle if inputs are asserted properly to indicate Auto Refresh command.

The Auto Precharge circuitry 808 receives Chip Select (CS) signal, Row Address Strobe (RAS) signal, Column Address Strobe (CAS) signal, and Write Enable (WE) signal. This module 808 detects auto precharge cycle if inputs are asserted properly to indicate auto precharge command.

The output of all three sub circuitries (LMR 804, auto refresh 806 and auto precharge 808) will go to a logical device OR 810 which will drive another level of OR logic 812 and 814 along with either highest address line (814) or it's inverted state (812).

The inverted state drives both MUX wcs0 and wcs1 blocks 816 and 818 which goes to a respective register 820 and 822 and gets fan-out into rcs0 a and rcs0b or rcs1a or rcs1b eventually.

The non-inverted state will drive both MUX wcs2 and wcs3 blocks 824 and 826 which goes to a respective register 828 and 830 and gets fan-out into rcs2a and rcs2b or rcs3a or rcs3b eventually.

Many other families of memory devices or densities of memory devices (not shown) may be used to build the four rank memory module. Those of ordinary skill in the art will appreciate that the example of four rank memory module described above is not intended to be limiting and that other configuration can be used without departing from the inventive concepts herein disclosed.

While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art having the benefit of this disclosure that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Claims

1. A memory module connectable to a computer system, the memory module comprising: a printed circuit board;a plurality of double-data-rate (DDR) memory devices mounted to the printed circuit board, the plurality of DDR memory devices having a first number of DDR memory devices arranged in a first number of ranks;a circuit mounted to the printed circuit board, the circuit comprising a logic element and a register, the logic element receiving a set of input control signals from the computer system, the set of input control signals comprising at least one row/column address signal, and at least one chip-select signal, the set of input control signals corresponding to a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of DDR memory devices and the second number of ranks less than the first number of ranks, the circuit generating a set of output control signals in response to the set of input control signals, the set of output control signals corresponding to the first number of DDR memory devices arranged in the first number of ranks, wherein the circuit further responds to a first command signal and the set of input control signals from the computer system by generating and transmitting a second command signal and the set of output control signals to the plurality of memory devices, the first command signal and the set of input control signals corresponding to the second number of ranks and the second command signal and the set of output control signals corresponding to the first number of ranks; and a phase-lock loop device mounted to the printed circuit board, the phase-lock loop device operatively coupled to the plurality of DDR memory devices, and the register;wherein the circuit is configured to store an input control signal of the set of input control signals during a row access procedure and to transmit the stored input control signal as an output control signal of the set of output control signals during a column access procedure.

2. The memory module of claim 1, wherein the set of input control signals comprises a first number of chip-select signals and wherein the set of output control signals comprises a second number of chip-select signals greater than the first number of chip-select signals.

3. The memory module of claim 2, wherein the first number of chip-select signals is two and the second number of chip-select signals is four.

4. A memory module connectable to a computer system, the memory module comprising: a printed circuit board;a plurality of double-data-rate (DDR) memory devices mounted to the printed circuit board, the plurality of DDR memory devices having a first number of DDR memory devices arranged in a first number of ranks;a circuit mounted to the printed circuit board, the circuit comprising a logic element and a register, the logic element receiving a set of input control signals from the computer system, the set of input control signals comprising at least one row/column address signal, and at least one chip-select signal, the set of input control signals corresponding to a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of DDR memory devices and the second number of ranks less than the first number of ranks, the circuit generating a set of output control signals in response to the set of input control signals, the set of output control signals corresponding to the first number of DDR memory devices arranged in the first number of ranks, wherein the circuit further responds to a first command signal and the set of input control signals from the computer system by generating and transmitting a second command signal and the set of output control signals to the plurality of memory devices, the first command signal and the set of input control signals corresponding to the second number of ranks and the second command signal and the set of output control signals corresponding to the first number of ranks; and a phase-lock loop device mounted to the printed circuit board, the phase-lock loop device operatively coupled to the plurality of DDR memory devices, and the register;wherein the circuit receives and buffers a plurality of row/column address signals of the input control signals during a row access procedure and sends the buffered plurality of row/column address signals to the plurality of DDR memory devices during a subsequent column access procedure.

5. The memory module of claim 1, wherein the logic element comprises an application-specific integrated circuit, a field-programmable gate array, a custom-designed semiconductor device, or a complex programmable-logic device.

6. The memory module of claim 1, wherein the address signals of the set of input control signals are received by both the logic element and the register.

7. The memory module of claim 1, wherein the plurality of DDR memory devices is arranged as a first set of DDR memory devices on a first side of the printed circuit board, a second set of DDR memory devices on the first side of the printed circuit board, a third set of DDR memory devices on a second side of the printed circuit board, and a fourth set of DDR memory devices on the second side of the printed circuit board, the DDR memory devices of the second set spaced from the DDR memory devices of the first set, the DDR memory devices of the fourth set spaced from the DDR memory devices of the third set.

8. The memory module of claim 1, wherein the set of input control signals corresponds to a first memory density, and the set of output control signals corresponds to a second memory density, the second memory density greater than the first memory density.

9. A memory module connectable to a computer system, the memory module comprising: a printed circuit board;a plurality of double-data-rate (DDR) memory devices coupled to the printed circuit board, the plurality of DDR memory devices having a first number of DDR memory devices arranged in a first number of ranks;a circuit coupled to the printed circuit board, the circuit comprising a logic element and a register, the logic element receiving a set of input signals from the computer system, the set of input signals comprising at least one row/column address signal, and at least one chip-select signal, the set of input signals configured to control a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of DDR memory devices and the second number of ranks less than the first number of ranks, the circuit generating a set of output signals in response to the set of input signals, the set of output signals configured to control the first number of DDR memory devices arranged in the first number of ranks,wherein the circuit further responds to a command signal and the set of input signals from the computer system by selecting at least one rank of the first number of ranks and transmitting the command signal to at least one DDR memory device of the selected at least one rank of the first number of ranks; and a phase-lock loop device coupled to the printed circuit board, the phase-lock loop device operatively coupled to the plurality of DDR memory devices and the register; andwherein the circuit is configured to store an input signal of the set of input signals during a row access procedure and to transmit the stored input signal as an output signal of the set of output signals during a subsequent column access procedure.

10. The memory module of claim 9, wherein the command signal is transmitted to two ranks of the first number of ranks at a time.

11. The memory module of claim 10, wherein the command signal comprises a refresh command signal.

12. The memory module of claim 10, wherein the command signal is transmitted to the two ranks of the first number of ranks concurrently.

13. The memory module of claim 9, wherein the circuit is configured to store an input signal of the set of input signals during a row access procedure for subsequent use during a column access procedure.

14. The memory module of claim 9, wherein the command signal comprises a read command signal or a write command signal, the set of input signals comprises a density bit which is a row address bit, and the circuit is configured to store the row address bit during an activate command for a selected rank.

15. The memory module of claim 9, wherein the logic element comprises an application-specific integrated circuit, a field-programmable gate array, a custom-designed semiconductor device, or a complex programmable-logic device.

16. The memory module of claim 9, wherein the set of input signals comprises a plurality of row/column address signals received and buffered by the register and sent from the register to the plurality of DDR memory devices.

17. The memory module of claim 16, wherein the logic element receives address signals and the command signal from the computer system and the register receives the address signals and the command signal from the computer system.

18. A memory module connectable to a computer system, the memory module comprising: a printed circuit board;a plurality of double-data-rate (DDR) dynamic random-access memory (DRAM) devices coupled to the printed circuit board, the plurality of DDR DRAM devices having a first number of DDR DRAM devices arranged in a first number of ranks;a circuit coupled to the printed circuit board, the circuit comprising a logic element and a register, the logic element receiving a set of input control signals from the computer system, the set of input control signals comprising a row/column address signal, a chip-select signal, and an input command signal, the set of input control signals configured to control a second number of DDR DRAM devices arranged in a second number of ranks, the second number of DDR DRAM devices smaller than the first number of DDR DRAM devices, the second number of ranks smaller than the first number of ranks, the circuit generating a set of output control signals in response to the set of input control signals, the set of output control signals comprising an output command signal, the set of output control signals configured to control the first number of DDR DRAM devices arranged in the first number of ranks, wherein the circuit further responds to the set of input control signals from the computer system by selecting at least one rank of the first number of ranks and transmitting the set of output control signals to at least one DDR DRAM device of the selected at least one rank; anda phase-lock loop device coupled to the printed circuit board, the phase-lock loop device operatively coupled to the plurality of DDR DRAM devices, and the register;wherein the first number of ranks is four and the second number of ranks is two.

19. The memory module of claim 18, wherein the logic element comprises an application-specific integrated circuit, a field-programmable gate array, a custom-designed semiconductor device, or a complex programmable-logic device.

20. The memory module of claim 18, wherein the set of input control signals comprises fewer chip-select signals than does the set of output control signals.

21. The memory module of claim 20, wherein the set of input control signals comprises two chip-select signals and the set of output control signals comprises four chip-select signals.

22. The memory module of claim 18, wherein the register receives the address signals and the input command signal of the set of input control signals.

23. The memory module of claim 18, wherein the input command signal is a refresh signal and the output command signal is a refresh signal.

24. The memory module of claim 18, wherein the input command signal is a precharge signal and the output command signal is a precharge signal.

25. A memory module connectable to a computer system, the memory module comprising: a printed circuit board;a plurality of double-data-rate (DDR) dynamic random-access memory (DRAM) devices coupled to the printed circuit board, the plurality of DDR DRAM devices having a first number of DDR DRAM devices arranged in a first number of ranks;a circuit coupled to the printed circuit board, the circuit comprising a logic element and a register, the logic element receiving a set of input control signals from the computer system, the set of input control signals comprising a row/column address signal, a chip-select signal, and an input command signal, the set of input control signals configured to control a second number of DDR DRAM devices arranged in a second number of ranks, the second number of DDR DRAM devices smaller than the first number of DDR DRAM devices, the second number of ranks smaller than the first number of ranks, the circuit generating a set of output control signals in response to the set of input control signals, the set of output control signals comprising an output command signal, the set of output control signals configured to control the first number of DDR DRAM devices arranged in the first number of ranks, wherein the circuit further responds to the set of input control signals from the computer system by selecting at least one rank of the first number of ranks and transmitting the set of output control signals to at least one DDR DRAM device of the selected at least one rank; anda phase-lock loop device coupled to the printed circuit board, the phase-lock loop device operatively coupled to the plurality of DDR DRAM devices, and the register;wherein the circuit is configured to store an input control signal of the set of input control signals during a row access procedure and to transmit the stored input control signal as an output control signal of the set of output control signals during a column access procedure.

26. A memory module connectable to a computer system, the memory module comprising: a printed circuit board having a first side and a second side;a plurality of double-data-rate (DDR) memory devices mounted to the printed circuit board, the plurality of DDR memory devices arranged in two or more ranks which are selectable by a first number of chip-select signals; anda circuit mounted to the printed circuit board, the circuit comprising a logic element, a register, and a phase-lock loop device operationally coupled to the plurality of DDR memory devices and the register, the circuit receiving a plurality of input signals from the computer system, the plurality of input signals comprising row address signals, column address signals, command signals, and a second number of chip-select signals less than the first number of chip-select signals,wherein the logic element receives an address signal and at least one command signal of the plurality of input signals, the circuit element generating a plurality of output signals in response to the plurality of input signals, the plurality of output signals comprising row address signals, column address signals, command signals, and the first number of chip-select signals, the circuit further responsive to the plurality of input signals by selecting at least one rank of the two or more ranks and transmitting the plurality of output signals to at least one DDR memory device of the selected at least one rank; andwherein the plurality of input signals corresponds to a first memory density, and the plurality of output signals corresponds to a second memory density, the second memory density greater than the first memory density.

27. The memory module of claim 26, wherein the circuit comprises one or more integrated circuit elements selected from the group consisting of: an application-specific integrated circuit, a field-programmable gate array, a custom-designed semiconductor device, and a complex programmable-logic device.

28. The memory module of claim 26, wherein the row address signals and the column address signals of the plurality of input signals are received and buffered by the register and are sent from the register to the plurality of DDR memory devices.

29. The memory module of claim 28, wherein the logic element receives the second number of chip-select signals.

30. The memory module of claim 29, wherein both the register and the logic element receive address signals and at least one command signal of the plurality of input signals.

31. The memory module of claim 26, wherein the circuit is configured to respond to the plurality of input signals by selecting at least one rank of the two or more ranks and transmitting a command signal to at least one DDR memory device of the selected at least one rank.

32. The memory module of claim 26, wherein the circuit is configured to store a signal of the plurality of input signals during a row access procedure and to transmit the stored signal as an output signal of the plurality of output signals during a column access procedure.

33. A memory module connectable to a computer system, the memory module comprising: a printed circuit board having a first side and a second side;a plurality of double-data-rate (DDR) memory devices mounted to the printed circuit board, the plurality of DDR memory devices arranged in two or more ranks which are selectable by a first number of chip-select signals; anda circuit mounted to the printed circuit board, the circuit comprising a logic element, a register, and a phase-lock loop device operationally coupled to the plurality of DDR memory devices and the register, the circuit receiving a plurality of input signals from the computer system, the plurality of input signals comprising row address signals, column address signals, command signals, and a second number of chip-select signals less than the first number of chip-select signals,wherein the logic element receives an address signal and at least one command signal of the plurality of input signals, the circuit element generating a plurality of output signals in response to the plurality of input signals, the plurality of output signals comprising row address signals, column address signals, command signals, and the first number of chip-select signals, the circuit further responsive to the plurality of input signals by selecting at least one rank of the two or more ranks and transmitting the plurality of output signals to at least one DDR memory device of the selected at least one rank;wherein the plurality of output signals corresponds to a first number of DDR memory devices arranged in the two or more ranks which are selectable by the first number of chip-select signals and wherein the plurality of input signals corresponds to a second number of DDR memory devices arranged in ranks which are selectable by the second number of chip-select signals, wherein the memory module simulates a virtual memory module having the second number of DDR memory devices.