Patent Application
20130336051
The present application relates to systems, devices and methods for startup operations involving multi-bit phase change memory units.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
Phase change memory (“PCM”) is a relatively new nonvolatile memory technology, which is very different from any other kind of nonvolatile memory. First, the fundamental principles of operation, at the smallest scale, are different: no other kind of solid-state memory uses a reversible PHYSICAL change to store data. Second, in order to achieve that permanent physical change, an array of PCM cells has to allow read, set, and reset operations which are all very different from each other. The electrical requirements of the read, set, and reset operations make the peripheral circuit operations of a PCM very different from those of other nonvolatile memories. Obviously some functions, such address decoding and bus interface, can be the same; but the closest-in parts of the periphery, which perform set, reset, and read operations on an array or subarray, must satisfy some unique requirements.
The physical state of a PCM cell's memory material is detected as resistance. For each selected cell, its bitline is set to a known voltage, and the cell's access transistor is turned on (by the appropriate wordline). If the cell is in its low-resistance state, it will sink a significant current from the bit line; if it is not, it will not.
Set and Reset operations are more complicated. Both involve heat. As discussed below, a “set” operation induces the memory material to recrystallize into its low-resistance (polycrystalline) state; a “reset” operation anneals the memory material into its high-resistance (amorphous) state.
Write operations (Set and Reset) normally have more time budget than read operations. In read mode a commercial PCM memory should be competitive with the access speed (and latency if possible) of a standard DRAM. If this degree of read speed can be achieved, PCM becomes very attractive for many applications.
The phase change material is typically a chalcogenide glass, using amorphous and crystalline (or polycrystalline) phase states to represent bit states.
A complete PCM cell can include, for example: a top electrode (connected to the bit line), a phase change material (e.g. a chalcogenide glass), a conductive pillar which reaches down from the bottom of the phase change material, an access transistor (gated by a word line), and a bottom connection to ground. The phase change material can extend over multiple cells (or over the whole array), but the access transistors are laterally isolated from each other by a dielectric.
A conductive pillar 2050 connects the material 2030 to a bottom electrode 2040. In this example, no selection device is shown; in practice, an access transistor would normally be connected in series with the phase change material. The pillar 2050 is embedded in an insulator layer 2060.
When voltage is applied between the top 2020 and bottom 2040 electrodes, the voltage drop will appear across the high-resistivity zone 2070 (if present). If sufficient voltage is applied, breakdown will occur across the high-resistivity zone. In this state the material will become very conductive, with large populations of mobile carriers. The material will therefore pass current, and current crowding can occur near the top of the pillar 2050. The voltage which initiates this conduction is referred to as the “snapback” voltage, and
In the zone 2200 marked “READ,” the device will act either as a resistor or as an open (perhaps with some leakage). A small applied voltage will result in a state-dependent difference in current, which can be detected.
However, the curve with open circles, corresponding to the amorphous state of the device, shows some more complex behaviors. The two curves show behaviors under conditions of higher voltage and higher current.
If the voltage reaches the threshold voltage Vth, current increases dramatically without any increase in voltage. (This occurs when breakdown occurs, so the phase-change material suddenly has a large population of mobile carriers.) Further increases in applied voltage above Vth result in further increases in current; note that this upper branch of the curve with hollow circles shows a lower resistance than the curve with solid squares.
If the applied voltage is stepped up to reach the zone 2150, the behavior of the cell is now independent of its previous state.
When relatively large currents are applied, localized heating will occur at the top of the pillar 2050, due to the relatively high current density. Current densities with typical dimensions can be in the range of tens of millions of Amperes per square cm. This is enough to produce significant localized heating within the phase-change material.
This localized heating is used to change the state of the phase-change material, as shown in
In a single-bit PCM, as described above, only two phases are distinguished: either the cell does or does not have a significant high-resistivity “mushroom cap” 2070. However, it is also possible to distinguish between different states of the mushroom cap 2070, and thereby store more than one bit per cell.
For example, other PCM material compositions may display variation of the set resistance over time.
The downwards drift of reset resistance may be due to, for example, shrinking size of the amorphous zone of the phase-change material, due to crystal growth; and, in some cells, spontaneous nucleation steepening the drift curve (possibly only slightly) due to introducing further conductive elements into the mushroom-shaped programmable region.
A variety of nonvolatile memory technologies have been proposed over recent decades, and many of them have required some engineering to provide reference values for sensing. However, the requirements and constraints of phase-change memory are fundamentally different from those of any other kind of nonvolatile memory. Many memory technologies (such as EEPROM, EPROM, MNOS, and flash) test the threshold voltage of the transistor in a selected cell, so referencing must allow for the transistor's behavior. By contrast, phase-change memory simply senses the resistance of the selected cell. This avoids the complexities of providing a reference which will distinguish two (or more) possibilities for an active device's state, but does require detecting a resistance value, and tracking external variations (e.g. temperature and supply voltage) which may affect the instantaneous value of that resistance.
The possibility of storing more than one bit of data in a single phase-change material has also been suggested. Phase-change memories implementing such architectures are referred to here as “multibit” PCMs. If the “Set” and/or “Reset” operations can be controlled to produce multiple electrically distinguishable states, then more than one bit of information can be stored in each phase-change material location. It is known that the current over time profile of the Set operation can be controlled to produce electrically distinguishable results, though this can be due to more than one effect. In the simplest implementation, shorter anneals—too short to produce full annealing of the amorphous layer—can be used to produce one or more intermediate states. In some materials, different crystalline phases can also be produced by appropriate selection of the current over time profile. However, what is important for the present application is merely that electrically distinguishable states can be produced.
For example, if the complete layer of phase-change material can have four possible I/V characteristics, two bits of information can be stored in each cell—IF the read cycle can accurately distinguish among the four different states.
(The I/V characteristics of the cells which are not in the fully Set state are typically nonlinear, so it is more accurate to distinguish the states in terms of current flow at a given voltage; resistance is often used as a shorthand term, but implies a linearity which may not be present.)
In order to make use of the possible multibit cell structures, it is necessary to reliably distinguish among the possible states. To make this distinction reliably, there must be some margin of safety, despite the change in characteristics which may occur due to history, manufacturing tolerances, and environmental factors. Thus the read architecture of multibit PCMs is a far more difficult challenge it is for PCMs with single-bit cells.
The present application discloses surprising new approaches to systems in which multi-bit PCM is used, as well as methods for operating such systems. One example of systems using multi-bit PCM is memory incorporating multi-bit PCM. At power-up, test reads of multi-bit PCM memory elements with known states are used to determine whether instantaneous supply voltage levels permit multi-bit PCM to be reliably read.
The disclosed inventions will be described with reference to the accompanying drawings, which show important sample embodiments and which are incorporated in the specification hereof by reference, wherein:
The numerous innovative teachings of the present application will be described with particular reference to presently preferred embodiments (by way of example, and not of limitation). The present application describes several inventions, and none of the statements below should be taken as limiting the claims generally.
Multi-bit PCM can be used to make high-density non-volatile RAM memory (multi-bit PCRAM) in a variety of interfaces. It is advantageous to use multi-bit PCM as non-volatile redundancy memory for multi-bit PCRAM to store redundancy information to route around multi-bit PCRAM manufacturing defects; or as non-volatile repair memory to store repair, test, trim or configuration information to tune multi-bit PCRAM and other component (e.g., processor, input/output controller or power controller) behavior in a design, test, or as-manufactured context.
To increase performance when accessing multi-bit PCRAM, it is further advantageous to transfer the (for example) redundancy information to a volatile memory for comparisons to determine whether a redundant element is required for a given memory address.
Since multi-bit PCM is a very promising nonvolatile memory technology, one might consider storing startup information (e.g., redundancy or configuration information) in multi-bit PCM memory which will be used when a memory array comprising multi-bit PCM or other memory comes into operation after a complete or partial power-down. However, the present inventor has realized it is surprisingly difficult to determine at what point during a power-on process sufficient voltage is available to perform reliable reads on multi-bit PCM memory cells; and there are other surprising difficulties to implementation of multi-bit PCM. Typical power-on detect circuitry generally measures whether basic logic is functional by measuring the thresholds of devices used in the logic. Power-on detect for multi-bit PCM is significantly more complex, because multi-bit PCM sense/compare circuitry determines the particular voltage (or current) output as the result of an activated multi-bit PCM cell and compares that output to signal levels corresponding to multi-bit PCM bit states. Put another way, typical power-on detect only has to make an on/off determination corresponding to device thresholds; multi-bit PCM power-on detect has to make an analog determination of signal levels.
The present application discloses implementations for multi-bit PCM memories which accelerate the start of multi-bit PCM operation, e.g., from the start of a power-on sequence, to be exactly as fast as possible. To capture the first moment when the behavior of multi-bit PCM cells permit accurate read operations, the present inventor has developed a configuration which not only discriminates valid read operations, but also tracks temperature dependence and processing variations in the multi-bit PCM cells themselves.
To determine whether the supplied voltage can generate proper operating voltages to drive read operations, one or more memory elements with known resistances are activated and test voltages are applied to, e.g., voltage qualification test cells and corresponding sense amplifiers. The resulting cell outputs are used to determine corresponding logical states, substantially similarly to a typical multi-bit PCM element read, and the results are compared to expected logical states. If the comparisons indicate matches, multi-bit PCM reads can proceed. If the comparisons indicate match failure, then after a delay the test read procedure repeats.
By causing multi-bit PCM memory to begin reads earlier in a power-up process, inventive voltage qualification units can save total energy expenditure by, for example, (1) shortening the amount of total time when power to a corresponding memory needs to be on, because if reads begin sooner, then under certain conditions (e.g., when the memory has a finite set of operations, including reads, to complete before power-down that will keep the memory busy) the memory can power-down sooner; and (2) shortening the amount of time that a corresponding memory takes to reply to read requests, thus potentially reducing the number of wasted cycles (and thus wasted energy) in units requesting memory reads.
In some inventive embodiments, a Power On Reset test can be expected to produce an affirmative result before an inventive multi-bit PCM voltage qualification unit produces a voltage-valid result.
Multi-bit PCM can be used to increase storage density and data throughput of multi-bit PCM memories. However, the resistance levels corresponding to bit states in multi-bit PCM are closer together, and thus more difficult to discriminate, than in single-bit PCM.
Generally, PCM materials are subject to resistance “drift”; resistance levels of one or more states change over time. This means that, long term, outputs corresponding to states may become confused. For example, lower intermediate states may become confused with higher intermediate states as a resistance level of one drifts past an original (pre-drift) resistance level of another.
PCM materials also typically experience resistance changes as a result of temperature changes insufficient to cause state change. This, too, can cause difficulty in state discrimination.
In preferred embodiments, groups of multi-bit PCM cells are read all at once, by comparison with each other rather than against a reference voltage, i.e., using differential sensing rather than single ended sensing; and further, members of the group of cells are written contemporaneously. As a result, the temperature and drift histories of the group of cells are linked, so that comparison of read outputs of the grouped cells can be relied on to show the proper ordering. For example, if cells A, B and C are grouped, and A, B and C are written so that resistances are ordered A>B>C, later reads of this group state can be relied on to produce outputs corresponding to the resistance ordering A>B>C.
Preferably, but not necessarily, the number of cells in a group is equal to the number of PCM states that such cells can contain.
In preferred embodiments using differential sensing, where multi-bit PCM cells can have n nonvolatile states, groups of cells contain at least at least n members, with at least one instance of each state in a group.
Most preferably, groups contain exactly n members and are written so that groups do not contain repeat instances of states. For example, for groups of four cells that can each have any of four states “1”, “2”, “3” and “4”, group state “2314” is allowed, but group state “2334” is not; and for groups of three cells that can each have any of three states “1”, “2”, and “3”, the allowed group states are “012”, “021”, “102”, “120”, “201” and “210”.
Multi-bit voltage qualification is used with, generally, three or more states per cell. When differential sensing is used, then generally, groups of cells have three or more members.
Sense amplifiers 60 are advantageously on the same datapaths as those used by multi-bit PCM cells storing repair information 20, so that test cell 40 read behavior is matched to expected read behavior of the multi-bit PCM cells storing repair information 20 (or other data-storage cells within corresponding multi-bit PCM memories). Matched behaviors can include multi-bit PCM cell responses to temperature changes and responses to variable (e.g., erroneous) voltage inputs.
Repair information, often called test modes (though generally not limited to test configurations), is configuration information and can be, for example, redundancy, trim, test or other configuration information. Redundancy information is generally used to redirect accesses (read and write requests) from defective or otherwise inoperative memory cells to redundant (backup) memory cells. Trim information is generally used to alter the state of an existing topology when device features as-manufactured show variation—which can be expected within some degree of statistical distribution—that can be corrected using measures built into the device. Typically, trim information is determined on a per device (e.g., per chip) basis, and is not accessible to users. Trim can be used to correct, for example, variations in voltage supply outputs or sense amplifier thresholds. Test information can be used to implement test functions, e.g., for device design, design testing or as-manufactured quality assurance purposes. Configuration information can be used, for example, to change timing (e.g., sense amp timing, or setup and hold timing in a data path), internal supply voltages, whether ECC (error correction) or other memory or other component functionality is activated, or other device operation parameters.
In some embodiments, as shown in
To save chip area, it is advantageous for test cells 40 to share sense amplifiers 60 with multi-bit PCM cells used for other purposes, e.g., data-storing PCM cells and PCM cells containing non-volatile repair information 20. Test cells 40 can be located in an extended address space, hidden from users.
Performing this transfer (which requires multi-bit PCM reads) during power-up, as early in the power-up process as possible—preferably before the minimum complete power-up time has elapsed—can save both time and power.
However, as explained, finding the earliest possible time during power-up when multi-bit PCM reads can reliably be performed is complex and difficult, and can be made more difficult when system specifications do not provide a reset command or allow extremely slow skew rates of the external power supply.
Inventive embodiments incorporate voltage qualification units that detect whether a sense path corresponding to a multi-bit PCM cell is operational, that is, whether reads on memory cells containing multi-bit PCM elements along the sense path reliably produce voltage ranges corresponding to multi-bit PCM bit states.
Input X from bitline decoder BLDX enters nFET 1. nFET 1 is configured as a source follower; given the Bias applied to the gate of nFET 1, nFET 1 source is fixed at a particular voltage so that the drain has a current output IX. Put differently, nFET 1 forces a voltage on the bitline selected in bitline decoder BLDX and transforms the bitline output into a current output. pFET 2 is diode connected, i.e., the drain and gate are connected together and to the output of nFET 1, i.e., IX. pFET 2 and pFET 3 (the sources of which are connected to a voltage source, e.g., Vdd) are matched to form a current mirror with ratio 1:1, and together they mirror the source follower output current IX from the drain of pFET 3 to the drain and gate of diode connected nFET 4 and the gates of nFETs 5 and 6. nFETs 4, 5 and 6 are matched, and current mirror IX to nFET 5 and 6 outputs OutA and OutC.
Input Y from bitline decoder BLDY enters nFET 7. nFET 7 is configured as a source follower with gate input Bias. nFET 7 current output TY is input to the gate and drain of diode connected pFET 8 and to the gates of pFETs 9 and 10 (sources of pFETS 8, 9 and 10 are connected to a voltage source, e.g., Vdd). pFETs 8, 9 and 10 are matched, and current mirror IY to pFET 9 and 10 outputs OutB and OutC.
Input Z from bitline decoder BLDZ enters nFET 11. nFET 11 is configured as a source follower with gate input Bias. nFET 7 current output IZ is input to the gate and drain of diode connected pFET 12 and to the gates of pFETs 13 and 14 (sources of pFETS 12, 13 and 14 are connected to a voltage source, e.g., Vdd). pFETs 12, 13 and 14 are matched, and current mirror IZ to pFET 13 output OutA and to nFET 15 gate and drain (nFET 15 is diode connected) and nFET 16 gate. nFET 15 and 16 sources are connected to ground. IZ is current mirrored to nFET 16 output OutB.
OutA equals IX+IZ; OutB equals IY+IZ; and OutC equals IX+IY. Depending on which of each pair of currents comprising, respectively, OutA, OutB, and OutC is greater, the voltages of OutA, OutB and OutC will be driven to the supply voltage (e.g, Vdd) or to ground, depending on which of supply or ground the source of the respective outputting transistor was connected to (nFETs 5 and 6, IX, to ground, pFETs 9 and 10, IY, to source, pFET 13, IZ, to source, and nFET 16, IZ, to ground).
Continuing with two cell groups, two states per cell, a typical differential comparison is performed to obtain BIT0 1500. A 1510 and B 1520 are obtained by multiplying one of each pair of compared cell output currents I_Cell0 1530 and I_Cell1 1540 by a specified proportion (e.g., 20% to 50%, creating I_Cell0*(20% to 50%) 1550 and I_Cell1*(20% to 50%) 1560). The specified proportion is preferably chosen to avoid overlap between possible states. A 1510 and B 1520 are compared by comparison logic 1570; if A 1510 is low and B 1520 is high, the two cells are the same value, and BIT1 1580 is a “Don't Care” (the value of BIT0 1500 is discarded as undetermined). In the two cell group, two states per cell case, use of tristate differential amplifiers can recover at least one additional information state (i.e., the state where the two compared cells have the same phase state). Generally, a tristate differential sense amplifier will not be able to tell by itself which possible state two cells with identical states have been written to.
An I/O controller can also be configured as shown in
The disclosed innovations, in various embodiments, provide one or more of at least the following advantages. However, not all of these advantages result from every one of the innovations disclosed, and this list of advantages does not limit the various claimed inventions.
According to some but not necessarily all embodiments, there is provided: A memory comprising: at least one array of multi-bit phase change memory cells; redundancy logic which redirects attempted accesses from defective memory elements in said array to redundant memory elements, in dependence on a table of defective memory locations residing in multi-bit phase change memory when power to the memory is OFF; and a voltage qualification unit configured to test whether reads of a plurality of multi-bit phase change memory reference cells produce different outputs corresponding to the at least three different logic states stored in said reference cells, and to allow said redundancy logic to begin redirecting accesses only after said outputs correspond to said logic states, wherein said test uses a read voltage generated using said power to the memory.
According to some but not necessarily all embodiments, there is provided: A memory connectable to be powered from a supply voltage, comprising: at least one redundancy data storage comprising a plurality of multi-bit phase change memory cells; at least one array of multi-bit phase change memory cells; at least one access logic controlling access to said array and operating in at least partial dependence on redundancy data stored in said redundancy data storage; and a voltage qualification unit configured to detect whether the supply voltage causes reads of a plurality of multi-bit reference phase change memory cells to produce correctly distinct outputs corresponding to at least three different logic states stored in said reference cells, wherein said redundancy data storage is operatively connected to enable said access logic only after said voltage qualification unit has detected said correctly distinct outputs.
According to some but not necessarily all embodiments, there is provided: A memory comprising: at least one multi-bit phase change memory array; a test logic configured to read/write test memory elements in said array, and to write redundancy information corresponding to defective memory elements that fail said read/write testing to a table of defective memory locations, said table residing in multi-bit phase change memory when power is OFF; a voltage qualification unit configured to test whether reads of multiple multi-bit phase change memory reference cells produce different outputs corresponding to the at least three different logic states stored in said reference cells, and to allow a redundancy logic to begin redirecting accesses from said defective memory elements to redundant multi-bit phase change memory elements, in dependence on said table, only after said outputs correspond to said logic states, wherein said test uses a voltage generated using said power to the memory.
According to some but not necessarily all embodiments, there is provided: A processing system comprising: one or more memory units, one or more processors which execute programmable instruction sequences, and one or more input/output units; repair logic which applies one or more activation voltage variances to adjust feature activation voltages in at least one of said memory units, said processors and said input/output units, said activation voltage variances being at least partially specified by values residing in a multi-bit phase change memory when power to the memory is OFF; and a voltage qualification unit configured to test whether reads of a plurality of reference phase change memory cells produce different outputs corresponding to the at least three different logic states stored in said reference cells, and to allow said repair logic to begin adjusting feature activation voltages only after said outputs correspond to said logic states, wherein said test uses a voltage generated using said power to the memory.
According to some but not necessarily all embodiments, there is provided: A processing system comprising: a phase change memory unit, a processor which executes programmable instruction sequences, an input/output unit, and configuration logic which loads configuration information from said multi-bit phase change memory when power is turned on; a voltage qualification unit configured to test whether reads of a plurality of multi-bit phase change memory reference cells of said multi-bit phase change memory unit, after power is turned on, produce correctly distinct outputs corresponding to the at least three different logic states stored in said reference cells; wherein said configuration logic begins loading the configuration information only if said voltage qualification unit confirms said reads produce said correctly distinct outputs, and wherein said processor and/or said input/output unit operate external elements in accordance with said configuration data.
According to some but not necessarily all embodiments, there is provided: A method of accessing a memory comprising: redirecting attempted accesses from defective memory elements in an array of phase change memory cells to redundant memory elements using a redundancy logic, said redirecting in dependence on a table of defective memory locations residing in multi-bit phase change memory when power to the memory is OFF; and testing, using a voltage qualification unit, whether reads of a plurality of multi-bit phase change memory reference cells produce different outputs corresponding to the different logic states stored in said reference cells; and allowing said redundancy logic to begin redirecting accesses only after said outputs correspond to said logic states, wherein said testing uses a read voltage generated using said power to the memory.
According to some but not necessarily all embodiments, there is provided: A method of accessing a memory comprising: read/write testing memory elements in at least one phase change memory array; writing redundancy information corresponding to defective memory elements that fail said read/write testing to a table of defective memory locations, said table residing in multi-bit phase change memory when power to the memory is OFF; testing whether an input voltage generated using power to the memory causes different read outputs of multiple multi-bit phase change memory reference cells to correspond to at least three different logic states stored in said reference cells; and allowing a redundancy logic to begin redirecting accesses from said defective memory elements to redundant phase change memory elements in dependence on said table, only after said read outputs correspond to said logic states.
According to some but not necessarily all embodiments, there is provided: A method of operating a processing system comprising: applying one or more activation voltage variances, using a repair logic, to adjust feature activation voltages in at least one of one or more memory units, one or more processors which execute programmable sequence instructions and one or more input/output units, said activation voltage variances being at least partially specified by values residing in a multi-bit phase change memory when power to the memory is OFF; and testing whether an input voltage generated using said power to the memory causes one or more multi-bit phase change memory outputs to correspond to at least three logic states stored in corresponding phase change memory cells; and allowing said repair logic to begin adjusting said feature activation voltages only after said outputs correspond to said logic states.
According to some but not necessarily all embodiments, there is provided: Systems in which multi-bit PCM is used, including memory systems, as well as methods for operating such systems. A test of multi-bit PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read multi-bit PCM. This can be used to accelerate availability of memory states residing in multi-bit PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful.
As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given. It is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.
Embodiments described herein have been disclosed with respect to three- and four-state PCM materials. However, in some embodiments, PCM materials with larger numbers of states (e.g., five) may also be used.
In some embodiments, outputs from physical cells within groups of cells are not compared pairwise. For example, pairs of outputs may be added together and the sums compared.
In some embodiments, more than one physical cell within a group of cells is allowed to have a given state. In such embodiments, differential sense amplifiers may use, for example, tri-state logic so that the output equality case can be represented.
In some embodiments, a group of cells may contain a different number of multi-bit PCM cells than the corresponding multi-bit PCM material has nonvolatile states.
In some embodiments, output values other than current may be compared, e.g., voltage.
In some embodiments, cells within a group may be accessed substantially simultaneously when said group is accessed.
In some embodiments, cells within a group may be accessed at different times when said group is accessed.
In some embodiments, cells can be switched from differential sense amplification to single ended sense amplification and back.
In some embodiments, divided (unmirrored) currents are compared.
In some embodiments, fewer than all possible states of corresponding multi-bit PCM cells can be used.
In some embodiments, contents of groups can be rearranged so that groups are comprised of different sets of cells from prior to being rearranged.
In some embodiments, duplicate instances of a state can be stored within a group of cells.
In some embodiments, a voltage qualification test could use differential sensing for some bitlines, and single ended sensing for other bitlines.
In some embodiments, a memory could use a lower signal margin to obtain higher storage density at the expense of longer sense and/or write times. In other embodiments, a memory could use a higher single margin to obtain higher sense and/or write times at the expense of lower storage density.
In some embodiments, multi-bit PCM is used in contexts in which embedded DRAM is typically used.
In some embodiments, multi-bit PCM is used for CPU on-chip memory.
In some embodiments, multi-bit PCM is used in on-chip memory contexts where field-programmable gate array (FPGA) memory is typically used.
In some embodiments, multi-bit PCM may be used to load a startup state into device registers, e.g., CPU registers.
In some embodiments, multi-bit PCM may be used with multiple other memory types on a single chip.
In some embodiments, more than one cell storing a particular logical state can be used in the multi-bit PCM cells in the voltage qualification unit.
In some embodiments, information is stored in multi-bit PCM cells for startup procedures other than defective memory repair.
In some embodiments, multiple valid reads are required by some or all of the cells within the voltage qualification unit, across multiple test cycles, before a usable read voltage is determined to be available.
In some embodiments using multiple multi-bit PCM cells storing ones of possible logical states in a voltage qualification unit, at least one of said cells within the voltage qualification unit is not rewritten, either (1) for an extended period of time or (2) ever.
In some embodiments using multiple multi-bit PCM cells storing ones of possible logical states in a voltage qualification unit, at least one of said cells within the voltage qualification unit is rewritten at random intervals when a corresponding memory's power is on.
In some embodiments, multi-bit phase change memory cells can contain multiple multi-bit phase change memory elements, ones of said memory elements having separate readable states.
In some embodiments, multi-bit SET and RESET pulses reset multi-bit PCM cell drift characteristics of both “0” and “1” logical states, i.e., without requiring a logical state transposition to reset cell drift characteristics.
In some embodiments, outputs of groups of multi-bit PCM cells storing all possible logical states of a multi-bit PCM are compared to each other, e.g., using a logic gate, after having been read by a sense amplifier.
In some embodiments, multi-bit PCM test cells storing all possible logical states of a multi-bit PCM are not grouped physically or by address.
In some embodiments, different numbers of multi-bit PCM test cells store different logical states.
In some embodiments using multiple multi-bit PCM cells storing ones of possible logical states in a voltage qualification unit, multi-bit PCM cells within the voltage qualification unit are rewritten to store different logical states when certain conditions are met, e.g., after a certain number of reads or writes, after a certain amount of time, after a certain amount of time when a corresponding memory's power is on, after a certain number of voltage qualification tests, after a certain number of voltage-valid voltage qualification test results, or after every power-on. In some of these embodiments, different cells or groups of cells may have different criteria to trigger a rewrite.
None of the description in the present application should be read as implying that any particular element, step, or function is an essential element which must be included in the claim scope: THE SCOPE OF PATENTED SUBJECT MATTER IS DEFINED ONLY BY THE ALLOWED CLAIMS. Moreover, none of these claims are intended to invoke paragraph six of 35 USC section 112 unless the exact words “means for” are followed by a participle.
Additional general background, which helps to show variations and implementations, may be found in the following publications, all of which are hereby incorporated by reference: Lam, Chung. “Phase Change Memory: A Replacement or Transformational Memory Technology,” IEEE Workshop on Microelectronics and Electron Devices (WMED), c. 2011. Choi, Youngdon, et al. “A 20 nm 1.8V 8 Gb PRAM with 40 MB/s Program Bandwidth.” ISSCC 2012/Session 2/High Bandwidth DRAM & PRAM/2.5. c. 2012. U.S. Pat. No. 8,259,490 for “Multi-level Phase-Change Memory Device and Method of Operating Same”. U.S. Pat. No. 8,238,147 for “Multi-Level Phase Change Memory Device, Program Method Thereof, and Method and System Including the Same”. Papandreou, N., et al., “Multi-Level Phase Change Memory”, 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2010, Zurich, Switzerland (Dec. 2010), 1017-1020. Papandreou, N., et al., “Drift-Tolerant Multilevel Phase-Change Memory”, 3rd IEEE International Memory Workshop (IMW), 2011, Zurich, Switzerland (May 2011), 1-4.
Additional general background, which helps to show variations and implementations, as well as some features which can be synergistically with the inventions claimed below, may be found in the following US patent applications. All of these applications have at least some common ownership, copendency, and inventorship with the present application, and all of them are hereby incorporated by reference: U.S. Provisional Pat. Nos. 61/637,331; 61/637,496; 61/637,513; 61/637,518; 61/637,526; 61/637,533; 61/638,217; 61/694,217; 61/694,220; 61/694,221; 61/694,223; 61/694,224; 61/694,225; 61/694,228; 61/694,234; 61/694,240; 61/694,242; 61/694,243; and 61/694,245.
The claims as filed are intended to be as comprehensive as possible, and NO subject matter is intentionally relinquished, dedicated, or abandoned.
Priority is claimed from U.S. Provisional Patent Application Nos. 61/637,533 filed Apr. 24, 2012, and 61/784,480 filed Mar. 14, 2013, both of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61637533 | Apr 2012 | US | |
| 61784480 | Mar 2013 | US |
