Patent Application
20220304149
The present disclosure generally relates to multilayer circuit boards, and particularly to high speed traces routing methods for OSFP and/or QSFP DD printed circuit boards.
Quad small form-factor pluggable (QSFP) is a widely used interface for data center external TO connection applications. As the industry is moving toward a higher data rate per cable, the quad small form-factor pluggable double density (QSFP-DD) interface and octal small form-factor pluggable (OSFP) interface have been introduced to carry double the data capacity of a QSFP cable assembly. High speed traces are routed in the circuit boards to achieve high speed data transmission at low losses.
Some aspects of the disclosure relate to a multilayer circuit board extending along a first direction between opposite front and rear edges of the circuit board. The multilayer circuit board includes a plurality of stacked layers. A plurality of electrically conductive rear pads is disposed between the front and rear edges for termination of a plurality of wires thereto. A plurality of electrically conductive front pads is disposed between the rear pads and the front edge for insertion into a connector. A plurality of pairs of substantially parallel traces extend between and connect the front pads to the rear pads. Each pair of traces is configured to transmit a differential signal. For at least a first pair of traces, the pair of traces and their corresponding rear and front pads are disposed in a same layer in the plurality of layers. For at least a second pair of traces, at least portions of the second pair of traces are disposed in a same first layer in the plurality of layers, and the rear and front pads corresponding to the second pair of traces are disposed in a same second layer in the plurality of layers, different from the first layer. For at least a third pair of traces, at least portions of the third pair of traces are disposed in a same third layer in the plurality of layers, the rear pads corresponding to the third pair of traces are disposed in a same fourth layer, different from the third layer, in the plurality of layers, and the front pads corresponding to the third pair of traces are disposed in a same fifth layer, different from the third and fourth layers. For at least one common cross-section of the plurality of pairs of traces, the common cross-section substantially perpendicular to the first direction, each pair of traces is disposed between ground traces disposed on opposite lateral sides of the pair of traces. For each trace extending between and connecting the front and rear pads corresponding to the trace, the trace includes no more than two vias.
Other aspects of the disclosure relate to a multilayer circuit board including a plurality of electrically conductive rear pads for termination of a plurality of wires thereto. The multilayer circuit board includes a plurality of electrically conductive front pads for insertion into a connector. The multilayer circuit board also includes a plurality of pairs of substantially parallel traces extending between and connecting the front pads to the rear pads. Each pair of traces is configured to transmit a differential signal. At least a first pair of traces and the front and rear pads connected thereto are disposed in a same layer of the multilayer circuit board. At least a second pair of traces is disposed in a same layer of the multilayer circuit board. The rear and front pads connected thereto are disposed in a different layer of the multilayer circuit board. At least a third pair of traces are disposed in different layers of the multilayer circuit board. In a plan top view of the multilayer circuit board, a total area of the pluralities of the rear pads, front pads, and pairs of traces is A1, and a total projected area of the pluralities of the rear pads, front pads, and pairs of traces is A2, wherein A2/A1≤0.8.
These and other aspects of the present application will be apparent from the detailed description below. In no event, however, should the above summaries be construed as limitations on the claimed subject matter, which subject matter is defined solely by the attached claims.
The various aspects of the disclosure will be discussed in greater detail with reference to the accompanying figures where,
The figures are not necessarily to scale. Like numbers used in the figures refer to like components. However, it will be understood that the use of a number to refer to a component in a given figure is not intended to limit the component in another figure labeled with the same number.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure.
A multilayer circuit board is a circuit board made up of a plurality (e.g., at least 2, or at least 3, or several, or a large number) of wiring layers laminated with insulation layers interposed therebetween. Various electronic parts and a connector are mounted at predetermined positions of the multilayer circuit board. Each layer of the multilayer circuit board carries electrical connections, or conductive traces, which act as wires and are used to interconnect various components of the circuit. The conductive traces are bonded to, or otherwise incorporated into, an insulating substrate which mechanically supports the components. The conductive traces may be formed using any number of techniques, for example electroplating, etching, sputtering, mechanical attachment using adhesives and others explained elsewhere. The substrate may be flexible or rigid and may be fabricated from any suitable material, for example polymers, ceramics, glasses, silicon, etc.
Electrical connection between adjacent layers is achieved using “vias.” A via may be created by forming a hole between adjacent layers. In some aspects, the hole is filled with conductive material to form an electrical connection between the two adjacent layers. In a method of printed circuit board (PCB) fabrication, the conductive traces are formed separately on each layer of the multilayer circuit board. The circuit board layers of the multilayer circuit board are then stacked and aligned to each other with an electrically insulating bonding layer between adjacent layers. The assembled layers may then subjected to heat and pressure to provide a bond between adjacent layers. Via holes are then drilled in the appropriate locations which interconnect pads on successive layers. The electrical interconnect is achieved by applying a conductive material to the side walls of the via holes.
OSFP PCBs have double the data bandwidth when compared to the QSFP standard. The OSFP interface is similar to the QSFP DD interface except that it uses only one row of mating interface to achieve the 8 high speed channel design. As the number of high speed channels increases there are challenges in designing PCBs and cable arrangements in order to fit bigger size cables within the same overall size of metal shell that covers the PCB. High speed traces within the PCB should be more uniformly routed to achieve high speed transmission, with better signal integrity (SI) performance at low losses.
A multilayer circuit board (300), as illustrated in
As best seen in
A plurality of electrically conductive rear pads (30) is disposed between the front (11) and rear (10) edges for termination of a plurality of wires (40) thereto. In some embodiments, the plurality of electrically conductive rear pads (30) forms first (31), second (32) and third (33) rows of rear pads on an upper side (301) of the circuit board and a fourth row (34) of rear pads on a lower side (302) of the circuit board.
A plurality of electrically conductive front pads (50) is disposed between the rear pads (30) and the front edge (11) for insertion into a connector (400). In certain embodiments as best illustrated in
As shown in
As best shown in
As best shown in
The rear pads (90c, 90d) corresponding to the third pair of traces (90a, 90b) are disposed in a same fourth layer (21), different from the third layer (23), in the plurality of layers. The front pads (90e, 90f) corresponding to the third pair of traces (90a, 90b) are disposed in a same fifth layer (24), different from the third and fourth layers.
Further, each front pad (80e, 80f) of the second pair of traces (110c, 110d) are connected to respective vias (160). The second pair of traces (110c, 110d) are disposed such that vias (160) connect respective front pads (80e, 80f) disposed on one layer of the multilayer circuit board to a portion of the second pair of trace disposed on a different layer of the circuit board. In some aspects, the vias (160) connect the respective front pads (80e, 80f) of the second pair of traces (110c, 110d), said front pads being disposed on a layer of the multilayer circuit board, to a portion of the second pair of trace (110c, 110d) disposed on a layer below the layer on which the front pads (80e, 80f) are disposed.
The cross sectional view of
In other aspects of the disclosure, in a plan top view of the multilayer circuit board, a total area of the pluralities of the rear pads, front pads, and pairs of traces is A1. A total projected area of the pluralities of the rear pads, front pads, and pairs of traces is A2. The projected area A2 is the area of overlap of the traces in the plan view. In some embodiments, A2/A1≤0.8. In other embodiments, A2/A1≤0.75, or A2/A1≤0.70. In some other embodiments, A2/A1 is about 0.64 and in some other embodiments, A2/A1 is about 0.65.
Descriptions for elements in figures should be understood to apply equally to corresponding elements in other figures, unless indicated otherwise. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations can be substituted for the specific Embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific Embodiments discussed herein. Therefore, it is intended that this disclosure be limited only by the claims and the equivalents thereof.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/IB2020/055250 | 6/3/2020 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 62867960 | Jun 2019 | US |
