1. Field of the Invention
The present invention relates to a multilayer circuit substrate.
2. Description of Related Arts
A multilayer circuit substrate proposed in Patent Document 1 (see, for example, Japanese Published Unexamined Patent Application No. 2008-182184) includes a laminated circuit portion, a metal substrate, and a heat releasing via. The laminated circuit portion is formed by alternately laminating a conductor layer and an insulating layer made of resin. The metal substrate is disposed in contact with the insulating layer that is a lowermost layer. A conductor layer is formed on an inner surface of the heat releasing via, and this conductor layer connects the conductor layer, which is an uppermost layer on which electronic parts are mounted, to the lowermost insulating layer.
Also, a multilayer circuit substrate in which a semiconductor bare chip is embedded is proposed in Patent Document 2 (see, for example, Japanese Published Unexamined Patent Application No. 2004-153084). A heat releasing pattern for heat release of the semiconductor bare chip is provided on a base material of a lowermost layer of the multilayer circuit substrate. The heat releasing pattern is formed integral to the semiconductor bare chip.
Also, a multilayer substrate proposed in Patent Document 3 (see, for example, Japanese Published Unexamined Patent Application No. 2005-260878) has dielectric layers on which a plurality of power amplifying circuits are mounted. Interference preventing grounding patterns respectively corresponding to the power amplifying circuits are disposed in a mutually separated manner on a dielectric layer corresponding to an upper layer or a lower layer among the dielectric layers. The interference preventing grounding patterns are connected via vias to a common grounding pattern provided on one of the dielectric layers.
By using a via, efficiency of heat release to a conductor layer that is a lowermost layer is improved. On the other hand, a level of heat release efficiency of a pathway for releasing heat from the conductor layer that is the lowermost layer to a metal plate via an insulating resin layer is a bottleneck for improving a heat release property of a multilayer circuit substrate as a whole.
An object of the present invention is to provide a multilayer circuit substrate with which a heat release property can be improved as a whole.
A preferred mode of the present invention provides a multilayer circuit substrate that includes a substrate body in turn including a plurality of conductor layers and a plurality of insulating layers that are laminated alternately, and a plurality of heat releasing vias. The plurality of conductor layers include an uppermost conductor layer and a lowermost conductor layer. The uppermost conductor layer includes a plurality of conductor patterns on which a plurality of semiconductor devices are respectively mounted. The lowermost conductor layer includes a plurality of conductor patterns including a plurality of heat releasing patterns. The plurality of heat releasing patterns are respectively provided in one-to-one correspondence with the plurality of semiconductor devices. Each of the heat releasing patterns has an area no less than an area of the corresponding semiconductor device. Each of the heat releasing patterns is connected to the corresponding semiconductor device via a corresponding heat releasing via.
With the present preferred mode, heat can be released efficiently from the conductor patterns of the uppermost conductor layer, respectively having the semiconductor devices mounted thereon, to the respectively corresponding heat releasing patterns of the lowermost conductor layer via separate heat releasing vias. Moreover, the following merit is provided by the area of each of the heat releasing patterns of the lowermost conductor layer being made no less than the area of the corresponding semiconductor device on the corresponding conductor pattern of the uppermost conductor layer. That is, in a case where the present multilayer circuit substrate is supported by a heat releasing plate (for example, an aluminum plate or other metal plate) via an insulating resin layer, heat can be released efficiently to the heat releasing plate side from the heat releasing patterns of the lowermost conductor layer. The multilayer circuit substrate is thus improved in heat release property as a whole.
A preferred embodiment of the present invention shall now be described specifically with reference to the drawings.
The substrate body 2 includes a plurality of conductor layers 11 to 14 and a plurality of insulating layers 21 to 23 that are laminated alternately. That is, the substrate body 2 is formed by the first conductor layer 11 as an uppermost conductor layer, a first insulating layer 21, a second conductor layer 12, a second insulating layer 22, a third conductor layer 13, a third insulating layer 23, and a fourth conductor layer 14 as a lowermost conductor layer being laminated in that order.
Each of the conductor layers 11 to 14 may be formed, of a metal, such as copper, aluminum, nickel, silver, titanium, gold, etc., or an alloy of such metals, or may be formed by application of nickel plating or nickel/gold plating on a surface of such a metal or a surface of an alloy of such metals. Each of the insulating layers 21 to 24 may be formed, for example, of a synthetic material of glass fibers and epoxy resin.
The adhesive layer 4 may, for example, be arranged by adding a thermal conductivity improving material 42 for increasing thermal conductivity to a base material 41 that includes an epoxy resin or other resin. The thermal conductivity improving material 42 is a powder or grains of a material with a high thermal conductivity coefficient. An insulating ceramic may be used as the thermal conductivity improving material 42. At least one material among aluminum nitride (AlN), aluminum oxide (Al203), silicon nitride (Si3N4) and silicon oxide (Si02) may be used as the insulating ceramic.
In a case the insulating ceramic may be used as the thermal conductivity improving material 42, the thermal conductivity can thereby be increased while maintaining the insulating property of the adhesive layer 4. Consequently the heat releasing effect of the multilayer circuit substrate 1 as a whole can be improved.
Also, at least one of either a metal or carbon may be used as the thermal conductivity improving material 42. In general, a metal and carbon have electrical conductivity and are preferably added at an addition rate in a range that does not decrease an insulation resistance of the base material. The thermal conductivity can thereby be increased while maintaining the insulating property of the adhesive layer 4. At least one of either the metal or the carbon may be used with the insulating ceramic.
As shown in
That is, the first semiconductor device 51 is mounted on the first conductor pattern 111. The second semiconductor device 52 is mounted on the second conductor pattern 112. The third semiconductor device 53 is mounted on the third conductor pattern 113. The fourth semiconductor device 54 is mounted on the fourth conductor pattern 114. The fifth semiconductor device 55 is mounted on the fifth conductor pattern 115. The sixth semiconductor device 56 is mounted on the sixth conductor pattern 116. For example, each of the semiconductor devices 51 to 56 may be a bare chip of a switching device, such as a MOSFET, for driving an electric motor.
Also, as shown in
The respective conductor patterns 111 to 116 of the first conductor layer 11 as the uppermost conductor layer shown in
That is, the first semiconductor device 51 is connected to the first heat releasing pattern 141 via a plurality of heat releasing vias 61. The second semiconductor device 52 is connected to the second heat releasing pattern 142 via a plurality of heat releasing vias 61. Also, although not illustrated, the third semiconductor device 53 is connected to the third heat releasing pattern 143 via a plurality of heat releasing vias. The fourth semiconductor device 54 is connected to the fourth heat releasing pattern 144 via a plurality of heat releasing vias. The fifth semiconductor device 55 is connected to the fifth heat releasing pattern 145 via a plurality of heat releasing vias. The sixth semiconductor device 56 is connected to the sixth heat releasing pattern 146 via a plurality of heat releasing vias.
In terms of improving thermal conduction to the heat releasing patterns 141 to 146 of the fourth conductor layer 14 as the lowermost conductor layer, it is preferable for each of the conductor patterns 111 to 116 of the first conductor layer 11 as the uppermost conductor layer to be connected to the corresponding heat releasing pattern among the heat releasing patterns 141 to 146 of the fourth conductor layer 14 as the lowermost conductor layer via the plurality of heat releasing vias 61.
Each heat releasing via 61 is arranged, for example, by filling a thermal via hole with a conductive metal material, such as copper. Also, a metal, such as aluminum, nickel, silver, titanium, gold, etc., or an alloy of such metals may be used in place of copper as the conductive metal material to be filled in the thermal via hole.
As shown in
Also, as shown in
Referring again to
Although not illustrated in
With the present preferred embodiment, heat can be released efficiently from the respective conductor patterns 111 to 116 of the first conductor layer 11 as the uppermost conductor layer, on which the respective semiconductor elements 51 to 56 are mounted, to the respectively corresponding heat releasing patterns 141 to 146 of the fourth conductor layer 14 as the lowermost conductor layer via separate sets of the plurality of heat releasing via 61.
Moreover, the area of each of the heat releasing patterns 141 to 146 of the fourth conductor layer 14 as the lowermost conductor layer is made no less than the area of the respectively corresponding semiconductor device among the semiconductor devices 51 to 56 of the first conductor layer 11 as the uppermost conductor layer. Heat can thus be released efficiently from the respective heat releasing patterns 141 to 146 of the fourth conductor layer 14 as the lowermost conductor layer to the heat releasing plate 3 side via the adhesive layer 4 having the high thermal conductivity coefficient. The heat release property of the multilayer circuit substrate 1 as a whole is thus improved.
That is, the heat releasing effect of the multilayer circuit substrate 1 as a whole can be improved because the first to sixth heat releasing patterns 141 to 146 are connected to the heat releasing plate 3 via the adhesive layer 4, which is a resin layer with an insulating property.
Also, the semiconductor devices 51 to 56 are bare chips of switching devices, and thus heating of the switching devices to a high temperature can be prevented, and by using these switching devices, for example, an electric motor can be driven with stability.
The present invention is not restricted to the preferred embodiment described above, and for example, at least a portion of wiring vias may be used in common as the heat releasing vias.
While the present invention has been described in detail by way of a specific preferred embodiment, those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to the preferred embodiment. Accordingly, the scope of the present invention should be assessed as that of the appended claims and any equivalents thereto.
This application corresponds to Japanese Patent Application Nos. 2010-120850 and 2011-98638, filed with the Japan Patent Office on May 26, 2010 and Apr. 26, 2011, the entire disclosures of which are incorporated herein by reference.
Number | Date | Country | Kind |
---|---|---|---|
2010-120850 | May 2010 | JP | national |
2011-98638 | Apr 2011 | JP | national |