Patent Application
20190363067
The present invention relates to a multilayer semiconductor integrated circuit device, and in particular to a structure for supplying the potential of a power supply between semiconductor chips that are layered on top of each other.
In recent years, integrated circuits of which the degree of integration has been increased by layering chips three-dimensionally have been demanded. When memory chips are layered on top of each other, for example, the memory capacity can be increased, and the power consumption that is required for data transfer can be reduced. As for the technology for connecting signals or power supplies between such layered chips, connection by means of wire bonding, connection by means of TAB (tape automated bonding), connection by means of TSV (through silicon via) and the like are known.
From among these, wire bonding has such a problem that the mounting volume becomes large because chips must be layered on top of each other while shifting in such a manner that the openings of the bonding pads for the power supply are not covered. In addition, the current capacity per bonding wire is small and the number of bonding wires has an upper limit, and therefore, such a problem also arises that a sufficient power supply quality cannot be gained.
TAB provides a current capacity that is greater as compared to wire bonding, and the pads for power supply can be arranged in the places other than the periphery of the chips; however, a relatively large gap for allowing the TAB to pass between the layered chips is required, which causes such a problem that the pitch between the chips in the direction in which the chips are layered on top of each other becomes large.
In contrast, TSV is characterized in that all of these problems can be solved. Furthermore, TSV can be used not only in a case where individual chips are layered on top of each other so as to be connected, but also in a case where wafers are layered on top of each other so as to be connected, and thus has such an advantage that the manufacturing efficiency (throughput) can be increased. However, additional processes for creating holes in the silicon substrate, forming an insulating film on the surface of the inner wall of the holes, filling the holes with an electrode, and connecting the electrodes to bumps are necessary, and therefore, such a problem arises that the manufacturing costs increase.
Meanwhile, the present inventor has proposed an electronic circuit which allows wireless data communication between semiconductor integrated circuit chips that are layered on top of each other by using inductive coupling between coils that are formed of wires in the chips, and thus has solved the above-described problems concerning data connection (see Patent Literature 1 or Patent Literature 2).
According to the invention in Patent Literature 1, for example, wireless data communication can be achieved between the layered chips by using inductive coupling between the pair of coils. According to the invention in Patent Literature 2, identical chips are layered on top of each other when mounted in such a manner that wireless data communication can be achieved between the chips, and the power can be supplied by means of wire bonding.
Though TSV can solve the above-described technical problems, the manufacturing costs increase, and therefore, TSV has not been adopted at present in an actual production line. Therefore, the present inventor has proposed manufacturing a multilayer semiconductor integrated circuit device of which the manufacturing costs have been greatly reduced by using a through semiconductor region instead of TSV in order to solve the problems with TSV (see Patent Literature 3).
Here, a p++ type well region 102 and an n++ type well region 103 that penetrate through the p− type Si substrate 101 are provided in the p− type Si substrate 101 so as to form a power supply wire instead of TSV. Here, through semiconductor regions are provided as the p++ type well region 102 and the n++ type well region 103 where B (boron) is used as the impurity because doping at a high concentration is possible up to the deep portion of the substrate. Numbers 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116 and 117 in the figure respectively denote a p+ type contact region, an n type region, an n+ type contact region, a p type region, an interlayer insulating film, a contact electrode, a contact electrode, a wire layer, a wire layer, an interlayer insulating film, a surface electrode and a surface electrode.
By layering a number of semiconductor chips like this on top of each other, a multilayer semiconductor integrated circuit device can be implemented. In this case, a sufficiently low wire resistance value is achieved by securing a predetermined area in the entire plane for the p++ type well region 102 and the n++ type well region 103 that become the through semiconductor regions.
A similar idea to this proposal has already been proposed (see Patent Literature 4). In this proposal, however, the resistance value of the through semiconductor regions is too high to be applied to an actual device, and no means for solving this problem have been disclosed. That is to say, the use of a through semiconductor region as a power supply wire for the connection to the power supply is not considered at all in Patent Literature 4. This is because the resistance value of the semiconductor through hole region is several tens [ohm], and it is clear for those skilled in the art that the semiconductor through hole region makes the voltage drop on the basis of the resistance value too large to supply a stable power supply in the case when it is used as the wire for power supply, though it can be used as a signal wire for a low speed signal. In the case where a number of semiconductor substrates are layered on top of each other, in particular, a high quality power supply voltage is not supplied to a semiconductor substrate in an upper layer, which prevents the semiconductor substrates from functioning as a multilayer integrated circuit device.
As a result of the diligent research by the present inventor, however, it has been found that a problem arises in the case where the concentration of B (boron) is increased in order to lower the resistance of the p type through semiconductor region, for example, in the case where the concentration is 1018 cm−3 or higher, though almost no problem arises in the case where the concentration of B in the p type through semiconductor region is not very high, for example, in the case where the concentration is less than 1018 cm−3. It has also been found that no such problem arises in then type through semiconductor region irrelevant of the concentration of P (phosphorous).
This phenomenon was examined. As for the principal of why the Si substrate can be polished in accordance with CMP, the Si—Si bonds in the Si substrate are polarized, and the Si atoms that have been negatively polarized create Si—OH bases, which are mechanically removed. In the p type Si substrate where Si is doped with B (boron) at a high concentration, however, it is considered that negatively charged B atoms take the OH bases, which makes it difficult for Si—OH bases to be generated, and thus, the polishing rate of CMP is lowered. In contrast, in the n type Si substrate where Si is doped with P (phosphorous) at a high concentration, a conclusion has been reached that the positively charged P atoms do not take the OH bases, which does not prevent Si—OH bases from being generated, and thus, the polishing rate of CMP is not lowered.
In the case where the p type Si substrate is converted to a thin layer of 4 μm or less, a stable layering step is possible when there is a difference in the level of approximately 1 nm over a range of 20 μm×20 μm; however, layering becomes difficult when there is a difference in the level of approximately 90 nm.
Thus, an object of the present invention is to implement a stable multilayer structure.
One embodiment provides a multilayer semiconductor integrated circuit device with at least a first semiconductor integrated device and a second semiconductor integrated device, where the first semiconductor integrated circuit device includes: a first p type semiconductor body; a first n type semiconductor region that is provided in the first p type semiconductor body, and where an element including a transistor is provided; a first p type semiconductor region that is provided in the first p type semiconductor body, and where an element including a transistor is provided; a first n type through semiconductor region that penetrates through the first p type semiconductor body in the direction of the thickness, and at the same time is connected to the potential of a grounded power supply; and a second n type through semiconductor region that penetrates through the first p type semiconductor body in the direction of the thickness, and at the same time is connected to the potential of a positive power supply; and where the second semiconductor integrated circuit device forms a multilayer structure together with the first semiconductor integrated circuit device, and has a first electrode that is electrically connected to the first n type through semiconductor region and a second electrode that is connected to the second n type through semiconductor region.
The disclosed multilayer semiconductor integrated circuit device makes a stable multilayer structure possible.
The multilayer semiconductor integrated circuit device according to an embodiment of the present invention is described in reference to
In this manner, an n type through semiconductor region can be used when a through semiconductor region having a high impurity concentration is used instead of TSV, of which the manufacturing costs are high, and thus, a step can be effectively prevented from being generated at the time of polishing of the rear surface. As a result, a plurality of semiconductor integrated circuit devices can be layered on top of each other in a stable manner. Here, Patent Literature 3 does not disclose or suggest the point where a first n type through semiconductor region and a second n type through semiconductor region are provided in a p type semiconductor substrate.
In this case, it is desirable for the thickness of the first p type semiconductor substrate 21 to be 4 μm or less. In this manner, the first p type semiconductor substrate 21 can be converted to a thin layer of which the thickness is 4 μm or less, more preferably 3 μm or less, so that a through semiconductor region can be formed of which the power supply quality can be sufficiently assured even when a type of ion implantation unit that is widely available at present is used. In addition, the total height of the multilayer can be reduced. As a result, communication channels can be arranged at a high concentration or the power consumption for communication can be lowered by reducing the size of the coils for communication through magnetic field coupling.
In order to apply the potential of a grounded power supply to the first p type semiconductor substrate 21, a first p type contact region 71 that is connected to the potential of the grounded power supply is provided in proximity to the first n type through semiconductor region 51. In addition, a second p type contact region 81 that is connected to the potential of the grounded power supply is provided in proximity to the second n type through semiconductor region 61.
The wire resistance value in this case, that is to say, the sum of the resistance of the resistance value of the through semiconductor region and the contact resistance between the through semiconductor region and the contact electrode can be made sufficiently small, typically 3 mΩ or less, so that a sufficiently high power supply quality can be gained. Incidentally, the resistance value of an Au wire for wire bonding becomes 20 mΩ when the diameter of the Au wire is 25 μmφ, the length is 0.5 mm, and the electrical resistivity is 2.21×10−8 Ωm. Accordingly, 3 mΩ is enough to reduce the resistance value by one digit as compared to the resistance value of conventional bonding wires, which makes it possible to gain a sufficiently high power supply quality (see Patent Literature 3).
At this time, crystal defects are introduced on the polished surface due to rear surface polishing, and a leak current flows through the resistance r1 caused by the depletion layer 13. When VDD is higher than the voltage Vf in the forward direction (0.6 V), the parasitic bipolar transistor could be turned on; however, r1 is 1 MΩ or higher, and rs is 1 kΩ or lower, and thus, the risk of the parasitic bipolar transistor being turned on is not necessarily high. In order to suppress the turning on of the parasitic bipolar transistor without fail, however, rs<<r1 may be achieved. In order to do so, a second p type contact region 81 may be provided in proximity to the second n type through semiconductor region 61 so that the parasitic resistance rs between the first p type contact region 71 and the first p type semiconductor substrate 21 can be made small.
That is to say, in order for the parasitic bipolar transistor with the first n type through semiconductor region 51 being the emitter, the first p type semiconductor substrate 21 being the base, and the second n type through semiconductor region 61 being the collector to be prevented from being turned on, it is desirable for the resistance rs between the base and the emitter to be smaller than the resistance r1 between the collector and the base.
At this time, the arrangement may allow the first p type contact region 71 to surround the periphery of the first n type through semiconductor region 51, and the second p type contact region 81 to surround the periphery of the second n type through semiconductor region 61.
Alternatively, the arrangement may allow the side of the first p type contact region 71 that faces the first n type through semiconductor region 51 to be longer than the side of the first n type through semiconductor region 51 that faces the first p type contact region 61 and the side of the second p type contact region 81 that faces the second n type through semiconductor region 61 to be longer than the side of the second n type through semiconductor region 61 that faces the second p type contact region 81. Alternatively, the arrangement may allow the first p type contact region 71 and the second p type contact region 81 to be integrated so as to form a continuous pattern.
Alternatively, the arrangement may allow the first p type contact region 71 and the second p type contact region 81 to form a single p type semiconductor region in a frame form in such a manner that the first n type through semiconductor region 51 and the second n type through semiconductor region 61 are arranged inside this single p type semiconductor region in a frame form.
In addition, in order to increase the parasitic resistance between the collector and the base, an n type semiconductor region in a frame form may be provided around the second n type through semiconductor region 61 that is connected to the potential of a positive power supply with a portion of the first p type semiconductor substrate 21 in between. Instead of this n type semiconductor region in a frame form, multiple n type semiconductor regions in a frame form may be provided.
As for the second semiconductor integrated circuit device 12, a second n type semiconductor region 32, where an element that includes a transistor is provided, and a second p type semiconductor region 42, where an element that includes a transistor is provided, are provided in a second p type semiconductor substrate 22. In addition, a third n type through semiconductor region 52 that penetrates through the second p type semiconductor substrate 22 in the direction of the thickness, and at the same time is connected to the potential of a grounded power supply, and a fourth n type through semiconductor region 62 that is connected to the potential of a positive power supply may be provided, and a first electrode 92 may be connected to the third n type through semiconductor region 52, and a second electrode 102 may be connected to the fourth n type through semiconductor region 62. In this manner, through semiconductor regions can be provided in the second semiconductor integrated circuit device 22 as well in order to make it possible for three or more chips to be layered on top of each other.
It is desirable for no electrodes to be provided on the surfaces of the first n type through semiconductor region 51 and the second n type through semiconductor region 62 that are exposed from the surface of the first semiconductor integrated circuit device 11 that faces the second semiconductor integrated circuit device 12, that is to say, from the rear surface of the first semiconductor integrated circuit device 11. In this manner, no electrodes are provided on the rear surface, which makes it possible to reduce the manufacturing costs, and at the same time makes it possible to reduce the height of the multilayer.
In the case where no electrodes are provided on the rear surface, a plurality of first plug electrodes may be provided on the surface of the first electrode 92 that is provided in the second semiconductor integrated circuit device 12, and a plurality of second plug electrodes may be provided on the surface of the second electrode 102 that is provided in the second semiconductor integrated circuit device 12. By providing these plug electrodes, electrical contact with the rear surfaces of the first n type through semiconductor region 51 and the second n type through semiconductor region 61 where no rear surface electrodes are provided can be achieved without fail.
The arrangement of the elements in the first semiconductor integrated circuit device 11 and the arrangement of the elements in the second semiconductor integrated circuit device 12 may be the same. In this manner, the arrangement of the elements in the respective semiconductor integrated circuit devices can be made the same in order to implement, for example, a memory device with a large capacity at a low cost.
Alternatively, the arrangement of the elements in the first semiconductor integrated circuit device 11 and the arrangement of the elements in the second semiconductor integrated circuit device 12 may be different. In this manner, the arrangement of the elements in the respective semiconductor integrated circuit devices can be made different in order to implement, for example, a multifunctional semiconductor device having a hybrid integrated memory and logic circuit at a low cost.
A plurality of semiconductor integrated circuit devices that are the same as the first semiconductor integrated circuit device 11 may be layered on top of each other. By providing such a multilayer structure, a multilayer semiconductor integrated circuit device with the first semiconductor integrated circuit device 11 being a nonvolatile memory and the second semiconductor integrated circuit device 12 being a controller chip can be implemented.
The first p type semiconductor region 41 may be electrically isolated from the first p type semiconductor substrate 21 by means of an n type separation layer, whereas the n type separation layer may be exposed from the rear surface of the first p type semiconductor substrate 21.
The second n type through semiconductor region 61 may be arranged between the first n type through semiconductor region 51 and the first n type semiconductor region 31. In this case, the first n type through semiconductor region 51 that is connected to the potential of a grounded power supply absorbs the collector current from the parasitic bipolar transistor with the first n type region 31 being the collector, and therefore, the parasitic bipolar transistor can be effectively prevented from being turned on.
Alternatively, the first p type semiconductor region 41 may be arranged between the first n type through semiconductor region 51 and the first n type semiconductor region 31. In this case, the parasitic bipolar transistor with the first n type region 31 being the collector has a long base, and therefore, the current amplification effects of the parasitic bipolar transistor can be made small.
The first semiconductor integrated circuit device 11 and the second semiconductor integrated circuit device 12 may be provided with a coil for transmitting and receiving a signal. Thus, it is desirable to use inductive coupling through coils for the transmission and reception of a signal. That is to say, in the case where through semiconductor regions are used as signal wires, the signal delay due to their resistance values makes high speed data communication impossible, and therefore, inductive coupling data communication through coils, which makes electrical signal wires unnecessary, becomes optimal.
When semiconductor integrated circuit devices are layered on top of each other, the first semiconductor integrated circuit device 11 is fixed to a support substrate, and after that is polished so that the thickness is reduced to approximately 2 μm to 4 μm and the through semiconductor regions (51, 61) are exposed. Next, the second semiconductor integrated circuit device 12 having the same or a different element structure may be layered on the first semiconductor integrated circuit device 11 in such a manner that the surface electrodes (92, 102) make contact with the rear surface of the through semiconductor regions (51, 61). In the case where another semiconductor integrated circuit device is layered, the second semiconductor integrated circuit device 12 may also be polished so that the high impurity concentration regions become through semiconductor regions. Here, the through semiconductor regions are high impurity concentration regions, and therefore, contact electrodes may be made of Al, Cu or W. Chips during the layering process require no pads, for example, and therefore, surface electrodes may be formed in the uppermost layer of multilayer wires formed of Cu. Here, a multilayer structure made of a contact layer (TiN, TaN)/a barrier layer (TiW, TaN)/a metal may be adopted in order to achieve a good ohmic contact.
This layering process may be carried out at the wafer stage or after the chips have been cut out. Furthermore, wafers that have been reconstructed through KGD (Known Good Die) may be used as the wafers. That is to say, good chips are found on the wafer through testing, individual chips are cut out through dicing and sorted out so as to discard the defective chips, and only the good chips are realigned on a support substrate in a wafer form so as to be fixed with an adhesive, and thus, a wafer may be reconstructed.
Next, the multilayer semiconductor integrated circuit device according to Example 1 of the present invention is described in reference to
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrate in
As described above, in Example 1 of the present invention, the n++ type well region that has been doped with P so as to be a high impurity concentration well region that cannot be expected as a through wire according to the prior art is used as a power supply wire for the multilayer semiconductor integrated circuit device, and therefore, a step can be prevented from being created at the time of polishing on the rear surface. In the same manner as TSV, it is not necessary to shift the chips when the chips are layered on top of each other. In addition, it is not necessary to insert a TAB between the chips, and therefore, the size can be made smaller three-dimensionally.
As illustrated in
Next, the multilayer semiconductor integrated circuit device according to Example 2 of the present invention is described in reference to
Thus, the chip in the final layer needs not to transfer the power supply to the next layer, and therefore does not need a high purity well region. Accordingly, in the case where layered chips include a chip having different properties, the chip having different properties can be arranged in the final layer. The process for forming an n++ type well region becomes unnecessary in the chip that forms the final layer, and therefore, it becomes possible to reduce the manufacturing costs.
Next, the multilayer semiconductor integrated circuit device according to Example 3 of the present invention is described in reference to
The junctions at this time are normal temperature junctions under pressure between the metals of the rear surface electrodes 60, 61 and the front surface electrodes 48, 49 after the surfaces of the metals have been activated, that is to say, junctions by means of solid phase welding through intermetal diffusion. Thus, it is possible to layer chips on top of each other even when rear surface electrodes are provided on each chip by using solid state welding through intermetal diffusion.
Next, the multilayer semiconductor integrated circuit device according to Example 4 of the present invention is described in reference to
The junctions at this time are made by means of solid phase welding where the silicon and the silicon oxide film diffuse. Thus, surface plugs electrodes 63 and 64 can be provided on the front surface side of the semiconductor integrated circuit device in the second or higher layer so that the electrical connection with the multilayer integrated circuit device in the first layer can be established without fail.
Next, the multilayer semiconductor integrated circuit device according to Example 5 of the present invention is described in reference to
In Example 5, the n type deep well region 65 has been polished so as to be thinner until the bottom thereof is exposed from the polished surface; however, the p type well region 34 that is an element formation region is not directly exposed, and therefore, the element properties are only affected microscopically.
Next, the multilayer semiconductor integrated circuit device according to Example 6 of the present invention is described in reference to
In the controller chip in this case, an n++ type well region 72 is provided in a p− type Si substrate 71 in the same location as the n++ type well region 32 that is provided in the memory chips, and an n++ type well region 73 is provided in the same location as the n++ type well region 33. Next, a p type well region 74 and an n type well region 75 that become element formation regions are formed in the p− type Si substrate 71. At this time, p+ type substrate contact regions 81 and 82 are formed around the periphery of the n++ type well regions 72 and 73. Next, a p+ type contact region 76 is formed in the p type well region 74, and at the same time, n type regions 77 and 78 that become a source region or a drain region are formed, and a gate electrode (not shown) is provided so as to form an n channel MOSFET. Meanwhile, an n+ type contact region 79 is formed in the n type well region 75, and at the same time, a p type region 80 that becomes a source region or a drain region is formed, and a gate electrode (not shown) is provided so as to form a p channel MOSFET.
Next, contact electrodes 83 and 84 made of Cu are formed on the surface of the n++ type well region 72 and the n++ type well region 73, and at the same time, a multilayer wiring technology is used to form a wire layer 86, 87. Next, a surface electrode 89 made of Al, Cu or W that is connected to the contact electrode 83 and a surface electrode 90 made of Al, Cu or W that is connected to the contact electrode 84 are formed.
At this time, a communication coil 91 for inductive coupling data communication is formed by using multilayer wires in such a manner that the location thereof becomes the same as that of the communication coil 66 provided in the memory chip when the chips are layered on top of each other. In addition, polishing is carried out in order to flatten the surface. Here, the numbers 85 and 88 in the figure are interlayer insulating films made of SiO2.
Next, the rear surface of the p− type Si substrate 71 that forms the controller chip is fixed onto a package substrate 51 using an adhesive 52. After that, the power supply pad 53 for grounding and the surface electrode 58 that is connected to the n++ type well region 32 are connected through a bonding wire 55. Meanwhile, the power supply pad 54 to which VDD is to be applied and the surface electrode 49 that is connected to the n++ type well region 33 are connected through a bonding wire 56, and thus, the basic structure of the multilayer semiconductor integrated circuit device according to Example 6 of the present invention is complete.
As described above, in Example 6 of the present invention, a technology for making layers thinner and a multilayer technology are combined for use to make it possible to implement at low costs a compact semiconductor memory device where a memory chip and a controller chip for driving and controlling the memory chip are layered.
Next, the multilayer semiconductor integrated circuit device according to Example 7 of the present invention is described in reference to
The layered wafer is removed from the support substrate and is divided into chips of a predetermined size. After that, surface electrodes 89 and 90 of a controller chip are deposited onto a GND pad 93 and a VDD power supply pad 94 on top of a package substrate 91 through bumps 92, and as a result, the basic structure of the multilayer semiconductor integrated circuit device according to Example 7 of the present invention is complete. At this time, the space between a package substrate 91 and the controller chip is filled with an underfill resin (not shown). Here, the number 95 in the figure is a signal pad, which is connected to a pad (not shown) provided on the surface of the controller chip through a bump 92.
In Example 7 of the present invention, the controller chip is electrically connected to the package substrate through pads without using a bonding wire, and therefore, space for arranging bonding wires becomes unnecessary, which makes it possible to reduce the space.
Next, the multilayer semiconductor integrated circuit device according to Example 8 of the present invention is described in
In this case, as illustrated in
Next, the multilayer semiconductor integrated circuit device according to Example 9 of the present invention is described in reference to
In this case, as illustrated in
Next, the multilayer semiconductor integrated circuit device according to Example 10 of the present invention is described in reference to
As illustrated in
In addition, the p type well region 34 is arranged between the n++ type well region 32 and the n type well region 35, and therefore, the base of the parasitic bipolar transistor with the n type well region 35 being the collector becomes long, which can make the current amplification effect of the parasitic bipolar transistor smaller. Here, this effect can be gained in the case where the distance between the n++ type well region 32 and the n type well region 35 is large; however, the p type well region 34 is arranged between the n++ type well region 32 and the n type well region 35 in order to use the space efficiently. This configuration can be applied to Examples 2 through 9.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2017-026977 | Feb 2017 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2018/004788 | 2/13/2018 | WO | 00 |
