The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2017-252427, filed Dec. 27, 2017, the entire contents of which are incorporated herein by reference.
The present invention relates to a multilayer wiring board having asymmetrical structures on a front side and a back side thereof.
Japanese Patent Laid-Open Publication No. 2010-10183 describes a multilayer wiring board having an asymmetrical structure. The entire contents of this publication are incorporated herein by reference.
According to one aspect of the present invention, a multilayer wiring board includes a base substrate including conductor layers and insulating layers formed such that the conductor layers and the insulating layers are laminated alternately and that the conductor layers include a first conductor pattern, an inter-pattern insulating resin layer formed on a surface of the base substrate and including an insulating resin layer and an insulating base material laminated on the insulating resin layer such that resin forming the insulating resin layer is filling gaps formed between portions of the first conductor pattern, and a second conductor pattern formed on an outer layer side of the first conductor pattern such that the inter-pattern insulating resin layer is formed between the first conductor pattern and the second conductor pattern. The base substrate, the inter-pattern insulating resin layer and the second conductor pattern form an antenna portion.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
In the following, the present embodiment is described with reference to
The base substrate 11 includes a core substrate 20 which is formed from a first insulating base material 21 and conductor layers 22 respectively laminated on front and back sides of the first insulating base material 21, and build-up parts (20A, 20B) which are respectively laminated on front and back sides of the core substrate 20. In the first insulating base material 21, through-hole conductors 23 connecting to each other the conductor layer 22 on the front side and the conductor layer 22 on the back side are formed. In each of the build-up parts (20A, 20B), multiple interlayer insulating layers 24 and multiple conductor layers 25 are alternately laminated. In each of the interlayer insulating layers 24, via conductors 27 are formed. The first insulating base material 21 and the interlayer insulating layers 24 are each formed by impregnating a woven fabric of reinforcing fibers (for example, a glass cloth) with a resin. The first insulating base material 21 has a thickness of, for example, about 50-150 μm. Further, the interlayer insulating layers 24 each have a thickness of, for example, about 15-30 μm. The conductor layers (22, 25) are each formed mainly of a copper foil, an electroless copper plating, and an electrolytic copper plating, and each have a thickness of, for example, about 15-20 μm. The core substrate 20 has a thickness of, for example, about 80-190 μm.
In the interlayer insulating resin layer 36, via conductors 27 are formed. Then, due to the via conductors 27, the second conductor layer (37F), and a conductor layer 25 which is an outermost conductor layer on the F surface (11F) side among the conductor layers 25 of the base substrate 11 are connected to each other. The interlayer insulating resin layer 36 is formed by impregnating a woven fabric of reinforcing fibers (for example, a glass cloth) with a resin. Further, a thickness of the interlayer insulating resin layer 36 is substantially the same as that of each of the interlayer insulating layers 24, and is, for example, about 15-30 μm. The conductor layers (37F, 37S) are each formed mainly of a copper foil, an electroless copper plating, and an electrolytic copper plating, and each have a thickness of, for example, about 15-20 μm. The copper foil included in each of the conductor layers (22, 25, 37F, 37S) has a thickness of about 1-5 μm.
Then, an antenna part 50 is formed from the inter-pattern insulating resin layer 30, a first conductor layer 55 which is an outermost conductor layer 25 on the S surface (11S) side among the multiple conductor layers 25 of the base substrate 11, and the second conductor layer (37S). In this structure, the first conductor layer 55 and the second conductor layer (37S) are not electrically connected to each other.
Here, in the wiring board 10 of the present embodiment, the inter-pattern insulating resin layer 30 is formed from a second insulating base material 31, a first insulating resin layer 34 formed on an F surface (31F) side of the second insulating base material 31, and a second insulating resin layer 35 formed on an S surface (31S) side of the second insulating base material 31. The second insulating base material 31, the first insulating resin layer 34 and the second insulating resin layer 35 are each formed by impregnating a woven fabric of reinforcing fibers (for example, a glass cloth) with a resin. Thicknesses of the first insulating resin layer 34 and the second insulating resin layer 35 are each substantially the same as that of each of the interlayer insulating layers 24, and are each, for example, about 15-30 μm. The second insulating base material 31 has a thickness of, for example, about 200-300 μm.
In the wiring board 10 of the present embodiment, the thickness of the second insulating base material 31 is larger than the thickness of any one of the interlayer insulating layers 24 and the first insulating base material 21 of the base substrate 11. Further, the thickness of the second insulating base material 31 is 3 or more times the thickness of each of the interlayer insulating layers (24, 36), the first insulating resin layer 34 and the second insulating resin layer 35. Further, the thickness of the second insulating base material 31 is larger than the thickness of the core substrate 20. However, the thickness of the second insulating base material 31 may be smaller than or the same as the thickness of the core substrate 20.
Further, the entire F surface (31F) and S surface (31S) of the second insulating base material 31 are rough surfaces. That is, all surfaces of the second insulating base material 31 that are respectively bonded to the first insulating resin layer 34 and the second insulating resin layer 35 are rough surfaces. Roughness of each of the F surface (31F) and the S surface (31S) of the second insulating base material 31 is larger than 0.1-1.0 μm.
As illustrated in
To manufacture the wiring board 10, first, the base substrate 11 (see
(A1) A copper-clad laminated plate (21K) illustrated in
(A2) Through holes (23A) penetrating the copper-clad laminated plate (21K) are formed by subjecting the front and back sides of the copper-clad laminated plate (21K) to laser processing (see
(A3) An electroless plating treatment is performed. An electroless plating film (not illustrated in the drawings) is formed on the copper foil (22C) and on inner surfaces of the through holes (23A). Next, a plating resist 40 of a predetermined pattern is formed on the electroless plating film on the copper foil (22C) (see
(A4) An electrolytic plating treatment is performed. The through-hole conductors 23 are formed by filling the through holes (23A) with electrolytic plating, and an electrolytic plating film 29 is formed in a non-forming portion of the plating resist 40 on the electroless plating film (not illustrated in the drawings) on the copper foil (22C) (see
(A5) The plating resist 40 is removed, and the electroless plating film (not illustrated in the drawings) and the copper foil (22C) under the plating resist 40 are removed. Then, the conductor layers 22 are respectively formed on the front and back sides of the first insulating base material 21 by the remaining electrolytic plating film 29, electroless plating film and copper foil (22C), and the front side conductor layer 22 and the back side conductor layer 22 are connected to each other by the through-hole conductors 23 (see
(A6) As illustrated in
(A7) As illustrated in
(A8) An electroless plating treatment is performed. An electroless plating film (not illustrated in the drawings) is formed on the copper foil (25C) and on inner surfaces of the via holes (27H). Next, a plating resist 40 of a predetermined pattern is formed on the electroless plating film (see
(A9) An electrolytic plating treatment is performed. As illustrated in
(A10) The plating resist 40 is removed, and the electroless plating film (not illustrated in the drawings) and the copper foil (25C) under the plating resist 40 are removed. Then, the conductor layers 25 are respectively formed on the interlayer insulating layers 24 by the remaining electrolytic plating film 29, electroless plating film and copper foil (25C) (see
(A11) By repeating the above-described processes of (A6)-(A10), as illustrated in
(B1) A copper-clad laminated plate (31K) illustrated in
(B2) An etching process is performed to remove the copper foil (32C) on the front and back sides of the copper-clad laminated plate (31K) (see
The descriptions about the methods for manufacturing the base substrate 11 and the second insulating base material 31 are as given above. Next, a method for manufacturing the wiring board 10 using the base substrate 11 and the second insulating base material 31 is described.
The wiring board 10 is manufactured as follows.
(1) As illustrated in
(2) Next, by irradiating CO2 laser to the copper foil (37C) on the F surface (11F) side, tapered via holes (36A) penetrating the copper foil (37C) and the interlayer insulating resin layer 36 are formed. An electroless plating treatment is performed. An electroless plating film (not illustrated in the drawings) is formed on the copper foil (37C) and on inner surfaces of the via holes (36A). Next, a plating resist 40 of a predetermined pattern is formed on the electroless plating film on the copper foil (37C) (see
(3) An electrolytic plating treatment is performed. The via conductors 27 are formed by filling the through holes (36A) with electrolytic plating, and an electrolytic plating film 29 is formed in a non-forming portion of the plating resist 40 on the electroless plating film (not illustrated in the drawings) on the copper foil (37C).
(4) The plating resist 40 is removed, and the electroless plating film (not illustrated in the drawings) and the copper foil (37C) under the plating resist 40 are removed. Then, the conductor layers (37F, 37S) are respectively formed on the interlayer insulating resin layer 36 and the second insulating resin layer 35 by the remaining electrolytic plating film 29, electroless plating film and copper foil (37C), and the conductor layer (37F) on the F surface (11F) side and the conductor layers 25 on the F surface (11F) side of the base substrate 11 are connected to each other by the via conductors 27 (see
(5) As illustrated in
In the wiring board 10 of the present embodiment, the antenna part 50 includes the inter-pattern insulating resin layer 30, and the first conductor layer 25 and the second conductor layer (37S) that are respectively formed on the front and back sides of the inter-pattern insulating resin layer 30. Then, the inter-pattern insulating resin layer 30 has a structure that includes the second insulating base material 31 formed by removing the copper foils (32C, 32C) from the copper-clad laminated plate (31K). That is, the inter-pattern insulating resin layer 30 has the structure that includes the second insulating base material 31 that is already cured. Therefore, a thickness of the second insulating base material 31 can be easily increased. As a result, the wiring board 10 having asymmetrical structures on the front side and the back side can be easily manufactured.
Further, in the wiring board 10 of the present embodiment, when the second insulating base material 31 is formed sufficiently thick, that an electric signal transmitted in the base substrate 11 propagates as a noise to an electric signal transmitted in the second insulating base material 31 is suppressed.
Further, in the wiring board 10 of the present embodiment, the second conductor layer (37S) is formed after the second insulating base material 31 is laminated on the first insulating resin layer 34 filling the gaps between the portions of the first conductor layer 25. As a result, the second conductor layer (37S) can be formed on a flat surface, and thus, desired antenna characteristics can be easily obtained.
As illustrated in
As illustrated in
As illustrated in
It is thought that there is a problem that it is difficult to manufacture a multilayer wiring board having an asymmetrical structure.
A multilayer wiring board according to an embodiment of the present invention has an asymmetrical structure and can be easily manufactured.
A multilayer wiring board according to an embodiment of the present invention includes alternately laminated conductor layers and insulating layers and has an antenna part on one of a front side and a back side. The antenna part includes: a first conductor pattern; a second conductor pattern arranged on an outer layer side of the first conductor pattern; and an inter-pattern insulating layer arranged between the first conductor pattern and the second conductor pattern. The inter-pattern insulating layer includes: an insulating resin layer; and an insulating base material laminated on the insulating resin layer. A resin forming the insulating resin layer enters into gaps between portions of the first conductor pattern.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
Number | Date | Country | Kind |
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2017-252427 | Dec 2017 | JP | national |