Patent Application
20240290835
For the past several decades, the scaling of features in integrated circuit (IC) structures has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize every portion of an IC structure becomes increasingly significant.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
For purposes of illustrating nanoribbon-based transistors with etch stop layer to assist subfin removal, described herein, it might be useful to first understand phenomena that may come into play during IC fabrication. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
Non-planar transistors such as double-gate transistors, tri-gate transistors, FinFETs, and nanowire/nanoribbon/nanosheet transistors refer to transistors having a non-planar architecture. In comparison to a planar architecture where the transistor channel has only one confinement surface, a non-planar architecture is any type of architecture where the transistor channel has more than one confinement surfaces. A confinement surface refers to a particular orientation of the channel surface that is confined by the gate field. Non-planar transistors potentially improve performance relative to transistors having a planar architecture, such as single-gate transistors.
Nanoribbon-based transistors may be particularly advantageous for continued scaling of complementary metal-oxide-semiconductor (CMOS) technology nodes due to the potential to form gates on all four sides of a channel material (hence, such transistors are sometimes referred to as “gate all around” transistors). As used herein, the term “nanoribbon” refers to an elongated structure of a semiconductor material having a longitudinal axis parallel to a support structure (e.g., a substrate, a die, a chip, or a wafer) over which such a structure is built. Typically, a length of a such a structure (i.e., a dimension measured along the longitudinal axis, shown in the present drawings to be along the y-axis of an example x-y-z coordinate system) is greater than each of a width (i.e., a dimension measured along the x-axis of the example coordinate system shown in the present drawings) and a thickness/height (i.e., a dimension measured along the z-axis of the example coordinate system shown in the present drawings). In some settings, the terms “nanoribbon” or “nanosheet” have been used to describe elongated semiconductor structures that have a rectangular transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe similar elongated structures but with circular transverse cross-sections. In the present disclosure, the term “nanoribbon” is used to refer to all such nanowires, nanoribbons, and nanosheets, as well as elongated semiconductor structures with a longitudinal axis parallel to the support structures and with having transverse cross-sections of any geometry (e.g., transverse cross-sections in the shape of an oval or a polygon with rounded corners). A transistor may then be described as a “nanoribbon-based transistor” if the channel of the transistor is a portion of a nanoribbon, i.e., a portion around which a gate stack of a transistor may wrap around. The semiconductor material in the portion of the nanoribbon that forms a channel of a transistor may be referred to as a “channel material,” with source and drain (S/D) regions of a transistor provided on either side of the channel material.
Typically, nanoribbon-based transistor arrangements include stacks of nanoribbons, where each stack includes two or more nanoribbons stacked above one another, with a single gate stack that includes a work function material provided for an entire stack or multiple stacks. Optionally, the gate stack may also include a gate dielectric material around each nanoribbon. Such nanoribbon-based transistor arrangements may be fabricated by, first, providing a stack of alternating layers of first and second semiconductor materials over a support (e.g., a substrate, a die, a wafer, or a chip). The first semiconductor material is a material that will later form nanoribbons, while the second semiconductor material is a material that is etch-selective with respect to the first semiconductor material so that it may later be removed to separate different nanoribbons of a stack from one another. For example, the first semiconductor material may be silicon, while the second semiconductor material may be silicon germanium. In such a fabrication process, the first semiconductor material provides the bottom layer of the stack as well two or more layers above the bottom layer, alternating with layers of the second semiconductor material. The fabrication process further includes patterning the stack of alternating layers, as well as, possibly, an upper portion of the support into a fin to define the width of future nanoribbons. Sidewalls of a bottom portion of the fin are enclosed by an insulator material commonly referred to as a “shallow trench insulator” (STI) and such a bottom portion of the fin enclosed by the STI is commonly referred to as a “subfin,” similar to a subfin portion of fin-based transistors. The subfin may include the bottom layer of the first semiconductor material of the stack and an upper portion of the support over which the stack was provided. The fabrication process further includes removing the second semiconductor material from the fin to release nanoribbons formed by the fin portions of the first semiconductor material above the subfin. After the nanoribbons are released, a gate stack is provided around portions of the nanoribbons formed of the higher levels of the first semiconductor material, while the first semiconductor material in the subfin portion of the fin remains but does not serve as a part of the nanoribbon-based transistors.
Embodiments of the present disclosure are based on recognition that performance of IC structures with nanoribbon-based transistors may be improved if some or all of the subfin resulting from conventional fabrication approaches to forming nanoribbon-based transistors could be removed. In particular, inventors of the present disclosure realized that, since the subfin is formed of the first semiconductor material, it may increase parasitic capacitance and compromise performance of IC structures in terms of frequency and/or speed of operation. Inventors further realized that removing the subfin from under the stack of nanoribbons is not trivial and may easily result in drive degradation and undesirable threshold voltage shifts in nanoribbon-based transistors.
Disclosed herein are fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors. The methods are based on providing, after the nanoribbons have been released, an etch stop layer over the surface of the subfin and the insulator material surrounding sidewalls of the subfin. After that, the back side of the substrate on which the nanoribbons were formed may be thinned until the bottom of the subfin is exposed, and then an etch may be performed to remove some or all of the material of the subfin without substantially removing the insulator material surrounding the sidewalls of the subfin. The etch stop layer at the top of the subfin will then prevent the etch from damaging the nanoribbons because the etch will not be able to continue past the etch stop layer. Fabrication methods disclosed herein allow removing some or all of the subfin in a manner that may reduce or eliminate drive degradation and undesirable threshold voltage shifts in nanoribbon-based transistors.
An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.
IC structures as described herein, in particular IC structures with nanoribbon-based transistors and an etch stop layer below the nanoribbons (i.e., the etch stop layer that was used to assist subfin removal according to the fabrication methods described herein), may be implemented in one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. In some embodiments, IC structures as described herein may be included in a radio frequency IC (RFIC), which may, e.g., be included in any component associated with an IC of an RF receiver, an RF transmitter, or an RF transceiver, e.g., as used in telecommunications within base stations (BS) or user equipment (UE). Such components may include, but are not limited to, power amplifiers, low-noise amplifiers, RF filters (including arrays of RF filters, or RF filter banks), switches, upconverters, downconverters, and duplexers. In some embodiments, IC structures as described herein may be included in memory devices or circuits. In some embodiments, IC structures as described herein may be employed as part of a chipset for executing one or more related functions in a computer.
For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value, e.g., within +/−5% of a target value, based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−10% of a target value, e.g., within +/−5% of a target value, based on the context of a particular value as described herein or as known in the art.
In the following description, references are made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,
In the drawings, while some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the fabricating processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of nanoribbon-based transistors with an etch stop layer below the nanoribbons as described herein.
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. These operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. The terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. Although some materials may be described in singular form, such materials may include a plurality of materials, e.g., a semiconductor material may include two or more different semiconductor materials.
The nanoribbon 104 may take the form of a nanowire or nanoribbon, for example. In some embodiments, an area of a transversal cross-section of the nanoribbon 104 (i.e., an area in the x-z plane of the example coordinate system x-y-z shown in
In various embodiments, the semiconductor material of the nanoribbon 104 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the nanoribbon 104 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the nanoribbon 104 may include a combination of semiconductor materials. In some embodiments, the nanoribbon 104 may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the nanoribbon 104 may include a compound semiconductor with a first sub-lattice of at least one element from group Ill of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).
For some example N-type transistor embodiments (i.e., for the embodiments where the transistor 110 is an N-type metal-oxide-semiconductor (NMOS) transistor), the channel material of the nanoribbon 104 may include a III-V material having a relatively high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material of the nanoribbon 104 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). For some example P-type transistor embodiments (i.e., for the embodiments where the transistor 110 is a P-type metal-oxide-semiconductor (PMOS) transistor), the channel material of the nanoribbon 104 may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material of the nanoribbon 104 may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7.
In some embodiments, the channel material of the nanoribbon 104 may be a thin-film material, such as a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, if the transistor formed in the nanoribbon is a thin-film transistor (TFT), the channel material of the nanoribbon 104 may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, Nor P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, the channel material of the nanoribbon 104 may have a thickness between about 5 and 75 nanometers, including all values and ranges therein. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, which allows depositing the channel material within the thermal budgets imposed on back end fabrication to avoid damaging other components, e.g., front end components such as the logic devices.
A gate stack 106 including a gate electrode material 108 and, optionally, a gate dielectric material 112, may wrap entirely or almost entirely around a portion of the nanoribbon 104 as shown in
The gate electrode material 108 may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor 110 is a PMOS transistor or an NMOS transistor (P-type work function metal used as the gate electrode material 108 when the transistor 110 is a PMOS transistor and N-type work function metal used as the gate electrode material 108 when the transistor 110 is an NMOS transistor). For a PMOS transistor, metals that may be used for the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further layers may be included next to the gate electrode material 108 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.
In some embodiments, the gate dielectric material 112 may include one or more high-k dielectrics including any of the materials discussed herein with reference to the insulator material that may surround portions of the transistor 110. In some embodiments, an annealing process may be carried out on the gate dielectric material 112 during fabricate of the transistor 110 to improve the quality of the gate dielectric material 112. The gate dielectric material 112 may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 3 nanometers, including all values and ranges therein (e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers). In some embodiments, the gate stack 106 may be surrounded by a gate spacer, not shown in
In some embodiments, e.g., when the transistor 110 is a storage transistor of a hysteretic memory cell (i.e., a type of memory that functions based on the phenomenon of hysteresis), the gate dielectric 112 may be replaced with, or complemented by, a hysteretic material. In some embodiments, a hysteretic material may be provided as a layer of a ferroelectric (FE) or an antiferroelectric (AFE) material. Such an FE/AFE material may include one or more materials that can exhibit sufficient FE/AFE behavior even at thin dimensions, e.g., such as an insulator material at least about 10% of which is in an orthorhombic phase or a tetragonal phase (e.g., as a material in which at most about 90% of the material may be amorphous or in a monoclinic phase). Some examples of such materials include materials that include hafnium, oxygen, and zirconium (e.g., hafnium zirconium oxide (HfZrO, also referred to as HZO)), materials that include hafnium, oxygen, and silicon (e.g., silicon-doped (Si-doped) hafnium oxide), materials that include hafnium, oxygen, and germanium (e.g., germanium-doped (Ge-doped) hafnium oxide), materials that include hafnium, oxygen, and aluminum (e.g., aluminum-doped (Al-doped) hafnium oxide), and materials that include hafnium, oxygen, and yttrium (e.g., yttrium-doped (Y-doped) hafnium oxide). However, in other embodiments, any other materials which exhibit FE/AFE behavior at thin dimensions may be used to replace, or to complement, the gate dielectric 112, and are within the scope of the present disclosure. The FE/AFE material included in the gate stack 106 may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 10 nanometers, including all values and ranges therein (e.g., between about 1 and 8 nanometers, or between about 0.5 and 5 nanometers). In other embodiments, a hysteretic material may be provided as a stack of materials that, together, exhibit hysteretic behavior. Such a stack may include, e.g., a stack of silicon oxide and silicon nitride. Unless specified otherwise, descriptions provided herein with respect to the gate dielectric 112 are equally application to embodiments where the gate dielectric 112 is replaced with, or complemented by, a hysteretic material.
Turning to the S/D regions 114 of the transistor 110, in some embodiments, the S/D regions may be highly doped, e.g., with dopant concentrations of about 1021 cm−3, in order to advantageously form Ohmic contacts with the respective S/D electrodes, although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Irrespective of the exact doping levels, the S/D regions of a transistor are the regions having dopant concentration higher than in other regions, e.g., higher than a dopant concentration in the transistor channel (i.e., in a channel material extending between the first S/D region 114-1 and the second S/D region 114-2), and, therefore, may be referred to as “highly doped” (HD) regions. Even with doped to realize threshold voltage tuning as described herein, the channel portions of transistors typically include semiconductor materials with doping concentrations significantly smaller than those of the S/D regions 114.
The S/D regions 114 of the transistor 110 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 104 to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the nanoribbon 104 may follow the ion implantation process. In the latter process, portions of the nanoribbon 104 may first be etched to form recesses at the locations of the future S/D regions 114. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 114. In some implementations, the S/D regions 114 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions 114 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 114. In some embodiments, a distance between the first and second S/D regions 114 (i.e., a dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers).
The IC structure 100 shown in
Implementations of the present disclosure may be formed or carried out on any suitable support structure, such as a substrate, a die, a wafer, or a chip. The support structure may, e.g., be the wafer 1500 of
As further shown in
The support 101 is shown in
Although only one nanoribbon 104 is shown in
In addition, the example fabricating method 200 may include other operations not specifically shown in
The method 200 may begin with a process 202 that includes providing alternate layers of first and second semiconductor materials in a stack. An IC structure 302 of
The first semiconductor material 332 may be any of the semiconductor/channel materials described above with reference to the nanoribbon 104. The second semiconductor material 334 may be any suitable material that is etch-selective with respect to the first semiconductor material 332 so that, in a later process, the second semiconductor material 334 may be etched away to form nanoribbons of the first semiconductor material 332. As known in the art, two materials are said to be “etch-selective” (or said to have “sufficient etch selectivity”) with respect to one another when etchants used to etch one material do not substantially etch the other, enabling selective etching of one material but not the other. For example, in some embodiments, the first semiconductor material 332 may be silicon while the second semiconductor material 334 may be silicon germanium. It should be noted that while the present disclosure refers to the second semiconductor material 334, descriptions provided herein are equally applicable to the layers shown as layers of the second semiconductor material 334 being made of a non-semiconductor material, e.g., of an insulator material, as long as this material is sufficiently etch-selective with respect to the first semiconductor material 332. Thus, material 334 may be any suitable sacrificial material that is etch-selective with respect to the first semiconductor material 332. Selecting the material 334 to be a semiconductor material may be particularly advantageous because it may improve quality of the first semiconductor material 332 if the first semiconductor material 332 is epitaxially grown on the material 334. Thus, in some embodiments, the process 202 may include epitaxially growing layers of the first semiconductor material 332 and the second semiconductor material 334 in an alternating manner. In other embodiments, alternate layers of the first semiconductor material 332 and the second semiconductor material 334 may be provided in the process 202 using other techniques, such as layer transfer or thin-film deposition. Although
In some embodiments, a thickness 333 of the bottom layer of the second semiconductor material 334 may be greater than a thickness 337 of subsequent layers of the second semiconductor material 334, which may be advantageous in terms of enlarging the process window for hard mask to recess between the bottom nanowire and the subfin. For example, the thickness 333 may be between about 5 and 80 nanometers. On the other hand, the thickness 337 may be between about 5 and 30 nanometers. A thickness 335 of various layers of the first semiconductor material 332 may be that of the thickness of the nanoribbons 104, e.g., between about 5 and 75 nanometers.
The method 200 may then proceed with a process 204 that includes forming the stack of alternate layers of first and second semiconductor materials into a fin. An IC structure 304 of
The IC structure 304 further illustrates a further material 338. The further material 338 may represent a replacement metal gate as known in the art and may include any suitable materials, such as polysilicon.
The method 200 may then proceed with a process 206 that includes exposing a portion of the fin where the gate will be formed, i.e., exposing a portion of the fin above the subfin portion. An IC structure 306 of
The method 200 may then include a process 208, in which the second semiconductor material is removed to release the nanoribbons. An IC structure 308 shown in
Processes 202-208 of the method 200 provide one example of how a stack of released nanoribbons with gate regions exposed for providing a gate metal may be fabricated. In other embodiments, other processes known in the art for providing a stack of released nanoribbons may be used, e.g., any processes of replacement metal gate (RMG) techniques and are within the scope of the present disclosure. The nanoribbons may be described as “released” when openings are formed around channel portions of the nanoribbons, the openings defining areas where gate electrode materials are to be deposited.
The method 200 may then proceed with a process 210 that includes depositing an etch stop layer over all exposed surfaces of the IC structure resulting from the process 208. An IC structure 310 of
The method 200 may further include a process 212, in which a mask material is provided over the IC structure resulting from the process 210. An IC structure 312 shown in
The method 200 may then include a process 214, in which the mask material provided in the previous process is recessed to expose nanoribbons while still covering the subfin 342 and the etch stop layer 116 that is on the subfin 342 and on the insulator material 336. An IC structure 314 shown in
The method 200 may then proceed with a process 216 that includes removing the etch stop layer 116 not protected by the recessed mask material 346. An IC structure 316 of
The method 200 may further include a process 218, in which the remainder of the mask material 346 is removed. An IC structure 318 of
Next, the method 200 includes a process 220 of depositing a gate dielectric over exposed surfaces of the IC structure resulting from the process 218. An IC structure 320 of
After the gate dielectric material, a gate electrode material may be deposited in a process 222 of the method 200. An IC structure 322 of
The method 200 may further include a process 224, in which the support 101 is removed to expose the back side of the first semiconductor material 332 of the subfin 342. An IC structure 324 of
Removing the support 101 exposes the first semiconductor material 332 of the subfin 342, which may then be etched in a process 226 of the method 200. An IC structure 326 of
The method 200 may further include depositing a replacement material 350 in the opening 348 and, optionally, at the back side of the insulator material 336. An IC structure 328 of
Performing the method 200 will result in several characteristic features in the IC structure 100/328 which would not be seen in IC structures with conventional nanoribbon-based transistors. For example, because the replacement material 350 is deposited to replace the subfin 342 of the fin 340 that was formed earlier in the method 200, the replacement structure 102 will be aligned with at least the bottom nanoribbon 104 of the stack of nanoribbon 104. Having a replacement structure 102 of an insulator material at the bottom of the nanoribbons 104 and substantially aligned in the direction of the x-axis is characteristic of the method 200. The replacement structure 102 may be seen as a trench in the insulator material 336, filled with an insulator material that may have same or different material composition.
The replacement structure 102 may extend along the entire length of the nanoribbons 104, as is seen in the perspective illustration of
Nanoribbon-based transistors with etch stop layer as described herein (e.g., as described with reference to
The IC structures 100 disclosed herein may be included in any suitable electronic component.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors) of the device region 1604 through one or more interconnect layers disposed on the device region 1604 (illustrated in
The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in
In some embodiments, the interconnect structures 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the base 102 upon which the device region 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in
A first interconnect layer 1606 may be formed above the device region 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., contacts to the S/D regions 114 of the IC structures 100) of the device region 1604.
A second interconnect layer 1608 may be formed above the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
A third interconnect layer 1610 (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device region 1604) may be thicker.
The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In
The package substrate 1652 may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, glass, an organic material, an inorganic material, combinations of organic and inorganic materials, embedded portions formed of different materials, etc.), and may have conductive pathways extending through the dielectric material between the face 1672 and the face 1674, or between different locations on the face 1672, and/or between different locations on the face 1674. These conductive pathways may take the form of any of the interconnects 1628 discussed above with reference to
The package substrate 1652 may include conductive contacts 1663 that are coupled to conductive pathways (not shown) through the package substrate 1652, allowing circuitry within the dies 1656 and/or the interposer 1657 to electrically couple to various ones of the conductive contacts 1664 (or to devices included in the package substrate 1652, not shown).
The IC package 1650 may include an interposer 1657 coupled to the package substrate 1652 via conductive contacts 1661 of the interposer 1657, first-level interconnects 1665, and the conductive contacts 1663 of the package substrate 1652. The first-level interconnects 1665 illustrated in
The IC package 1650 may include one or more dies 1656 coupled to the interposer 1657 via conductive contacts 1654 of the dies 1656, first-level interconnects 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660 may be coupled to conductive pathways (not shown) through the interposer 1657, allowing circuitry within the dies 1656 to electrically couple to various ones of the conductive contacts 1661 (or to other devices included in the interposer 1657, not shown). The first-level interconnects 1658 illustrated in
In some embodiments, an underfill material 1666 may be disposed between the package substrate 1652 and the interposer 1657 around the first-level interconnects 1665, and a mold compound 1668 may be disposed around the dies 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the mold compound 1668. Example materials that may be used for the underfill material 1666 and the mold compound 1668 are epoxy mold materials, as suitable. Second-level interconnects 1670 may be coupled to the conductive contacts 1664. The second-level interconnects 1670 illustrated in
The dies 1656 may take the form of any of the embodiments of the die 1502 discussed herein (e.g., may include any of the embodiments of the IC device 1600). In embodiments in which the IC package 1650 includes multiple dies 1656, the IC package 1650 may be referred to as a multi-chip package (MCP). The dies 1656 may include circuitry to perform any desired functionality. For example, or more of the dies 1656 may be logic dies (e.g., silicon-based dies), and one or more of the dies 1656 may be memory dies (e.g., high-bandwidth memory).
Although the IC package 1650 illustrated in
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.
The IC device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in
In some embodiments, the package interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to through-silicon vias (TSVs) 1706. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in
Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in
The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic RAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).
In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications.
The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).
The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.
The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC structure that includes: a stack, including a plurality of nanoribbons vertically stacked above one another; a gate electrode material enclosing the nanoribbons in a portion of the stack; a subfin replacement structure including an insulator material, where the subfin replacement structure is below and substantially aligned with a bottom nanoribbon of the stack; and an etch stop layer between the subfin replacement structure and the gate electrode material.
Example 2 provides the IC structure according to example 1, where the insulator material is a first insulator material, and the IC structure further includes a second insulator material on at least portions of sidewalls of the subfin replacement structure.
Example 3 provides the IC structure according to example 2, where the first insulator material and the second insulator material have different material compositions.
Example 4 provides the IC structure according to examples 2 or 3, where the subfin replacement structure is a trench in the second insulator material.
Example 5 provides the IC structure according to any one of examples 2-4, where the etch stop layer is further between the second insulator material and the gate electrode material.
Example 6 provides the IC structure according to example 5, further including a gate dielectric material between the etch stop layer and the gate electrode material.
Example 7 provides the IC structure according to example 6, where a portion of the etch stop layer is between the second insulator material and a portion of the gate dielectric material.
Example 8 provides the IC structure according to example 7, where a further portion of the etch stop layer is between the first insulator material and a further portion of the gate dielectric material.
Example 9 provides the IC structure according to any one of the preceding examples, where the etch stop layer is etch-selective with respect to a semiconductor material of the nanoribbons.
Example 10 provides the IC structure according to any one of the preceding examples, where the etch stop layer includes aluminum and oxygen.
Example 11 provides the IC structure according to any one of the preceding examples, where the etch stop layer has a thickness between about 1 and 10 nanometers.
Example 12 provides the IC structure according to any one of the preceding examples, where the subfin replacement structure is substantially aligned with the bottom nanoribbon of the stack in a direction that is in a plane perpendicular to a longitudinal axis of the bottom nanoribbon of the stack and is perpendicular to a vertical axis along which the nanoribbons are stacked above one another (i.e., in a direction of the x-axis of the example coordinate system shown in the present drawings).
Example 13 provides an IC structure that includes: a nanoribbon including one or more semiconductor materials; a transistor, where a channel region of the transistor includes a portion of the nanoribbon; a first layer of a gate dielectric material, where the first layer at least partially wraps around the channel region of the transistor; a gate electrode material at least partially wrapping around the first layer; a second layer of the gate dielectric material; an intermediate material; and an insulator material, where the gate electrode material is between the second layer and the first layer, the second layer is between the intermediate material and the second layer, and the intermediate material is between the insulator material and the second layer.
Example 14 provides the IC structure according to example 13, where the intermediate material includes a material that is etch-selective with respect to the one or more semiconductor materials.
Example 15 provides the IC structure according to examples 13 or 14, where the intermediate material includes a material that is etch-selective with respect to the insulator material.
Example 16 provides the IC structure according to any one of examples 13-15, where the intermediate material includes a metal and either oxygen or nitrogen.
Example 17 provides the IC structure according to any one of examples 13-16, where one side of the intermediate material is in physical contact with the second layer and another side of the intermediate material is in physical contact with the insulator material.
Example 18 provides a method of fabricating an IC structure, the method including: providing a stack of nanoribbons above a subfin, wherein the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.
Example 19 provides the method according to example 18, where the etch stop layer includes a material that is etch-selective with respect to the subfin.
Example 20 provides the method according to examples 18 or 19, where the etch stop layer includes a material that is etch-selective with respect to the nanoribbons.
Example 21 provides the method according to any one of examples 18-20, where the IC structure is an IC structure according to any one of the preceding examples.
Example 22 provides an IC package that includes an IC die including an IC structure according to any one of examples 1-17; and a further IC component, coupled to the IC die.
Example 23 provides the IC package according to example 22, where the further IC component includes a package substrate.
Example 24 provides the IC package according to example 22, where the further IC component includes an interposer.
Example 25 provides the IC package according to example 22, where the further IC component includes a further IC die.
Example 26 provides a computing device that includes a carrier substrate and an IC structure coupled to the carrier substrate, where the IC structure is an IC structure according to any one of examples 1-17, or the IC structure is included in the IC package according to any one of examples 22-25.
Example 27 provides the computing device according to example 26, where the computing device is a wearable or handheld computing device.
Example 28 provides the computing device according to examples 26 or 27, where the computing device further includes one or more communication chips.
Example 29 provides the computing device according to any one of examples 26-28, where the computing device further includes an antenna.
Example 30 provides the computing device according to any one of examples 26-29, where the carrier substrate is a motherboard.
Example 31 provides the IC structure according to any one of examples 1-17, where the IC structure includes or is a part of a central processing unit.
Example 32 provides the IC structure according to any one of examples 1-31, where the IC structure includes or is a part of a memory device, e.g., a high-bandwidth memory device.
Example 33 provides the IC structure according to any one of examples 1-32, where the IC structure includes or is a part of a logic circuit.
Example 34 provides the IC structure according to any one of examples 1-33, where the IC structure includes or is a part of input/output circuitry.
Example 35 provides the IC structure according to any one of examples 1-34, where the IC structure includes or is a part of an FPGA transceiver.
Example 36 provides the IC structure according to any one of examples 1-35, where the IC structure includes or is a part of an FPGA logic.
Example 37 provides the IC structure according to any one of examples 1-36, where the IC structure includes or is a part of a power delivery circuitry.
Example 38 provides the IC structure according to any one of examples 1-37, where the IC structure includes or is a part of a III-V amplifier.
Example 39 provides the IC structure according to any one of examples 1-38, where the IC structure includes or is a part of PCIE circuitry or DDR transfer circuitry.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
