Patent Application
20230094466
The present invention relates generally to the electrical, electronic and computer arts and, more particularly, to nanosheet field effect transistors.
The well-known field-effect transistor (FET) is a device that uses an electric field to control the flow of current in a semiconductor, and typically includes source, gate, drain (and body) terminals. FET devices control the flow of current by the application of a voltage to the gate, which in turn alters the conductivity in the channel between the drain and source. The fin-type field effect transistor (FinFET) is a multi-gate device, built on a substrate, with the gate placed on two or more sides of the channel or wrapped around the channel, thus forming a multiple-gate structure. FinFET devices have significantly faster switching times and higher current density than planar CMOS (complementary metal-oxide-semiconductor) FET technology.
Further advances beyond FinFETs have been proposed in the form of semiconductor nanowires employed as metal-oxide-semiconductor field-effect transistor (MOSFET) channels which can enable a gate-surrounding structure allowing good electrostatic gate control over the channel for reducing short-channel effects. Similar to lateral nanowire FETs, nanosheet FETs use wider and thicker wires to provide improved electrostatics and drive current.
Buried power rails (BPRs) have been proposed for increased integrated circuit (IC) device density/reduction of standard cell size. However, conventional BPRs may suffer from metal contamination as BPR metal is formed in the early stages of device fabrication (e.g., fin or nanosheet module). Furthermore, in conventional BPR integration, there can be parasitic stress generation in adjacent devices that can harm performance. Furthermore, BPRs integrated below the active device into the substrate can increase substrate-to-BPR parasitic capacitance and negatively impact device performance.
Principles of the invention provide techniques for nanosheet transistors with buried power rails; in a non-limiting example, gate-all-around nanosheet transistors with BPRs and air-gaps. In one aspect, an exemplary semiconductor structure includes a substrate; a first field effect transistor (FET) formed on the substrate and including a first FET first source-drain region, a first FET second source-drain region, a first FET gate between the first and second source-drain regions, and a first FET channel region adjacent the first FET gate and between the first FET first and second source-drain regions; a buried power rail, buried in the substrate, having a top at a level lower than the first FET channel region, and having buried power rail sidewalls; a first FET shared contact electrically interconnected with the buried power rail and the first FET second source-drain region; and a first FET electrically isolating region adjacent the buried power rail sidewalls and separating the buried power rail from the substrate.
In a further aspect, an exemplary semiconductor array structure includes a substrate, and a plurality of field effect transistors formed on the substrate, each including a first source-drain region, a second source-drain region, a gate between the first and second source-drain regions, and a channel region adjacent the gate and between the first and second source-drain regions. The plurality of field effect transistors are arranged in rows; and a plurality of buried power rails are buried in the substrate. Each has a top at a level lower than the channel regions, and each has buried power rail sidewalls. A plurality of shared contacts are electrically interconnected with the buried power rails and the second source-drain regions. Electrically isolating regions are adjacent the buried power rail sidewalls of each of the plurality of buried power rails and separate the buried power rails from the substrate. the buried power rails are located between adjacent rows of the field effect transistors.
In still a further aspect, an exemplary method of forming a semiconductor structure includes epitaxially forming a plurality of nanosheet stacks on a substrate to obtain a first precursor structure. The nanosheet stacks are separated by a plurality of gaps, and the first precursor structure has an outer surface. Further steps include depositing at least one shallow trench isolation liner over the outer surface of the first precursor structure and depositing shallow trench isolation oxide in the plurality of gaps over the at least one liner; replacing the shallow trench isolation oxide in select ones of the plurality of gaps with buried power rails surrounded by electrically isolating regions; and forming a plurality of rows of field effect transistors on the substrate, with the buried power rails located between adjacent rows of the field effect transistors.
As used herein, “facilitating” an action includes performing the action, making the action easier, helping to carry the action out, or causing the action to be performed. Thus, by way of example and not limitation, instructions executing on a processor might facilitate an action carried out by semiconductor fabrication equipment, by sending appropriate data or commands to cause or aid the action to be performed. Where an actor facilitates an action by other than performing the action, the action is nevertheless performed by some entity or combination of entities.
Techniques as disclosed herein can provide substantial beneficial technical effects. Some embodiments may not have these potential advantages and these potential advantages are not necessarily required of all embodiments. By way of example only and without limitation, one or more embodiments may provide one or more of:
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The following drawings are presented by way of example only and without limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:
It is to be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown in order to facilitate a less hindered view of the illustrated embodiments.
Principles of inventions described herein will be in the context of illustrative embodiments. Moreover, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the claims. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.
As noted, further advances beyond FinFETs have been proposed in the form of semiconductor nanowires employed as metal-oxide-semiconductor field-effect transistor (MOSFET) channels which can enable a gate-surrounding structure allowing good electrostatic gate control over the channel for reducing short-channel effects, and, similar to lateral nanowire FETs, nanosheet FETs use wider and thicker wires to provide improved electrostatics and drive current.
Referring now to
In
In
In
For clarity, note that each source/drain region shown on the right-hand side of
Consider now a second exemplary process flow for an exemplary embodiment of nanosheet transistors with buried power rails and an air gap liner. Initial steps are similar to
In
In
Consider now a third exemplary process flow for an exemplary embodiment of nanosheet transistors with buried power rails and an air gap liner, including robust air-gap formation and an air gap localized only in the BPR regions. It should be noted that except to the extent that differences are discussed and pointed out, the steps and corresponding structures of the first, second, and third exemplary process flows are generally similar. Initial steps are similar to
It will thus be appreciated that an exemplary embodiment of a semiconductor structure includes a buried power rail 337, 337′, 337″, 337P, 337P′, formed in between two adjacent nanosheet FETS 355, 355P, 355′, 355P′, and a shared contact 361, 361P, 361′, 361P′, between the source and drain of the transistor and the BPR material. The top of the BPR is located below the bottom of the active channels of the FET. The BPR sidewalls are separated from the FET sub-fin sidewalls by at least one dielectric (e.g., a low-K dielectric or an air gap encapsulated by one or more dielectric materials). One or more embodiments include a BPR integrated in the STI material with a dielectric liner 325, 327 or air gap 3299, 3999, 4611, 4611A, 4611B, on the sidewall.
It will be further appreciated that an exemplary method to form a semiconductor device includes forming a nanosheet epitaxy stack (e.g.
One or more embodiments provide techniques for integrated Buried-Power-Rails (BPR) 337, 337′, 337″, 337P, 337P′, in the Shallow-Trench-Isolation (STI) 341 with a dielectric liner 325, 327 or an air gap 3299, 3999, 4611, 4611A, 4611B, isolating the BPR from the sub-Fin sidewalls and substrate 305 to reduce parasitic capacitance. One or more embodiments thus advantageously include reducing parasitic capacitance in an operating integrated circuit by providing such a structure. In one or more embodiments, the BPR integration is presented for Gate-All-Around (GAA) devices and is compatible with Bottom Dielectric Isolation (BDI) 353, 353′, 353″. The BPR is formed, for example, in place of the STI over the sub-Fin Dielectric liner 325, 327 and in one or more embodiments does not require over etch past the bottom of the STI level. One or more embodiments thus include refraining from such an over-etch. In the case of the air gap (e.g.,
Semiconductor device manufacturing includes various steps of device patterning processes. For example, the manufacturing of a semiconductor chip may start with, for example, a plurality of CAD (computer aided design) generated device patterns, which is then followed by effort to replicate these device patterns in a substrate. The replication process may involve the use of various exposing techniques and a variety of subtractive (etching) and/or additive (deposition) material processing procedures. For example, in a photolithographic process, a layer of photo-resist material may first be applied on top of a substrate, and then be exposed selectively according to a pre-determined device pattern or patterns. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions. The photo-resist may then be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern or photo-mask. The photo-resist pattern or photo-mask may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.
There are numerous techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are referred to generically as “etching”. For example, etching includes techniques of wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE), which are all known techniques to remove select material(s) when forming a semiconductor structure. The Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. The SC2 contains a strong acid such as hydrochloric acid and hydrogen peroxide. The techniques and application of etching is well understood by those skilled in the art and, as such, a more detailed description of such processes is not presented herein.
Although the overall fabrication method and the structures formed thereby are novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to one having ordinary skill in the relevant arts given the teachings herein. For example, the skilled artisan will be familiar with epitaxial growth, self-aligned contact formation, formation of high-K metal gates, and so on. The term “high-K” has a definite meaning to the skilled artisan in the context of high-K metal gate (HKMG) stacks, and is not a mere relative term. Moreover, one or more of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, including, for example: James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001 and P. H. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, which are both hereby incorporated by reference herein. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative, and one skilled in the art may be familiar with several equally suitable alternatives that would be applicable.
It is to be appreciated that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of explanation. This does not imply that the semiconductor layer(s) not explicitly shown are omitted in the actual integrated circuit device.
Given the discussion thus far, it will be appreciated that, in general terms, an exemplary semiconductor structure includes a substrate 305 and a first field effect transistor (FET) (e.g., 1907, 1909, 1907′, 1909′) formed on the substrate and including a first FET first source-drain region (e.g., 355, 355P, 355′, 355P′), a first FET second source-drain region (e.g., 355, 355P, 355′, 355P′), a first FET gate (see, e.g., stacks in
One or more instances further include a second field effect transistor (FET) (e.g., 1907, 1909, 1907′, 1909′), adjacent the first field effect transistor, formed on the substrate, and including a second FET first source-drain region, a second FET second source-drain region, a second FET gate between the second FET first and second source-drain regions, and a second FET channel region adjacent the second FET gate and between the second FET first and second source-drain regions. In this aspect, the buried power rail is located between the adjacent first and second field effect transistors. See, e.g., top views 1901, 1901′.
In some cases (e.g.,
One or more embodiments are implemented in the context of gate all-round nanosheet technology, as shown in the non-limiting exemplary embodiments. Thus, in one or more embodiments, the first field effect transistor channel region includes a first field effect transistor nanosheet channel region; the second field effect transistor channel region includes a second field effect transistor nanosheet channel region; the first field effect transistor gate includes a first field effect transistor all-around gate; and the second field effect transistor gate includes a second field effect transistor all-around gate. However, the skilled artisan will appreciate that techniques disclosed herein can also be employed with, for example, a FinFET that has a fin channel for example.
In another aspect, a semiconductor array structure (e.g.,
In some instances, first adjacent pairs of the rows are n-type 1907, 1907′ and second adjacent pairs of the rows are p-type 1909, 1909′.
As discussed above, the electrically isolating regions can include an electrically insulating dielectric compound and/or encapsulated gaps such as air gaps.
As noted, one or more embodiments are implemented in the context of gate all-round nanosheet technology, as shown in the non-limiting exemplary embodiments. Thus, in one or more embodiments, the channel regions include nanosheet channel regions; and the gates include all-around gates.
In accordance with still another aspect of the invention, an exemplary method of forming a semiconductor structure includes epitaxially forming a plurality of nanosheet stacks 323 on a substrate 305 to obtain a first precursor structure (e.g.
In one or more embodiments, in the step of replacing the shallow trench isolation oxide in the select ones of the plurality of gaps with the buried power rails surrounded by the electrically isolating regions, the electrically isolating regions include at least one electrically insulating dielectric compound (see, e.g.,
In some instances, in the step of replacing the shallow trench isolation oxide in the select ones of the plurality of gaps with the buried power rails surrounded by the electrically isolating regions, the electrically isolating regions each include an encapsulated gap (e.g.,
In some instances, the etching of the at least portion of the shallow trench isolation liner adjacent the buried power rails to form the at least a partial gap includes complete etching (
In some cases, the etching of the at least portion of the shallow trench isolation liner adjacent the buried power rails to form the at least a partial gap includes partial etching to leave an underlying support pedestal (
In some cases, in the step of depositing the at least one shallow trench isolation liner, the at least one shallow trench isolation liner includes a tri-liner (
Those skilled in the art will appreciate that the exemplary structures discussed above can be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare dies, in packaged form, or incorporated as parts of intermediate products or end products.
An integrated circuit in accordance with aspects of the present inventions can be employed in essentially any application and/or electronic system. Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments disclosed herein.
The illustrations of embodiments described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the circuits and techniques described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. It should also be noted that, in some alternative implementations, some of the steps of the exemplary methods may occur out of the order noted in the figures. For example, two steps shown in succession may, in fact, be executed substantially concurrently, or certain steps may sometimes be executed in the reverse order, depending upon the functionality involved. The drawings are also merely representational and are not drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Embodiments are referred to herein, individually and/or collectively, by the term “embodiment” merely for convenience and without intending to limit the scope of this application to any single embodiment or inventive concept if more than one is, in fact, shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that an arrangement achieving the same purpose can be substituted for the specific embodiment(s) shown; that is, this disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those of skill in the art given the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Terms such as “bottom”, “top”, “above”, “over”, “under” and “below” are used to indicate relative positioning of elements or structures to each other as opposed to relative elevation. If a layer of a structure is described herein as “over” another layer, it will be understood that there may or may not be intermediate elements or layers between the two specified layers. If a layer is described as “directly on” another layer, direct contact of the two layers is indicated. As the term is used herein and in the appended claims, “about” means within plus or minus ten percent.
The corresponding structures, materials, acts, and equivalents of any means or step-plus-function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit thereof. The embodiments were chosen and described in order to best explain principles and practical applications, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.
The abstract is provided to comply with 37 C.F.R. § 1.76(b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, the claimed subject matter may lie in less than all features of a single embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.
Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that illustrative embodiments are not limited to those precise embodiments, and that various other changes and modifications are made therein by one skilled in the art without departing from the scope of the appended claims.
