Patent Application
20140283901
The invention relates to semiconductor nanostructures, such as nanowires or nano “flakes”, and is applicable, for example, in photovoltaic devices or the like.
Conventionally, a nanostructure is a material structure having at least one region or characteristic dimension whose size is in the nanometre range (i.e. ˜10−9 m). For example, the structure may be in the form of a plate whose thickness is in the nanometre range. Alternatively, the structure may be substantially one dimensional, wherein its transverse dimension is in the nanometre range. Quasi-one-dimensional nanostructure may be referred to as nanowires.
Growth of semiconductor nanowires was first discussed in 1964 by Wagner and Ellis. The nanowires they grew were catalyzed by means of a liquid gold catalyst particle and a nanowire growth mechanism named Vapour-Liquid-Solid (VLS) growth mechanism. This name derives from the fact that material(s) used for growing the wires are initially in a vapour or gas phase, then become incorporated into the liquid phase of the gold catalyst particle, and finally enter the solid phase in the nanowire itself. Generally, such nanowire growth was characterised by placing one or more gold catalyst particles on a growth substrate and subsequently introducing growth materials into the system, where they would be collected by the gold catalyst particle. At some point the gold particle would become supersaturated with the growth materials and start to nucleate the material underneath itself and in that way “grow” the nanowire. The diameter of the catalyst particle determined the diameter of the nanowire.
For some years, the preferred material for the catalyst has been gold. The growth of both silicon and group III-V semiconductor nanowires by means of gold catalyst particles has been investigated thoroughly and there is a large body of published literature on this topic.
An advantage of the small diameter of nanowires is that it is possible to grow them on non-lattice matched substrates, i.e. on substrates where the distance between the individual atoms in the crystal lattice is different from that in the nanowire. This advantage arises because the small diameter of the nanowire reduces or minimises the strain that it experiences. In an early article [1] describing gold-catalyzed growth of non-lattice matched gallium arsenide phosphide (GaAsP) III-V nanowires on silicon, the growth system used was a metal organic vapour phase epitaxy (MOVPE). Beside MOVPE, it is known how to fabricate group III-V semiconductor nanowires using molecular beam epitaxy (MBE).
Despite the interest in this area, a theoretical understanding of the nanowire growth has not developed to support the experimental data. In 2010, Frank Glas published an article [2] in which he calculated the chemical potential of the gold catalyst droplet as a function of its content of group III and group V atoms. In this article it was shown that the chemical potential of the gold droplet depended significantly on the amount of group V material inside the droplet. The difference in chemical potential of the catalyst droplet and the semiconductor surface it is lying on is a measure of the supersaturation of the droplet and hence the driving force for the nucleation of the nanowire below the droplet. The article included a theoretical calculation to show that, assuming a small amount of group V material was incorporated into the catalyst particle during nanowire growth, the chemical potential of the gold droplet would, for the same amount of group V material, be larger when growing gallium-phosphide (GaP) nanowires than when growing gallium-arsenide (GaAs) nanowires.
Recently a nanowire growth method has been developed which utilizes gallium as the particle for growing gallium-arsenide (GaAs) nanowires. This type of Ga-assisted growth is also know as self-assisted growth. The GaAs nanowires are grown either directly on a silicon substrate or on a substrate having a silicon oxide (SiOx) layer deposited on top prior to the nanowire growth [3, 4, 5]. The typical used crystal orientation of the substrate is (111). The use of gallium droplets to assist growth in this way means that the nanowires can be incorporated more readily onto silicon-based technology because gallium does not affect the electronic and semiconducting properties of silicon in the same way as gold, which can have detrimental effects on the properties of silicon [11].
The gallium-assisted GaAs nanowire growth mechanism is believed to be roughly identical to that of gold-catalyzed growth. It is thought that GaAs nanowire growth is initiated after the free gallium atoms, which move around on the silicon substrate, form gallium droplets, which then are supersaturated by the As material. When the droplets reach a certain critical amount of supersaturation they start to nucleate GaAs underneath. Since new gallium atoms are constantly being incorporated into the droplet during growth, the droplet remains throughout the growth unless the number of new gallium atoms incorporated in the droplet is smaller than the number of As atoms incorporated. It is known that self-assisted GaAs nanowires are preferred for optoelectronic applications [9].
Growth of indium-phosphide InP and InAsP without the use of gold have also been realised [6, 7]. However, at least for the case of InAs it is still debated whether or not a liquid particle is present during growth of the nanowires.
The use of group III-V semiconductor nanostructures in an active layer of a photovoltaic cell is known.
For example, U.S. Pat. No. 7,087,833 discloses a photovoltaic device that includes semiconductor nanostructures as at least a portion of a photoactive layer. Each nanostructure has a core made of a first material (e.g. GaAs) surrounded by a shell made of a second material (e.g. InP) that is different from the first material. The materials are selected to exhibit a type-II band offset profile, whereby one type of charge carrier created by incident light on the nanostructure is conducted through the core and the other type of charge carrier is conducted through the shell.
WO 2008/067824 discloses a photovoltaic device having an active layer in which core-shell type nanostructures having a flake-like (e.g. tapering planar) shape are grown on a substrate. In one example, InAs nanoflakes are grown on an GaAs substrate using a gold-catalysed VLS fabrication method.
At its most general, the present invention provides a technique for fabricating gallium-arsenide-phosphorous (GaAsP) nanostructures using gallium-assisted (Ga-assisted) growth, i.e. without requiring gold catalyst particles. Whereas GaAsP nanostructures (e.g. thin films, nanowires, etc.) are known per se, the present invention teaches the ability to form such GaAsP nanostructures using Ga-assisted growth. As discussed below, the Ga-assisted GaAsP nanostructures of the invention may exhibit properties, e.g. band gap, that make them suitable for use as a junction in a solar cell. In particular, the present invention may provide GaAsP nanostructures to be fabricated with a band gap in the range 1.6 to 1.8 eV (e.g. at and around 1.7 eV).
Relative to conventional gold-assisted growth, Ga-assisted growth may result in fewer impurity atoms in the crystal that forms the nanostructure. In particular, it is known that gold-assisted VLS growth causes Au atoms to be incorporated into the nanostructure [10], which degrades their optoelectronic properties. The present invention enables the growth of GaAsP nanostructures which are completely free from Au impurities. Growth of such nanostructures have not been possible heretofore. The increased purity of the nanostructures of the invention may enable them to behave more efficiently in a solar cell. It is also possible that Ga-assisted growth may result in a more uniform distribution of As and P atoms in the nanostructure than can be produced using the conventional gold-assisted technique.
The direct growth of nanostructures having band gaps around 1.7 eV may be preferred to conventional AlGaAs or GaAsP fabrication techniques for two reasons. Firstly, direct growth may permit doping to be performed as part of the same process. One type of conventional GaAsP growth comprises selectively etching a bulk layer of material to form nanostructures followed by a separate subsequent doping step in order to create a core-shell p-i-n junction. Secondly, direct growth may be more robust with respect to crystal defects than e.g. a known technique of performed selective area GaAsP growth on patterned silicon substrates.
The formation of Ga-assisted GaAsP nanostructures is a non-trivial development from the known techniques of fabricating Ga-assisted GaAs nanostructures due to the unknown effect of phosphorous (P) in the fabrication environment. The present application is based on the discovery that the growth process needs to be controlled in a manner that goes against conventional knowledge in this field in order to generate GaAsP nanostructure growth from gallium droplets. In particular, the theory in existence before the invention was conceived tended to suggest that a much higher chemical potential would be needed in the Ga particle to be supersaturated with P in contrast with As. Accordingly, it was believed that either P would not readily be incorporated with As to supersaturate a Ga particle, or that the chemical potential of the Ga particle would rise so much that it would be completely crystallised and hence terminate growth. As explained below, the present invention has found a balance which unexpectedly enables Ga-assisted GaAsP nanostructure growth.
According to one aspect of the invention, there is provided a GaAsP nanostructure resulting from Ga-assisted growth. The GaAsP nanostructure may be free from gold impurities, i.e. the invention may provide an Au-free GaAsP nanostructure. The nanostructure may be a quasi-one-dimensional nanostructure such as a nanowire, nanoflake, nanorod, nanopillar, nanocone or the like. In one embodiment, the GaAsP nanostructure may be a GaAsP nanowire having a length ranging from a few hundred nanometres to a few micrometres, e.g. from 50 nm to 100 μm, such as 1 to 25 μm, and a maximum traverse dimension in the order of nanometres, e.g. 200 nm or less, preferably less than 150 nm, such as less than 120 nm, e.g. between 20 and 120 nm. The GaAsP nanostructure may be plate-like, e.g. resembling a flake, having a length ranging from a few hundred nanometres to a few micrometres, e.g. between 1 to 25 μm, a width in the range 100 nm to 2 μm, and a thickness in the order of nanometres, e.g. less than 120 nm. For example, the nanostructure may comprise a nanowire extending in a longitudinal direction, wherein the nanowire has a maximum transverse dimension less than 100 nm.
The nanostructure grown from a Ga particle may comprise Ga and group V material comprising As and P, wherein the proportion of As in the group V material is 65% to 90% and the proportion of P in the group V material is 10% to 35%. Preferably the proportion of P in the group V material is 15% to 30%. The nanostructure may also include dopant atoms, e.g. Be or Si or the like.
As mentioned above, the GaAsP in nanostructure may exhibit a band gap in the range 1.6 to 1.8 eV.
In another aspect, the invention may provide a semiconductor device comprising a silicon substrate having a plurality of the GaAsP nanostructures discussed above grown thereon by Ga-assisted growth. For example, the plurality of GaAsP nanostructures may comprise a plurality of nanowires, each nanowire extending in a longitudinal direction from a growth surface of the substrate, the longitudinal direction being offset from, e.g. substantially normal to the surface of the substrate. The surface of the substrate may have a <111> crystal orientation
The semiconductor device of this aspect may find particular use as the active element in a photovoltaic cell, and especially a multi-junction photovoltaic cell. The advantages of using nanostructures over conventional thin film arrangements in photovoltaic cells are well documented, see e.g. WO 2010/120233. An advantage of the present invention is that the silicon substrate on which the GaAsP nanostructures are grown can be used actively in a final device without any detrimental effects caused by diffusion of gold into the silicon that can occur with known Au-assisted GaAsP growth techniques.
In one embodiment of a multi-junction photovoltaic cell, according to the invention, the silicon in the substrate may form a first p-n junction and the GaAsP in the nanostructures forms a second p-n junction. The band gap of the first p-n junction may be different from (e.g. lower than) that of the second p-n junction to enable the cell to generate electricity from a broad range of wavelengths in the light spectrum.
Herein, a p-n junction may mean any arranged of a first region having a first conductivity type (e.g. p-conductivity) with respect to a second region having a second conductivity type different from (e.g. opposite to) the first conductivity type (e.g. n-conductivity) which promotes separation of charge carriers (i.e. electron-hole pairs) created by the absorption of photons in the first or second region to generate a voltage across the cell. For example, the first and second region may contact one another at an interface, thereby creating a p-n junction. Alternatively, in a preferred arrangement, a substantially intrinsic region may be located between the first and second regions to form a p-i-n junction.
In one embodiment, the silicon substrate may comprise a first silicon layer having a first conductivity type, and a second silicon layer having a second conductivity type, the first and second silicon layers being disposed to form the first p-n junction (or p-i-n junction), and each GaAsP nanostructure may have a core region surrounded by a shell region, the core region being formed from one of the first and second conductivity types (e.g. n+-doped GaAsP) and the shell region being formed from the other of the first and second conductivity types (e.g. p+-doped GaAsP) to form a second p-n junction (or p-i-n junction if a region (e.g. an inner shell region) of substantially intrinsic GaAsP is disposed between the core and shell regions).
A third p-n junction (e.g. a tunnel junction) may be provided between the first and second p-n junctions. The third p-n junction is formed in the silicon substrate or in each GaAsP nanostructure or at the interface between the Si substrate and the GaAsP nanostructures.
As is conventional, a first electrical contact may be formed on the back surface of the substrate (i.e. the surface opposite to the surface on which the GaAsP nanostructures are grown), and a second electrical contact may be formed on top and/or around the upper part of the GaAsP nanostructures or around the bottom lower part of the GaAsP nanostructures. The latter configuration may improve light absorption while preserving the carrier collecting properties of the electrode. The second electrical contact may also be formed by overgrowing the nanostructures and the surface between the structures with a conductive layer having suitable properties such that the nanowires are connected by the conductive layer. The conductive layer may then be contacted by a metal grid pattern or the like. The contacts are for connecting the photovoltaic cell to electrical devices to use or store the electricity generated therein. Any suitable conductors may be used. For example, the second electrical contact may comprise a transparent conductor, such as a conducting polymer or a layer of transparent conductive oxide (TCO), e.g. of indium tin oxide (ITO) or the like. The GaAsP nanostructure may be surrounded by (e.g. embedded in) an insulating filler material. Preferably the filler material is transparent to light having wavelengths corresponding to the band gap of the first p-n junction. The filler material may assist the nanostructures in supporting the second electrical contact. The filler may contain material, e.g. silver nanoparticles, which promote the reflection of light into the nanostructures. However, in other embodiments, the nanostructures may be surrounded by air.
The Ga-assisted growth of GaAsP nanostructures according to the invention may use molecular beam epitaxy (MBE) or any other epitaxial growth process capable of utilizing the Ga droplets for growth of nanostructures therefrom. For example, the invention may use metalorganic vapour-phase epitaxy (MOVPE), chemical beam epitaxy (CBE) or the like.
According to a third aspect of the invention, there may be provided a vapour-liquid-solid (VLS) method of growing a GaAsP nanostructure, the method comprising: subjecting a silicon oxide surface layer on a substrate (e.g. a silicon substrate) to a Ga flux to form Ga droplets on the surface layer; subjecting the Ga droplets to the Ga flux and a group V flux to supersaturate the Ga droplets with group V atoms from the group V flux, the group V flux comprising an As flux and, optionally, a P flux; setting a growth temperature, a non-zero proportion of P flux in the group V flux and the Ga flux and the group V flux in a V/III flux ratio to effect growth of a GaAsP nanostructure at each supersaturated Ga droplet. The Ga droplets may be formed when only a Ga flux is present, but this is not essential. If a group V flux is also present, the Ga flux may need to be increased to cause formation of the Ga droplets.
This disclosure is based on the discovery that the proportion of P in the group V flux has an effect on the formation on Ga droplets on the substrate and an unexpected relationship to the amount of P present in produced GaAsP nanostructure. The invention proposes a technique which takes these effects into account, together with growth temperature and V/III flux ratio, during fabrication in order to achieve Ga-assisted GaAsP nanostructure growth.
In one embodiment, the method may include setting the proportion of P flux in the group V flux as a predetermined multiple of the proportion of P relative to the total amount of group V atoms to be present in the grown GaAsP nanostructure. The proportion of P flux in the group V flux affects the proportion of P in the group V atoms of the GaAsP nanostructure in a repeatable manner for given growth conditions (e.g. molecular composition of beam flux, growth temperature, group V/III flux ratio, etc.). Surprisingly, the multiple itself is much lower than what would be expected for conventional GaAsP bulk (i.e. thin film) growth. If the MBE growth technique is used, the multiple may depend on the molecular composition of the P flux and As flux. For example, if the P flux delivers P2 molecules and the As flux in the group V flux delivers As4 molecules, the predetermined multiple may be in the range 0.1 to 2 (preferably 0.25 to 1.5), which may be five to twenty times lower than the equivalent multiple in GaAsP bulk growth. If As2 molecules are used, the parameters may be adapted accordingly since As2 is known to incorporate more effectively into the crystal during growth than As4. For example, the predetermined multiple may be in the range 0.2 to 6 if As2 is used. If the MOVPE growth system is used, there may be a larger amount of carrier gases which can be used to supply the As or P atoms to the growth site. The effectiveness of these carrier gases may vary and therefore the predetermined multiple may be determined from the known effectiveness of each of the carrier gases when used for bulk thin film growth.
The method may including selecting the predetermined multiple based on the growth temperature and the group V/III flux ratio, e.g. to create a GaAsP nanostructure having a desired proportion of P atoms in its group V atoms. For example, if it is desirable to obtain 22% P atoms in the group V atoms of the nanostructure, the method may include determining (e.g. calculating or looking up) the multiple needed to achieve that proportion for a given growth temperature and group V/III flux ratio. For example, if the growth temperature was 630° C. and the group V/III flux ratio 50, the multiple may be determined as 0.55, in which case the proportion of P flux in the group V flux would be set as 12%. Of course, a similar determination may be undertaken to determine the growth temperature and/or group V/III flux ratio to ensure that a given proportion of P flux in the group V flux yields a desired proportion of P atoms in the group V atoms of the grown GaAsP nanostructure.
This may be particularly important if it is desirable to overgrow the nanowire with bulk (thin film) layers of GaAsP, e.g. to form a p-n junction or the like. It may be desirable to match the proportion of P atoms in the group V atoms of the deposited bulk layer with the proportion of P atoms in the group V atoms of the nanowire. Accordingly, it may be necessary to increase or decrease the proportion of P flux in the group V flux for the bulk growth. If the same growth parameters are used, it is likely that the bulk layer will contain less than half (more likely less than a fifth) of the proportion of P atoms that has been obtained in the nanowires.
A non-zero group V flux may be present in addition to the Ga flux during formation of the Ga droplets on the substrate surface. The group V flux may comprise an As flux and/or a P flux. The present disclosure also teaches that the presence of P in the group V flux during Ga droplet formation and growth initiation affects the maximum V/III flux ratio that can be used for a given growth temperature to ensure formation of the Ga droplets. This is important, because it may be desirable to perform Ga-assisted GaAsP nanostructure growth close to the maximum available V/III flux ratio to form high quality nanostructures. The presence of a P flux in the group V flux during Ga droplet formation means that the maximum V/III flux ratio for a given temperature is lower than what can be used for the known Ga-assisted GaAs growth discussed above.
The method may therefore include changing (e.g. increasing) the proportion of P flux in the group V flux after forming the plurality of Ga droplets. That is, a different V/III flux ratio and proportion of P flux in the group V flux may be used when forming the Ga droplets compared with when supersaturating the droplets and initiating growth.
Thin film growth of GaAsP is typically performed at around 450-490° C. Moreover, whilst the amount of P in the thin film increases slightly compared to As with an increase in growth temperature, this effect saturates at substrate temperatures above 550° C. [8]. In contrast, the set growth temperature in the invention may be higher than 550° C., e.g. higher than 620° C. and/or up to 660° C. In one embodiment, the growth temperature may be in the range 620° C. to 660° C. and the V/III flux ratio may be less than 70.
The invention may include forming a passivation layer (e.g. of silicon monoxide or silicon dioxide), on the substrate before subjecting it to the Ga flux. The Ga atoms in the droplet locally dissolve the oxide layer to create contact between the supersaturated Ga droplet and the substrate body (e.g. silicon), whereby GaAsP growth begins. If the GaAsP nanostructure has a core region surrounded by a shell region, the passivation layer may also act to insulate the substrate body (e.g. n-type silicon) from the shell region (e.g. n-type GaAsP) shell, since otherwise it may short to the silicon substrate surface.
Alternatively, the method may include, before subjecting the silicon oxide surface to a Ga flux, etching a plurality of holes in the silicon oxide surface layer to create an array of oxide free holes for receiving the Ga droplets in direct contact with the silicon. Direct contact with the silicon is desirable because it can improve the conversion efficiency between the nanostructure and the silicon, e.g. when used in a solar cell. However, direct contact was undesirable with known Au-catalysed growth, because the Au particles could diffuse into the silicon and adversely affect its properties. The array of oxide free holes may be formed by nanoimprint lithography.
The method may also include doping the nanostructure, e.g. by introducing a dopant flux (e.g. generating a conductivity type other than the grown nanostructure) during growth, or by overgrowing each nanostructure with a doped GaAsP shell (e.g. a coating), and then causing diffusion of doping atoms from the overgrown doped shell into the nanowire.
It is desirable to obtain good crystal quality for the grown nanowires e.g. to facilitate use in solar cells. If the grown nanowires contain crystal defects or changes in the crystal orientation (like twinning defects) the optical-electrical properties of the nanowires themselves may be significantly degraded. During a subsequent shell growth around the nanowires (e.g. to form a p-n junction as discussed above) the crystal defects, or twinning defects, may become further pronounced such that the quality of the grown shell may become significantly worse than the crystal quality of the nanowires. It is therefore very desirable to obtain growth parameters which results in single crystal nanowires without defects. Conventional GaAs nanowires can be grown in a significantly larger parameter space than perfect single crystal GaAs nanowires, so it is a challenge to obtain good crystal quality even for GaAs. The present invention adds P into the nanowire growth, and hence the optimal parameter space becomes even smaller. It is desirable to determine the influence of the phosphorus on critical growth conditions for obtaining good crystal quality, such as supersaturation. Too high a supersaturation may cause twinning defects. High supersaturation can be caused by a high P flux.
Examples of the invention are discussed in detail below with reference to the accompanying drawings, in which:
In the examples of the invention discussed below, molecular beam epitaxy was used as the growth technique. However, the teaching herein may be equally applicable to other epitaxial growth techniques, e.g. MOVPE.
The experimental parameters used for the growths shown in
The two growths shown in
Ga-assisted GaAs nanowire structures are visible as narrow white lines in
The image shown in
From the growths showed in
The experimental parameters used for the growths shown in
The growth conditions in these embodiments, were set to probe the effect of P in the group V material during the initial formation of Ga droplets on the substrate surface followed by the supersaturation of the droplets with group V material. During the subsequent nanowire growth the effect of using Be doping during growth was also tested.
For the growth shown in
At the end of the 5 minute initiation period, i.e. after some Ga droplets with certainty had been formed, the amount of P was increased during supersaturation and nanostructure growth from about 5% up to 50% while the group V/III flux ratio was lowered from 50 to 25. The growth temperature was 628° C. and the growth time was 53 minutes.
For the growth shown in
In this growth, the 2 minute initiation period was followed by more than 60 minutes of growth with a group V/III flux ratio of 40 and 10% P flux in the group V flux.
The starting and growth conditions for the growth shown in
The Ga flux was the same for all three growths.
Based on the results shown in
For Ga-assisted growth the diameter (i.e. transverse dimension) of the Ga-assisted nanowires is determined by the size of the Ga droplet from which it is grown. In turn the size of the droplets may depend on the level of supersaturation. Lower supersaturation may result in larger droplets being formed, and can hence influence subsequent nanowire growth. In the examples shown in
The experimental parameters used for the growths shown in
In general for the growth shown in
In this growth, the proportion of P flux in the group V flux was about 3% in the first two minutes and then raised to 15% in the last 28 minutes. The growth was carried out at a temperature which was 10-15° C. higher than for the other growths and with a higher group V/III flux ratio than for the other growths. The EDX results in
This experiment has parameters similar to
The difference in the incorporated amount of P between the growth shown in
The general observation from the growths resulting in the nanowires shown in
Turning to crystal quality, an inspection of the nanowire shown in
From Ga-assisted growth of GaAs nanowires it is known that the amount of group V and group III atoms reaching the Ga droplet on top of the wire may change during the nanowire growth. This is also expected for Ga-assisted growth of GaAsP and therefore the growth parameters may need to be modified in a similar manner during the nanowire growth to maintain a good crystal quality throughout the nanowire. Further, since the diffusion lengths and incorporation ratios of As and P is different the As/P flux ratio may also need to be adjusted during growth in order to ensure that a constant amount of P is incorporated in the GaAsP nanowire during the entire nanowire growth.
Overall, it is possible to express the proportion of P flux in the group V flux during growth as a multiple of the percentage of P that is to be incorporated in the nanowire group V atoms. That multiple may be in the range 0.2 to 2.0. Having advance knowledge of the multiple for a given growth temperature and group V/III flux ratio means that it is possible to select the amount of P to be present in the grown nanowire by adjusting the proportion of P flux in the group V flux accordingly. Surprisingly, the multiple is much lower than what would be expected for bulk GaAsP growth, which may enable greater control to be exercised over the composition of the nanowire.
The nanowire growths discussed above were carried out at temperatures greater than 629° C., i.e. in a temperature range of 630° C. to 645° C. This temperature is more than 50° C. higher than is used for Au-catalyzed growth.
The technique described above may be adapted to form core-shell p-n junctions (preferably p-i-n junctions) within the nanowire. For example, such a method may comprises a nanowire growth stage (e.g. for 50-60 mins) which may use any of the suitable conditions (e.g. growth temperature, group V/III flux ratio, etc.) and sub-stages outlined above. Following nanowire growth, the complete p-i-n structure may be created by additional bulk (i.e. thin film) GaAsP growth around the nanowire. Prior to creating the p-i-n structure the Ga droplet may be removed by transforming it to GaAsP by exposing it to a flux of As and P atoms without also supplying Ga atoms. The droplet will hence disappear and the Ga-assisted nanowire growth will stop.
The shell bulk growth may be performed at a lower temperature than the nanowire growth stage, so before the bulk growth stage there may be a cooling step (e.g. for around 10 mins) during which no growth occurs (e.g. because the Ga flux is reduced or switched off completely). For example, the nanowire growth stage may be performed at temperatures greater than 600° C., e.g. 635° C., whereas the bulk growth may be performed at temperatures less than 550° C. In addition, as mentioned above, bulk growth of GaAsP requires a higher proportion of P in the group V flux to achieve the equivalent proportion of P atoms in the group V atoms of the deposited structure. Accordingly, the P proportion in the group V flux during bulk growth is increased (e.g. to greater than 30% or greater than 35) in order to provide a proportion of P atoms in the deposited bulk layer that matches the proportion of P atoms in the nanowire.
Following the cooling step, a first bulk growth stage may be performed in which a p-type dopant (e.g. Be) is included in the flux. A p-doped layer may thus be formed on the nanowire.
Following the first bulk growth stage, there may be a heating step to promote diffusion of the dopant into the nanowire, e.g. to increase the uniformity of the p-type conductivity throughout the structure and form a p-type core. During the heating step no growth occurs (e.g. because the Ga flux is reduced or switched off completely). The temperature of the heating step may be greater than that possible for bulk growth, i.e. greater than 550° C. (e.g. 600° C.). The heating may take place for 10 minutes or more, e.g. 20 minutes.
The heating step may end with a cooling period in which the temperature is returned to a level suitable for bulk growth.
Following the heating step and cooling period, a second bulk growth stage may be performed, in which an intrinsic (i-type) layer is grown over the p-type core. No doping is present during this growth stage.
Following the second bulk growth stage, a third bulk growth stage may be performed in which an n-type dopant (e.g. Si) is introduced into the flux such that an n-type layer is formed on the i-type layer.
Following the third bulk growth stage, the process may terminate with a cooling period or by further growth of a surface passivation and/or contact layer.
A conventional tunnel junction 14 (in this case made of silicon) is formed (i.e. grown) on the upper surface 24 of the substrate 12. The tunnel junction may be excluded or be a heterojunction between the silicon and the nanowires.
On the other side of the tunnel junction 14 from the first p-n junction is a nanowire region 16 that forms a second p-n junction. The nanowire region 16 comprises a base layer (substrate) 26 of silicon (in this example p-type silicon) on which a plurality of GaAsP nanowires 28 are grown using the Ga-assisted MBE technique discussed above. The GaAsP nanowires 28 have a p-type core region and are subsequently coated in an n-type shell region to form a second p-n junction for the photovoltaic cell. A region of intrinsic GaAsP (not shown) may be formed between the p-type region and n-type region to form a p-i-n type junction. The band gap of the GaAsP in the second p-n junction may be about 1.7 eV.
To complete the cell, electrical contacts (not shown) may be provided on the bottom surface of the substrate 12 and the top surface of the nanowire region 16. The electrical contact at the top surface may comprise a transparent conductor to enable incident light 18 to reach the p-n junctions in the cell.
The silicon substrate 26 may be prepared for GaAsP nanowire fabrication using a nanoimprint lithographic process having the following steps. Firstly a layer of oxide (e.g. having a thickness of 40 nm) is grown on the silicon substrate 26, e.g. by means of a dry thermal oxidation technique. Secondly, a planarization layer and a subsequent imprint layer are deposited on top of the layer of oxide. Thirdly, an array or pattern of oxide free holes are formed by using a suitable imprint stamp to compact the imprint layer at each hole location, i.e. such that the imprint layer is substantially thinner where each oxide free hole is to be located. Fourthly, two reactive ion etch (RIE) steps are performed. The first RIE step removes a small amount of the imprint layer to thereby expose the planarization layer underneath. The second RIE step removes the planarization layer in the areas where this is exposed through the imprint layer. The effect of these steps is to expose the oxide layer at each hole location. Fifthly, the exposed oxide layer is etched with RIE and hydrofluoric acid. It is preferable for most of the oxide layer to be removed by the RIE etch since this gives the best etch profile but for the final few nanometres of oxide to be removed using hydrofluoric acid since this leaves a more clean silicon surface at the bottom of the etched holes. Sixthly, the remaining planarization layer and imprint layer are be removed and the substrate cleaned using a RCA cleaning process. Finally, before beginning the nanostructure fabrication, an additional HF etching step can be carried out to remove any native oxide that may have re-grown in the etched holes.
The silicon substrate 26 may also be provided with a patterned array of oxide free holes by using deep UV-lithography and subsequent etching steps. The array can also be fabricated by depositing on the silicon substrate a layer of spin-on-glass (or similar) into which the imprint pattern then can be imprinted and the spin-on-glass afterwards cured such that it forms a layer with the same properties as silicon oxide. A short etch step will then ensure that the patterned holes are completely oxide free whereas silicon oxide like spin-on-glass still covers the rest of the silicon substrate.
The GaAsP nanowires 28 grown on the substrate 26 may have surface passivation applied thereto, e.g. by growing an additional shell of highly n-doped InGaP using conventional epitaxial methods. Applying surface passivation in this way may increase the peak conversion efficiency of the nanowire. Peak efficiencies greater than 10% are possible.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1113464.0 | Aug 2011 | GB | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP12/64035 | 7/17/2012 | WO | 00 | 5/8/2014 |
| Number | Date | Country | |
|---|---|---|---|
| 61513018 | Jul 2011 | US |
