Patent Application
20070155025
The invention relates generally to the field of large-area electronics on flexible or rigid substrate, and more particularly to the large-area flexible electronics enabled by nanowire structures and methods of making the same.
Although rapid miniaturization of microelectronics has led to cost reduction, integration of these devices over large area substrates still poses challenges in terms of device efficiency and reliability. Current large-area and low-cost electronic devices are primarily based on amorphous silicon (a-Si) or polycrystalline silicon (poly-Si) transistors on glass, and the device performance is limited due to low carrier mobilities in amorphous silicon (a-Si) or poly-Si. These transistors are being used in various applications, such as flat panel displays (FPDs), solar cells, image sensor arrays and digital X-ray imagers.
There has been growing interest in the use of plastic as a substrate for large-area electronics due to various beneficial attributes of plastic, such as availability, low cost, light weight and flexibility. However, the fabrication of transistors such as field effect transistors (FETs) or thin film transistors (TFTs) is difficult on plastic substrates because the processing temperatures of the transistors should be maintained below the transition temperature of the plastic.
Single crystalline Si is traditionally used in microelectronic circuits with high mobility ˜1000 cm2/V·s for electrons and ˜400 cm2/V·s for holes. However, there exists no practical way to grow high quality single crystal Si at low temperature directly on flexible substrates. Although, deposition of a-Si at low temperature on flexible substrate is possible, a-Si is not capable of high-speed operation because of the low electron mobility (<1 cm2/V·s) caused by high defect densities.
Some fabrication methods counter this shortcoming of plastic substrates by employing assembling techniques. It includes fabricating circuits and devices on a first substrate, referred to as “mother” substrate and then separating and transferring the device to another substrate. “Separation and transfer fabrication” approaches all have the common feature of separating finished circuits from the mother substrate after all fabrication steps are completed. Some of these approaches remove all materials, processing, and processing temperature constraints. However, these approaches are still far from mature with limited final substrate sizes.
Accordingly, it is desirable to have a fabrication method, which enables low cost and more efficient methods for large-area devices. Also, it is desirable to provide large-area flexible electronics that is more efficient and provides improved device properties in terms of reliability.
In accordance with one aspect of the present technique, a nanowire structure is provided. The nanowire structure includes a nanowire defining an axis, where the nanowire includes a first end and a second end, and where the first end is axially spaced from the second end. Further, the nanowire structure includes magnetic segments that are coupled to the first and second ends of the nanowire.
In accordance with another aspect of the present technique, a device is provided. The device includes a substrate having a nanowire structure disposed thereon. The nanowire structure includes a nanowire and magnetic segments. The device also includes a first magnetic microelectrode and a second magnetic microelectrode coupled to the magnetic segments of the nanowire structure. The nanowire structure is configured to electrically couple the first and second magnetic microelectrodes. The nanowire structure is configured to be aligned in a predetermined direction under the influence of a magnetic filed.
In accordance with yet another aspect of the present technique, an article is provided. The article includes a nanoscale semiconducting pathway having a first end and a second end. Further, the article includes magnetically responsive portions coupled to the first and second ends of the pathway. The magnetically responsive portions are configured to align the article in response to a magnetic field.
In accordance with another aspect of the present technique, a method of making a nanowire structure is provided. The method includes providing a substrate, forming a porous layer on the substrate, depositing a magnetic material layer in the pores to form first magnetic segments. Further, the method includes depositing a nanowire material on the magnetic material layer to form nanowires on each of the first magnetic segments. Furthermore, a second magnetic material layer is deposited on the nanowires.
In accordance with yet another aspect of the present technique, a method of making a device is provided. The method includes providing a substrate, disposing a first magnetic microelectrode and a second magnetic microelectrode on the substrate, and disposing a plurality of nanowire structures between the first and second contact pads. Further, the method includes aligning the plurality of nanowire structures, such that nanowire structures are parallel to each other and are in operative association with the first and second electrodes to electrically couple the first and second electrodes.
These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:
Nanowires made of materials, such as semiconductors or inorganic materials, are being used in large area electronic devices to improve the performance of the devices. Also, the nanowires are being used in conventional electronic devices to achieve improved device behavior, while allowing for inexpensive and fast manufacturing processes. The semiconductor nanowires are single-crystal and have comparable or better electron or hole mobility than their corresponding bulk forms. These nanowires are mostly employed in the form of films of semiconductor materials, which may be used in electronic devices to make high performance, low cost devices on large and flexible substrates. In order to effectively employ such nanowires in electronics devices, it is desirable to form low-resistance and reliable electrical contacts to these nanowire in a manufacturable fashion. As used herein, “manufacturable” implies that the electrical contacts may be made at a high rate in a scaleable process (across large substrates), with precise control of the contact area, contact resistance, and yield. However, while employing electrical contacts in large-area electronics devices, a high level of control over the position of the nanowire structures on a substrate or within layers is desirable. For example, in integrated electronics and photonics nanotechnologies, it may be desirable to align these nanowires relative to the components of the devices.
In certain embodiments, the diameter 20 of the nanowire 12 may be in a range from about 5 nanometers to about 1000 nanometers, and preferably from about 10 nanometers to about 300 nanometers. The length of the nanowires may be in a range from about 1 micron to few centimeters, and preferably from about 1 micron to about 100 microns for the devices disclosed herein. In certain embodiments, the nanowire 12 may include semiconductor materials, for example, silicon. In certain embodiments, the nanowire 12 may include germanium, III-V semiconductors, II-VI semiconductors, IV-IV semiconductors, or combinations thereof
As will be described in detail below with regard to
Referring again to
In certain embodiments, the magnetic segments 22 may include magnetic metals, such as nickel, cobalt, iron, or combinations thereof In other embodiments, the magnetic segments 22 may include a ceramic, a polymer, or other materials which are magnetically responsive.
Further, in certain embodiments, the structure 10 may include a shell 24 coupled to the nanowire 12 and surrounding at least a portion of the nanowire 12. In these embodiments, the shell 24 may be spaced radially from the axis 14 of the nanowire 12. In the illustrated embodiment, the shell 24 surrounds the portion of the nanowire 12 located between the first and second ends 16 and 18. The shell 24 may have a thickness in a range from about 5 nanometers to about 1000 nanometers, and preferably from about 20 nanometers to about 200 nanometers. Such a structure 10 may be employed in transistors. When employed in a transistor, a single crystal nanowire results in high carrier mobility, thereby resulting in high performance. As will be described in detail below with regard to
In certain embodiments, the shell 24 may be an insulator, such as silicon dioxide, such that the electrons traveling through the nanowire 12 between the first and second ends 16 and 18 of the structure 10 may not migrate to the semiconductor shell 24. In these embodiments, the shell 24 may separate impurities from the nanowire 12, thereby reducing impurity related scattering from the surface of the nanowire 12 at the interface 26. This reduced scattering in turn may result in enhanced channel mobility of the nanowire 12. In an exemplary embodiment, the channel mobility at the interface 26 may be about 1000 cm2/volt-second for silicon. Also, in some embodiments, the material compatibility at the interface 26 of the nanowire 12 and the shell 24 may be enhanced. For example, by growing the native oxide, material properties, such as lattice constant may be matched at the interface 26, thereby reducing stress related defects in the device.
Although not illustrated, in certain embodiments, the structure 10 may further include a dielectric material layer disposed on the nanowire 12. In other embodiments, the dielectric material layer may be disposed on the shell 24, thereby making a three layered structure. In exemplary embodiments, the dielectric material layer may include materials, such as but not limited to, silicon oxide, or silicon nitride.
Further, the structure 28 includes a shell 46 disposed on the nanowire 30 and forming the interface 39 with the nanowire 30. The structure 28 further includes magnetic segments 44 disposed on the first and second ends 40 and 42 of the structure 28.
In embodiments where such a structure 28 is employed in a transistor as a channel, an electrode, such as a gate electrode may be disposed on only the portion 36 as opposed to completely covering the nanowire 28 when it is un-doped. In these embodiments, the gate electrode may also partially overlap with the portions 32 and 34. In these embodiments, the portion 36 may act as the active region of the channel of the transistor.
As noted above, in embodiments where nanowires, such as nanowires 12 and 28 are employed in large area electronics devices having flexible or rigid substrates, the magnetic segments may facilitate alignment of the nanowires with respect to the components of the devices by using magnetic fields. As will be appreciated, the magnetic shape anisotropy and high remnant magnetization of the magnetic segments 22 or 44 facilitates the orientation of nanowires in small external magnetic fields with high control to achieve desirable orientation of the nanowire structures 10 or 28. Furthermore, local magnetic fields generated by local magnetized electrodes, such as magnetic microelectrodes may be used to facilitate the distribution of nanowires on a substrate, such as a substrate for the large-area electronics devices. In an exemplary embodiment, a single nanowire, such as a nanowire 12 or 28 having magnetic segments 22 or 44 may be aligned between lithographically patterned magnetic microelectrodes. In this embodiment, a substrate having lithographically defined magnetic features is placed on the bottom of a chamber. Nanowires with magnetic segments in suspension are then introduced into the chamber in the presence of an aligning external magnetic field. Subsequently, as the nanowires settle towards the surface of the substrate, they reach the proximity of the local magnetic fields produced by the lithographic features, and are drawn into regions of strong local field gradients, such as the gap between two closely-spaced lithographic features. It should be noted that, if the gap is smaller than the size of the nanowires, and the nanowire concentration in the suspension is low, then single nanowires may bridge the gap between the lithographic features and become trapped between the features, such as the microelectrodes.
In some embodiment, the nanowires may be suspended in low viscosity liquids, such as water or ethanol, to be dispersed on a substrate. In these embodiments, the segmented nanowires precipitate from the solutions over the course time. Simultaneously, aggregation may also occur due to inter-wire magnetic forces. Suspending the nanowires in relatively more viscous media may reduce aggregation and precipitation of the nanowires in the liquid, thereby facilitating uniform dispersion of nanowires in the liquid. However, relatively lower viscosity liquids may be employed to limit inter-nanowire interactions in the diluted suspension. Further, the diluted suspension may also reduce the occurrence of multiple wires trapping between a pair of components, such as electrodes of the electronics device. Further, the trapping of the nanowires may be enhanced by the application of a uniform magnetic field parallel to the long axis of the magnetic components, which pre-orients the suspended nanowires. This further reduces aggregation of wires in the suspension, and large numbers of single wires reach the bottom of the cell. Additionally, by aligning the dipole moments of the wires with the poles of the magnetic microelectrodes, the configuration for trapping in the gaps is optimized. In some embodiments, the nanowires may be re-suspended in the liquid by ultrasonic agitation.
In the illustrated embodiment of
Further, in certain embodiments, the nanowire structure 62, such as structure 62 may include a capping layer, such as a capping layer 79, which may be disposed radially around the magnetic segments 78. The capping layer 79 may facilitate the reduction in agglomeration of the nanowire structures in a solution. In these embodiments, the capping layer 79 may be disposed such that it covers the portion of the magnetic segments 78, which is parallel to the longitudinal axis of the nanowire 64, and does not cover the ends of the magnetic segments 78. In some embodiments, the thickness of such a capping layer 79 may vary in a range from about 0.1 microns to about 100 microns, and preferably from about 10 microns to about 50 microns.
As used herein, the term “aligned” indicates that the majority of the longitudinal axis of the majority of the structures 82 is aligned within 30 degrees of a predetermined direction. Although in certain embodiments, the structures 82 may be aligned within 60 percent to 90 percent of the predetermined direction. For example, in the illustrated embodiment, the predetermined direction is the direction along the line joining the center of the source contact pad 86 to the center of the drain contact pad 88 and a majority of the nanowire structures are within 90 percent of the predetermined direction. As noted above, the segments 90 may be used to align the structures 82 in a predetermined direction. In certain embodiments, the structures 82 may be aligned under the influence of the magnetic field of the contact pads 86 and 88. In these embodiments, the magnetic segments 90 realign themselves under the influence of the magnetic field of the magnetic microelectrodes, such as contact pads 86 and 88, thereby aligning the nanowire structures 82 between the contact pads 86 and 88. In alternate embodiments, an external magnetic field may be applied to the structures 82 to align the structures 82 in a predetermined direction. In these embodiments, the external magnetic field may either be applied in combination with the magnetic field of the magnetic microelectrodes, or separately to align the structures 82. In an exemplary embodiment, the strength of the external magnetic field may be in a range from about 5 Gauss to about 50 Gauss.
Although in the illustrated embodiment the source and drain contact pads 86 and 88 are coupled using a single nanowire structure, however, it should be noted that a plurality of such structures may be employed to couple the source and drain contact pads 86 and 88 by controlling the shape of magnetized microelectrodes. Also, when a plurality of such structures 82 are employed between the source and drain contact pads 86 and 88, the structures may be aligned such that their respective axis 94 are parallel to each other to provide high current handling capacity along the direction parallel to the axis 94.
In certain embodiments, the contact pads 86 and 88 may include magnetic material. In these embodiments, the material of the contact pads and the magnetic segments 90 of the structure 82 may be the same. As will be described in detail below, in an exemplary embodiment, the contact pads 86 and 88 may have an elliptical shape to facilitate orientation of nanowire structures, such as structures 82.
The nanowire structure 82 may include a nanowire 92, and may be disposed between and electrically coupled to the contact pads 86 and 88 along the axis 94. The structure 82 further includes shell 96 surrounding the nanowire 92. In the illustrated embodiment, a gate contact pad 98 is coupled to a portion of the structure 82. Depending on the doping profile of the nanowire 92, the gate contact pad 98 may either cover the entire portion of the nanowire 92 disposed between the first and second ends 100 and 102, or may be disposed only on a portion of the nanowire 92. In the illustrated embodiment, the nanowire 92 may include similarly highly doped regions 104 and 106 disposed on either side of a relatively lightly doped region 108. In this embodiment, the region 108 acts as the active region of the channel or the nanowire 92. Therefore, when employing the gate electrode, the gate electrode may be disposed such that it covers mainly the region 108, and may overlap partially with the adjacent regions 104 and/or 106. As illustrated, the gate contact pad 98 stretches over the entire length of the region 108 and partially overlaps the regions 104 and 106. Hence, relatively smaller amount of the gate contact pad material may be employed in the transistor as opposed to the transistor employing an undoped nanowire structure, such as the structure 10 (see
As will be appreciated, the position of the source and drain contact pads 86 and 88 may be interchanged without affecting the performance of the device 80. In certain embodiments, the source and drain contact pads 86 and 88 may be coupled to capping pads, such as metal caps 110 and 112, respectively. In certain embodiments, the caps 110 and 112 may be used to secure the nanowire structure 82 to the source and drain contact pads 86 and 88 once they are aligned in the predetermined direction between the source and drain contact pads 86 and 88.
Subsequently, magnetic material layer 152 is deposited into the pores 150 to form first magnetic segments. In certain embodiments, this magnetic material layer 152 may be employed to form the magnetic segments of the nanowire structures. In these embodiments, the layer 152 may include the material, which is desirable as the magnetic segments. For example, the magnetic material layer 152 may include nickel, cobalt, or iron, or combinations thereof In an exemplary embodiment, electro-chemical deposition may be employed to deposit magnetic material layer 152 into the pores 150. The fill factor of layer the 152 may be reduced to increase the space between individual nanowires. In an exemplary embodiment, the fill factor of the layer 152 is reduced by using an easily oxidizing metal layer, such as titanium. Further, a catalyst 154, such as gold may be deposited on the magnetic material layer 152. In certain embodiments, the magnetic catalyst 154 may be deposited by employing processes, such as electrochemical deposition, e-beam evaporation, thermal evaporation, or sputtering. In an exemplary embodiment, the catalyst 154 may be deposited using electro-chemical deposition. In certain embodiments, the catalyst 154 may be used to facilitate the growth of the nanowire structure.
Next, a layer 156 of the nanowire material is deposited on the magnetic material layer 152 to form nanowire of the nanowire structure. In certain embodiments, the layer 156 of the nanowire material may include silicon, germanium, group III-V semiconductors, group II-VI semiconductors, group IV-IV semiconductors, or combinations thereof. In some embodiments, the layer 156 of the nanowire material may be deposited using chemical vapor deposition, such as one using vapor-liquid-solid mechanism. In these embodiments, the substrate 146 having the magnetic material layer 152 in the pores 150 and/or the catalyst 154 may be transferred to a chemical vapor deposition chamber prior to depositing the layer 156 of the nanowire material. Further, if a catalyst 154, such as gold, is employed, the catalyst is heated to form a liquid droplet and absorb the material of the nanowire and deposit it on the magnetic material layer 152 underneath. In the embodiments where a portion of the nanowire is doped, the dopants may be introduced as gas species in the chemical vapor deposition chamber during the deposition of the layer 156.
Subsequently, the second metal segment layer 162 is deposited on the layer 156 of the nanowire material to form the second magnetic segments 162 using the pores of the photoresist 158 as a template. In an exemplary embodiment, the magnetic segments 162 may be deposited by employing processes, such as electro- chemical deposition. Subsequently, the photoresist 158 is removed by dissolving it in a suitable solvent, such as acetone, PRS1000, PRS3000 or other resist strippers, or etching by oxygen plasma. Optionally, a portion of the metal film 148 of anodized alumina may also be etched away by controlled wet etching, such as buffered oxide etch, or KOH or NaOH, to fully expose the semiconductor segment.
As noted above, for applications such as LEDs and photodetectors, the steps illustrated in
As noted above, in certain embodiments a local magnetic field may be applied between these magnetic microelectrodes to align the nanowire structures. In some embodiments, prior to disposing the nanowires 172 between the magnetic microelectrodes 170, the magnetic microelectrodes 170 may be magnetized in a magnetic field or for example, 5 kilo Gauss. In the embodiments where the magnetic microelectrodes 170 are elliptical, the magnetic filed between a pair of these magnetic microelectrodes may be maximum along the line parallel to the major axis of the two ellipses and joining the center of the ellipses. Therefore, in embodiments where a single nanowire structure is desirable between each pair of the magnetic microelectrodes 170, it may be desirable to have the magnetic microelectrodes 170 in the shape of an ellipse. Similarly, in embodiments where it is desirable to have a plurality of nanowire structures between each pair of the magnetic microelectrodes 170, it may be desirable to have the magnetic microelectrodes 170 in a shape, which has a relatively uniform magnetic field along its faces. For example, it may be desirable to have rectangular magnetic microelectrodes 170.
In some embodiments, subsequent to forming the magnetic microelectrodes 170, a photoresist window (not shown) may be formed between the magnetic microelectrodes 170 for selective disposal of nanowire structures. Subsequently, nanowire structures 172 may be disposed between the magnetic microelectrodes 170. In certain embodiments, the step of disposing the nanowire structures 172 may include dispersing these structures 172 in a fluid and disposing the solution having the solvent and the structures 172 suspended in the fluid between the magnetic microelectrodes 170. In some embodiments, the fluid used to disperse the structures 172 may include water, methanol, ethanol, iso-propanol, or combinations thereof. As with the nanowire structures 10, 28, 48 or 62, the nanowire structures 172 may include a nanowire, optionally a shell surrounding the nanowire, and magnetic segments disposed on either side of the nanowire. Subsequent to disposing the structures 172 between each of the pairs of the magnetic microelectrodes 170, the structures 172 are aligned in a predetermined direction. In certain embodiments, the alignment of the structures 172 may be facilitated by interaction between the magnetic segments of the structures 172 and the magnetic microelectrodes 170, and/or by application of an externally applied magnetic field. In the illustrated embodiment, subsequent to aligning the nanowires 172 between the magnetic microelectrodes 170, the end of the nanowires 172 may be capped by employing metal pads 174, such as source and drain caps. Optionally, in case of a transistor, a gate contact pad (not shown) may be deposited on the structures 174.
Additionally, after aligning the nanowires and disposing metal caps, an additional pair of contact pads or magnetic microelectrodes may be disposed relative to the magnetic microelectrodes 170. For example, a pair of contact pads may be disposed perpendicular to the magnetic microelectrodes 170 and nanowire structures may be aligned between the additional contact pads to form cross-bar nanowire arrangement by employing the method mentioned above with respect to
Although the present technique is discussed mainly with reference to transistors, p-n and p-i-n diodes, the nanowire structure of the present technique may also be employed in other applications like switching devices, and other opto-electronic devices.
The nanowire structure and device described above find utility in a variety of electronics and opto-electronics systems, such as high-density nanowire light emitting diodes, and high-density photodetectors on flexible or rigid substrates, high-performance and large-area electronics on flexible or rigid substrate, hybrid systems with integrated electronics, such as, sensors, LED displays, and photodetector imagers on a single chip for compact display, communications, and sensor devices, and so forth. Further, the nanowire structures and devices as described above may be employed as light emitting diodes and control circuits in various display systems, such as, but not limited to wall-to-wall displays, or display on other non-flat surfaces. For example, such display device may be coupled to the insides of windshields. The nanowire devices as described above may be employed in X-ray imagers, display panels, and radio frequency identification tags. For example, such nanowire structure and devices may be employed in an X-ray imager as control circuit for the pixels and photodetector.
While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
