Patent Application
20240096968
The present disclosure relates to a nitride semiconductor device.
As a semiconductor device that operates at high power and in a high frequency region, a field effect transistor (FET) made of a nitride semiconductor and the like are conventionally used. However, a phenomenon of an increase in temperature of the interior of the semiconductor device during high power operation to reduce characteristics or reliability of the device has been problematic.
To suppress the increase in temperature of the interior of the semiconductor device, it is important to dispose a material or a structure having high heat dissipation near a heat generator. Diamond has the highest thermal conductivity of all solid substances, and is an optimum heat dissipation material.
As a semiconductor device expected to have a high heat dissipation effect, a structure in which a substrate of the semiconductor device as a whole is replaced with diamond, that is, diamond is used as a heat spreader is known. It is difficult to grow the nitride semiconductor directly over diamond, so that a structure in which diamond is grown over or applied to the nitride semiconductor via an intermediate layer is used. A GaN on Diamond structure in which gallium nitride (GaN) is used as the nitride semiconductor is well known.
It is necessary to form a via hole to impart desired high frequency characteristics with such a structure. The via hole is typically formed to provide contact between a front surface electrode and a back surface of a semiconductor substrate, and is formed by forming an opening by etching from the back surface of the semiconductor substrate and covering the interior of the opening with a metal layer. Such a configuration allows for omission of a wire bonding structure, reduction in source inductance, and, further, higher performance due to improvement in high frequency characteristics.
Patent Document 1 discloses a configuration in which a via hole extending between a front surface and a back surface of a semi-insulating substrate is a multi-step via hole including a small-diameter via hole on a side of the front surface and a large-diameter via hole on a side of the back surface. The multi-step via hole in Patent Document 1 is formed by dry etching. When diamond is used for the semi-insulating substrate, however, diamond has an extremely low etch rate as it is a difficult-to-etch material. This causes a problem in that formation of the via hole only by dry etching is time consuming, and increases costs.
Non-Patent Document 1 discloses formation of a tapered via in a high frequency device having a Gan on Diamond structure by laser drilling. In this case, there has been a problem in that conduction failure occurs due to a burr at an end of an opening of a via hole, roughness of a side wall of the via hole, and damage to an electrode pad, and desired high frequency characteristics cannot be imparted.
The present disclosure has been conceived to solve the above-mentioned problem, and it is an object of the present disclosure to impart desired high frequency characteristics to a nitride semiconductor device including diamond as a substrate at a low cost.
A nitride semiconductor device according to the present disclosure includes: a diamond layer; a ground electrode disposed over a first main surface of the diamond layer; an intermediate layer disposed over a second main surface being a main surface opposite the first main surface of the diamond layer; a nitride semiconductor layer disposed over a surface of the intermediate layer opposite the diamond layer; and an electrode disposed over a surface of the nitride semiconductor layer opposite the intermediate layer. A via hole extends from the first main surface of the diamond layer through the diamond layer, the intermediate layer, and the nitride semiconductor layer to the electrode. The via hole has a multi-step structure including a large-diameter via hole being in contact with the first main surface of the diamond layer and a small-diameter via hole facing the electrode, having a smaller diameter than the large-diameter via hole, and being tapered.
According to the nitride semiconductor device according to the present disclosure, desired high frequency characteristics can be imparted at a low cost. The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.
A via hole 16 extending through the diamond layer 11, the intermediate layer 12, and the nitride semiconductor layer 13 is formed directly below the source electrode of the electrode 14 or an electrode pad connected to the source electrode, and the electrode 14 and the ground electrode 15 are electrically connected via the via hole 16.
Polycrystalline diamond or monocrystalline diamond is used for the diamond layer 11. The diamond layer 11 is preferably manufactured by chemical vaper deposition (CVD). The diamond layer 11 preferably has a thickness of 10 μm or more and 500 μm or less.
Si, an oxide of Si, or a nitride of Si is used for the intermediate layer 12. When the intermediate layer 12 is a conductor, high frequency characteristics of the nitride semiconductor device 101 are reduced, so that the intermediate layer 12 preferably has a resistivity of 0.1 μΩ or more. The intermediate layer 12 is only required to have a thickness of 1 nm or more and 100 nm or less. When the intermediate layer 12 has a large thickness, however, heat dissipation of the nitride semiconductor device 101 is reduced. The intermediate layer 12 thus preferably has a thickness of 1 nm or more and 40 nm or less.
A material for the nitride semiconductor layer 13 includes GaN, AlGaN, InAlN, AlN, and the like, for example. The nitride semiconductor layer 13 may be a single semiconductor layer made of any one of these materials, or may be a stack of a plurality of semiconductor layers made of two or more dissimilar materials selected from these materials. The nitride semiconductor layer 13 typically has a thickness of 10 μm or less, but may have a thickness of more than 10 μm.
Materials for the electrode 14 and the ground electrode 15 may each be a single metal element or an alloy. As the single metal element, one element selected from the group consisting of Cu, Ti, Al, Au, Ni, Nb, Pd, Pt, Cr, W, Ta, and Mo may be used. As the alloy, AuGe, AuGa, AuSn, and the like may be used. The electrode 14 and the ground electrode 15 may each be a stack of any of the above-mentioned materials.
A semiconductor device such as a high electron mobility transistor (HEMT) is formed by the nitride semiconductor layer 13 and the electrode 14.
The via hole 16 includes a small-diameter via hole 16a facing the electrode 14 and a large-diameter via hole 16b facing the ground electrode 15 and having a larger diameter than the small-diameter via hole 16a. The small-diameter via hole 16a is tapered to have a diameter decreasing with decreasing distance from the electrode 14 and increasing with decreasing distance from the large-diameter via hole 16b. A tapered shape refers to a shape having an angle formed by a bottom surface and a side surface of the via hole, that is, a taper angle of 90° or more.
First, the nitride semiconductor layer 13 is formed over a substrate of Si and the like, and the electrode 14 is formed over the nitride semiconductor layer 13. The semiconductor device is thus formed by the nitride semiconductor layer 13 and the electrode 14. Next, the substrate is removed, and the second main surface S2 of the diamond layer 11 is bonded, via the intermediate layer 12, to a surface of the nitride semiconductor layer 13 from which the substrate has been removed. Surface activated bonding is used for bonding of the diamond layer 11. The intermediate layer 12 is made of Si, and has a thickness of 10 nm. The diamond layer 11 has a thickness of 100 μm. A stack of the diamond layer 11, the intermediate layer 12, the nitride semiconductor layer 13, and the electrode 14 illustrated in
Next, as illustrated in
Next, as illustrated in
Next, dry etching is performed using the metal mask 17 to etch remaining portions of the diamond layer 11, the intermediate layer 12, and the nitride semiconductor layer 13 to thereby form the via hole 16 including the small-diameter via hole 16a and the large-diameter via hole 16b. The via hole 16 is a via hole formed based on the via hole 16c as the first via hole, and is also referred to as a second via hole. An inductively coupled plasma (ICP) etching apparatus is used for dry etching. The diamond layer 11 and the intermediate layer 12 are etched with a mixed gas of O2, SF6, and Ar, and the nitride semiconductor layer 13 is etched with a mixed gas of Cl2, BCl3, and Ar. An etch depth is adjusted by adjusting an etch time. The thicknesses of the diamond layer 11, the intermediate layer 12, and the nitride semiconductor layer 13, the depth of the via hole 16c, and an etch rate of a material etched with each gas species are measured in advance, and the etch time is determined based on them.
By etching described above, a side surface and a bottom surface of the via hole 16c are etched to extend the via hole 16c through the intermediate layer 12 and the nitride semiconductor layer 13 to the electrode 14. The small-diameter via hole 16a is formed as described above. Since the side surface of the via hole 16c is etched, roughness of the side surface of the via hole 16c caused by laser processing is mitigated or removed. Furthermore, since the opening of the metal mask 17 is larger than an opening of the via hole 16c as described above, a portion of the first main surface S1 of the diamond layer 11 exposed from the opening of the metal mask 17 is also etched. The large-diameter via hole 16b is thus formed, and a burr in an opening portion of the via hole 16c caused by laser processing is removed. The small-diameter via hole 16a has a depth of 96 μm, and the large-diameter via hole 16b has a depth of 7 μm.
Then, as illustrated in
An example in which, after formation of the via hole 16c by laser processing, the metal mask 17 is formed, and dry etching is performed has been shown in description made above. The metal mask 17, however, may be formed before formation of the via hole 16c. In this case, when the via hole 16c is formed, a portion inward of an opening portion of the metal mask 17 is preferably irradiated with a laser so that the metal mask 17 is not irradiated to avoid damage to the metal mask 17.
Next, the ground electrode 15 is formed over the first main surface S1 of the diamond layer 11 and in the via hole 16. The nitride semiconductor device 101 illustrated in
The nitride semiconductor device 101 in Embodiment 1 includes: the diamond layer 11; the ground electrode 15 disposed over the first main surface S1 of the diamond layer 11; the intermediate layer 12 disposed over the second main surface S2 of the diamond layer 11, which is the main surface opposite the first main surface S1; the nitride semiconductor layer 13 disposed over the surface of the intermediate layer 12 opposite the diamond layer 11; and the electrode 14 disposed over the surface of the nitride semiconductor layer 13 opposite the intermediate layer. The via hole 16 extends from the first main surface S1 of the diamond layer 11 through the diamond layer 11, the intermediate layer 12, and the nitride semiconductor layer 13 to the electrode 14. The via hole 16 has the multi-step structure including the large-diameter via hole 16b being in contact with the first main surface S1 of the diamond layer 11 and the small-diameter via hole 16a facing the electrode 14, having a smaller diameter than the large-diameter via hole 16b, and being tapered.
Such a via hole 16 can be formed by first forming a via hole having a certain depth from the first main surface S1 by laser processing, and then removing a layer remaining at a bottom of the via hole and a portion around an opening of the via hole by dry etching. The diamond layer 11 is thus not required to be removed only by dry etching when the via hole 16 is formed, so that the via hole 16 can be formed in a short time. The via hole does not extend through the nitride semiconductor layer 13 by laser processing, so that damage of the laser to the electrode 14 is avoided. The burr or roughness in cross section of the via hole caused by laser processing is mitigated or removed by dry etching thereafter. As a result, the via hole 16 provides good conduction between the electrode 14 and the ground electrode 15. An increase in source inductance is thus suppressed, and high frequency characteristics do not deteriorate.
The method for manufacturing the nitride semiconductor device 101 includes: (a) forming the via hole 16c as the first via hole extending from the first main surface S1 of the diamond layer 11, which is the surface opposite the intermediate layer 12, not to the electrode 14 in the stack of the diamond layer 11, the intermediate layer 12, the nitride semiconductor layer 13, and the electrode 14 stacked in this order by laser processing; (b) forming the metal mask 17 having the opening from which the via hole 16c as a whole and the portion of the first main surface S1 of the diamond layer 11 adjacent to the via hole 16c are exposed and which has a larger diameter than the via hole 16c; (c) processing the via hole 16c into the via hole 16 as the second via hole by dry etching with the metal mask 17; and (d) forming the ground electrode 15 over the first main surface S1 of the diamond layer 11 and in the via hole 16. In the step (c), the via hole 16 is formed to have the multi-step structure including the large-diameter via hole 16b formed by removing the portion of the first main surface S1 of the diamond layer 11 exposed from the opening of the metal mask 17 and the small-diameter via hole 16a formed by extending the via hole 16c to the electrode 14, having a smaller diameter than the large-diameter via hole 16b, and being tapered. The burr or roughness in cross section of the via hole 16c caused by laser processing in the step (a) is thus mitigated or removed by dry etching in the step (c) thereafter. Only a portion of the diamond layer 11 is removed by laser processing in the step (a), so that the laser causes no damage to the electrode 14. As a result, the via hole 16 provides good conduction between the electrode 14 and the ground electrode 15, the increase in source inductance is suppressed, and high frequency characteristics do not deteriorate. An etch rate in dry etching of the diamond layer 11 is extremely low, so that the via hole 16 can be formed in a shorter time compared with a case where the via hole 16 is formed only by dry etching.
According to the method for manufacturing the nitride semiconductor device 101 in Embodiment 1, the intermediate layer 12 is etched by dry etching after formation of the via hole 16c. This sometimes recesses the intermediate layer 12 not only in a direction of the thickness but also in a planer direction perpendicular to the direction of the thickness to notch a side surface of the via hole 16 in the intermediate layer 12. As a result, it becomes difficult to cover the side surface of the via hole 16 with the ground electrode 15, and conduction failure might occur.
A method for manufacturing the nitride semiconductor device in Embodiment 2 differs from that in Embodiment 1 in that a via hole 26c formed by laser processing extends from the diamond layer 11 through the intermediate layer 12 to the nitride semiconductor layer 13.
The via hole 26 includes the small-diameter via hole 26a facing the electrode 14 and a large-diameter via hole 26b facing the ground electrode 15 and having a larger diameter than the small-diameter via hole 26a. The small-diameter via hole 26a is tapered to have a diameter decreasing with decreasing distance from the electrode 14 and increasing with decreasing distance from the large-diameter via hole 26b. The depth h of the small-diameter via hole 26a is greater than the sum of the thicknesses of the diamond layer 11 and the intermediate layer 12.
First, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, dry etching is performed using the metal mask 17 to etch the nitride semiconductor layer 13. The ICP etching apparatus is used for dry etching. The nitride semiconductor layer 13 is etched with a mixed gas of Cl2 and BCl3.
By etching described above, a bottom surface of the via hole 26c is etched, and the via hole 26c extends through the nitride semiconductor layer 13 to the electrode 14. The small-diameter via hole 26a is formed as described above. A side surface of the via hole 26c is etched, so that roughness of the diamond layer 11 forming the side surface of the via hole 26c caused by laser processing is mitigated or removed. Furthermore, the opening of the metal mask 17 is larger than that of the via hole 26c, so that a portion of the first main surface S1 of the diamond layer 11 exposed from the opening of the metal mask 17 is also etched. Thus, the large-diameter via hole 26b is formed, and a burr in an opening portion of the via hole 26c caused by laser processing is removed. The small-diameter via hole 26a has a depth h of 102 μm, and the large-diameter via hole 26b has a depth of 1 μm. The via hole 26 including the small-diameter via hole 26a and the large-diameter via hole 26b is a via hole formed based on the via hole 26c as the first via hole, and is also referred to as the second via hole.
The depth h of the small-diameter via hole 26a has a value obtained by subtracting the depth of the large-diameter via hole 26b from the sum of the thicknesses of the diamond layer 11, the intermediate layer 12, and the nitride semiconductor layer 13. The depth of the large-diameter via hole 26b herein corresponds to the thickness of the diamond layer 11 removed while the entire thickness of the nitride semiconductor layer 13 is removed by dry etching. The diamond layer 11 has a lower etch rate than the nitride semiconductor layer 13, so that the depth of the large-diameter via hole 26b is smaller than the thickness of the nitride semiconductor layer 13. The depth h of the small-diameter via hole 26a is thus greater than the sum of the thicknesses of the diamond layer 11 and the intermediate layer 12.
Then, as illustrated in
Next, the ground electrode 15 is formed over the first main surface S1, that is, a surface having an opening of the via hole 26 of the diamond layer 11. The nitride semiconductor device 102 illustrated in
In the nitride semiconductor device 102 in Embodiment 2, the depth of the small-diameter via hole 26a is equal to or greater than the sum of the thicknesses of the intermediate layer 12 and the nitride semiconductor layer 13. Such a small-diameter via hole 26a is formed by forming the via hole 26c as the first via hole extending from the first main surface S1 of the diamond layer 11 through the diamond layer 11 and the intermediate layer 12 by laser processing, and then removing the nitride semiconductor layer 13 at a bottom of the via hole 26c and the first main surface S1 around the opening of the via hole 26c by dry etching. Although the intermediate layer 12 is exposed to an etch gas in a step of dry etching the nitride semiconductor layer 13, the intermediate layer 12 is less likely to be recessed in the planar direction as the intermediate layer 12 has a low etch rate for the etch gas. A side surface of the via hole 26 is thus less likely to be notched in the intermediate layer 12, and conduction failure of the via hole 26 is less likely to occur. As a result, reduction in high frequency characteristics is suppressed, and the nitride semiconductor device 102 can be manufactured with high yield.
In the method for manufacturing the nitride semiconductor device 102 in Embodiment 2, in the step (a), the via hole 26c as the first via hole is formed to extend through the diamond layer 11 and the intermediate layer 12 to the nitride semiconductor layer, and, in the step (c), a portion of the nitride semiconductor layer 13 overlapping the via hole 26c in plan view is removed to form the small-diameter via hole 26a. The intermediate layer 12 is removed by laser processing, so that the intermediate layer 12 is exposed to the etch gas in the step of dry etching the nitride semiconductor layer 13 thereafter, but is less likely to be recessed in the planar direction as the intermediate layer 12 has a low etch rate for the etch gas. The side surface of the via hole 26 is thus less likely to be notched in the intermediate layer 12, and conduction failure of the via hole 26 is less likely to occur. As a result, reduction in high frequency characteristics is suppressed, and the nitride semiconductor device 102 can be manufactured with high yield.
In contrast to the intermediate layer 12, a difficult-to-etch material is used for the intermediate layer 32. The difficult-to-etch material is a material that is not easier to be etched than Si or SiN, and includes nanocrystalline diamond, an oxide or a carbide of Si, an oxide or a nitride of Al or Ti, an oxide of Hf or Zr, and the like as specific examples. The difficult-to-etch material is characterized in that a physical reaction predominates in dry etching. The difficult-to-etch material is also characterized by having an extremely low etch rate when dry etched with a Cl-based or an F-based gas. A high-temperature melting point material having a melting point of 1000° C. or more is typically likely to be the difficult-to-etch material.
There are two main principles of dry etching. The first is physical etching to perform sputtering by ions, and the second is chemical etching to perform reactive etching by a chemical reaction of the etch gas. The difficult-to-etch material can be processed by the former physical etching although an etch rate is low.
The intermediate layer 32 made of the difficult-to-etch material can be processed by physical etching.
Steps for manufacturing the nitride semiconductor device 103 in Embodiment 3 conform to steps for manufacturing the nitride semiconductor device 101 in Embodiment 1 or the nitride semiconductor device 102 in Embodiment 2.
In the former case, the intermediate layer 32 at a bottom of the via hole 16c can be removed by performing physical etching as dry etching. Assume that the intermediate layer 32 herein has a thickness of 10 nm and is made of AlN. The ICP etching apparatus is used for dry etching, and the diamond layer 11 and the intermediate layer 12 below the via hole 16c are etched with a mixed gas of Cl2 and Ar. The semiconductor layer 13 is then etched with a mixed gas of Cl2, BCl3, and Ar. The via hole 16 including the small-diameter via hole 16a and the large-diameter via hole 16b is thus obtained.
In the nitride semiconductor device 103 in Embodiment 3, the intermediate layer 32 is made of the difficult-to-etch material having a lower etch rate than Si or SiN in dry etching with the F-based gas or the Cl-based gas. Thus, when the via hole 16 is formed, the intermediate layer 12 is not recessed in the planar direction during etching of the nitride semiconductor layer 13. The side surface of the via hole 16 is thus not notched in the intermediate layer 32, so that conduction failure of the via hole 16 is avoided. As a result, reduction in high frequency characteristics is avoided, and the nitride semiconductor device 103 can be manufactured with high yield.
In the nitride semiconductor devices 101 and 102 in Embodiments 1 and 2, conduction failure of the via holes 16 and 26 sometimes occurs as a result of the intermediate layer 12 being recessed during etching of the nitride semiconductor layer 13.
A method for manufacturing the nitride semiconductor device 104 in Embodiment 4 conforms to that in Embodiment 1 or in Embodiment 2. The thickness of the ground electrode 45 at the bottom of the via hole 16, however, can be increased by increasing a plating thickness when the ground electrode 45 is formed.
The embedded layer 49 may be made of a single metal element or an alloy. As the single metal element, one element selected from the group consisting of Cu, Ti, Al, Au, Ni, Nb, Pd, Pt, Cr, W, Ta, and Mo may be used. As the alloy, AuGe, AuGa, AuSn, and the like may be used.
The embedded layer 49 can be embedded in the via hole 16 by forming a feed layer over the first main surface S1 of the diamond layer 11 and in the via hole 16, and performing plating while leaving the feed layer only in the via hole 16 by patterning.
In the nitride semiconductor device 104 in Embodiment 4, the thickness of the ground electrode 15 at the bottom of the via hole 16 facing the electrode 14 is equal to or greater than the sum of the thicknesses of the nitride semiconductor layer 13 and the intermediate layer 12. Thus, even if the intermediate layer 12 is recessed in the planar direction during etching of the nitride semiconductor layer 13 when the via hole 16 is formed, conduction failure of the via hole 16 is avoided by the ground electrode 15. Reduction in high frequency characteristics is thus avoided, and the nitride semiconductor device 104 can be manufactured with high yield.
The nitride semiconductor device 104A in Embodiment 4 includes the embedded layer 49 embedded in the via hole 16 via the ground electrode 15. The sum of the thicknesses of the ground electrode 15 at the bottom of the via hole 16 facing the electrode 14 and the embedded layer 49 is equal to or greater than the sum of the thicknesses of the nitride semiconductor layer 13 and the intermediate layer 12. Thus, even if the intermediate layer 12 is recessed in the planar direction during etching of the nitride semiconductor layer 13 when the via hole 16 is formed, conduction failure of the via hole 16 is avoided by the ground electrode 15 and the embedded layer 49. Reduction in high frequency characteristics is thus avoided, and the nitride semiconductor device 104A can be manufactured with high yield.
A method for manufacturing the nitride semiconductor device 104A in Embodiment 4 further includes (e) after the step (d), embedding the embedded layer 49 made of a metal or an alloy in the via hole 16 as the second via hole. The sum of the thicknesses of the ground electrode 15 at the bottom of the via hole 16 facing the electrode 14 and the embedded layer 49 is equal to or greater than the sum of the thicknesses of the nitride semiconductor layer 13 and the intermediate layer 12. Thus, even if the intermediate layer 12 is recessed in the planar direction during etching of the nitride semiconductor layer 13 when the via hole 16 is formed, conduction failure of the via hole 16 is avoided by the ground electrode 15 and the embedded layer 49. Reduction in high frequency characteristics is thus avoided, and the nitride semiconductor device 104A can be manufactured with high yield.
In Embodiments 1 to 4, opening portions of the large-diameter via holes 16b and 26b are vertical, and are thus sometimes difficult to be covered with the ground electrodes 15 and 45 to cause conduction failure. In contrast, in the present embodiment, a large-diameter via hole 16b1 is tapered.
Steps to formation of the via hole 16c by laser processing illustrated in
A photoresist 59 having a tapered opening cross section is then formed to obtain a configuration illustrated in
The SiOx film 58 is dry etched with the photoresist 59 as a mask, so that a mask 57 having a tapered opening cross section is obtained as illustrated in
Dry etching is then performed using the mask 57, so that the diamond layer 11 at the bottom of the via hole 16c, the intermediate layer 12, and the nitride semiconductor layer 13 are removed to obtain the small-diameter via hole 16a, and a portion of the first main surface S1 of the diamond layer 11 exposed from an opening of the mask 57 is removed to obtain the tapered large-diameter via hole 16bl. The mask 57 is then removed as illustrated in
Next, the ground electrode 15 is formed over the first main surface S1 of the diamond layer 11 and in the via hole 16. The large-diameter via hole 16b1 is tapered, so that the ground electrode 15 has good coverage over the large-diameter via hole 16b1. The nitride semiconductor device 105 illustrated in
In the nitride semiconductor device 105 in Embodiment 5, the large-diameter via hole 16b1 is tapered. The ground electrode 15 thus has improved coverage over the large-diameter via hole 16b1, and conduction failure of the via hole 16 is suppressed. As a result, reduction in high frequency characteristics of the nitride semiconductor device 105 is suppressed, and the nitride semiconductor device 105 can be manufactured with high yield.
Embodiments can freely be combined with each other, and can be modified or omitted as appropriate. The foregoing description is in all aspects illustrative. It is understood that numerous unillustrated modifications can be devised.
11 diamond layer, 12, 32 intermediate layer, 13 nitride semiconductor layer, 14 electrode, 15, 45 ground electrode, 16, 16c, 26, 26c via hole, 16a, 26a small-diameter via hole, 16b, 16b1, 26b large-diameter via hole, 17 metal mask, 49 embedded layer, 57 mask, 58 SiOx film, 59 photoresist.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2021/005869 | 2/17/2021 | WO |
