Embodiments of the invention are in the field of semiconductor devices and, in particular, non-planar semiconductor devices having germanium-based active regions with release etch-passivation surfaces.
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Semiconductor devices formed from germanium-based material systems offer exceptionally high hole mobility in the transistor channels due to low effective mass along with reduced impurity scattering. Such devices provide high drive current performance and appear promising for future low power, high speed logic applications. However, significant improvements are still needed in the area of germanium-based devices.
Additionally, in the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, or gate-all-around devices, such as nanowires, have become more prevalent as device dimensions continue to scale down. Many different techniques have been attempted to reduce channel or external resistance of such transistors. However, significant improvements are still needed in the area of channel or external resistance suppression. Also, many different techniques have been attempted to manufacture devices with non-Si channel materials such as SiGe, Ge, and III-V materials. However, significant process improvements are still needed to integrate these materials on Si wafers.
Non-planar semiconductor devices having germanium-based active regions with release etch-passivation surfaces are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
One or more embodiments described herein are directed to approaches for forming germanium (Ge)-containing nanowire architectures. For example, in an embodiment one or more devices described herein may be characterized as a Ge-based device, a nanoribbon device, a nanowire device, a non-planar transistor, or a combination thereof. More specifically, one or more embodiments are directed to performing a release of rectangular-shaped Ge-containing nanowires from Ge/SiGe, Ge/Si, SiGe/SiGe, or SiGe/Si multilayer stacks. Use of a hydrosulfide-based chemistry (e.g., ammonium hydrosulfide), which acts as both a sacrificial layer etchant and a Ge passivating agent, allows for conservation of the Ge-containing nanowire material during the etch and, hence, the generation of rectangular shaped nanowires or nanoribbons.
Earlier attempts to releasing nanowires, e.g., to completely expose a channel region of a nanowire for gate-all-around fabrication, have employed chemistries which act as sacrificial layer etchants only. Such solutions may result in loss of the Ge-containing channel material and, consequently, prevent formation of rectangular-shaped Ge-containing nanowires having squared corners. The conventional chemistries do not effectively passivate Ge during the sacrificial layer etch. For example, under the etch conditions previously used to consume a sacrificial layer, Ge may be easily oxidized and etched. Consequently, if Ge is not adequately passivated during the etch, it will likely be consumed at a significant rate along with the sacrificial layer.
In order to address the above issues, one or more embodiments involve nanostructure release using a wet etchant that acts to passivate a preserved material while etching an adjacent sacrificial layer. That is, methods described herein employ chemistries that act more than only as mere sacrificial layer etchants. In earlier approaches, some Ge-containing channel material is consumed during the release etch, which can additionally prevent or hinder the formation of rectangular-shaped nanowires. In a first example of earlier attempts,
In a second example of earlier attempts,
In contrast to the processes described in association with
Referring to
In an embodiment, a germanium-based material is preserved against a sacrificial material having less germanium during a wet etch release operation. In one embodiment, a selective chemistry that removes the sacrificial material while preserving the germanium-based material is based on an aqueous solution of ammonium sulfide (NH4)2S which is in equilibrium with ammonium hydrosulfide (NH4)SH. As best understood, the latter component acts to etch the sacrificial layer. Either the ammonium sulfide (NH4)2S or the ammonium hydrosulfide (NH4)SH, or both, acts to passivate at least a portion of the germanium-based material by providing sulfur atoms to the surface of the material. Here, chemical passivation through chemisorption provides bridging or terminal S groups. For example,
The above described sulfur passivation need not be entirely uniform nor be provided to every exposed germanium atom to effectuate suitable passivation. For example in one embodiment, although sulfur passivation may not be detected everywhere on the germanium surface, e.g., the passivation may not be perfect chemically, a suitable electrical passivation for impeding etching of the germanium material may be achieved with mere partial coverage of sulfur atoms. Whether completely chemically passivating or only partially chemically passivating (but suitably electrically passivating), the above is in contrast to conventional etching, e.g., a hydroxide (OH−)-based wet etch which leads to GeOx formation and ultimate dissolution (i.e., no passivation mechanism).
More specifically, in an embodiment, an aqueous solution of approximately 10% by weight (NH4)2S is used to etch a silicon-rich material (selective to a germanium-rich material) at an etch rate of about 1 nanometer/minute at a temperature of approximately 75 degrees Celsius. In a more general embodiment, an aqueous solution of (NH4)2S with a % weight approximately in the range of 1%-25% of (NH4)2S is used. The pH of the solution is basic at approximately 9+/−1. In general, a workable etch rate is not observed below approximately 55 degrees Celsius. As for concentration, no significant concentration modulation is observed approximately between 55 and 75 degrees Celsius. In a general embodiment, a solution of (NH4)2S having a temperature approximately in the range of 40-75 degrees Celsius is used. Above approximately 75 degrees Celsius, however, concentration modulation of the (NH4)2S may be used to vary the etch rate of the silicon-rich material. However, selectivity against the germanium-rich material may be impacted detrimentally. Furthermore, although sonication may be used for etch rate tunability, a non-agitated solution may be preferred when handling structures with very small features undergoing a release etch (e.g., nanowire release).
More generally, in an embodiment, a silicon-rich release or sacrificial layer is etched with high selectivity to a germanium-rich semiconductor structure that is preserved. Such etches may be effective for, e.g., etching an essentially pure silicon release layer with selectivity to an essentially pure germanium structure, such as a germanium nanowire, in accordance with one embodiment. However, intermediate compositions may also benefit from etching approaches described herein. For example, in another embodiment, a silicon germanium layer is removed with selectivity to an essentially pure germanium structure. In another embodiment, a silicon germanium release layer having a first germanium concentration is removed with selectivity to a silicon germanium structure having a second, higher, germanium concentration. In yet another embodiment, an essentially pure silicon release layer is removed with selectivity to a silicon germanium structure. In a specific embodiment, an approximately Si0.5Ge0.5 release layer is removed with selectivity to an essentially pure germanium structure. The release layer in this case has a composition suitable for germanium growth thereon but also sufficiently different for selective etching.
Semiconductor devices based on a released stack such as stack 210 (described above) or semiconductor devices 400 and 600 (described below) may be a semiconductor device incorporating a gate, a channel region and a pair of source/drain regions. In an embodiment, the semiconductor device is one such as, but not limited to, a MOS-FET or a Microelectromechanical System (MEMS). In one embodiment, the semiconductor device is a three-dimensional MOS-FET and is an isolated device or is one device in a plurality of nested devices. As will be appreciated for a typical integrated circuit, both N- and P-channel transistors may be fabricated on a single substrate to form a CMOS integrated circuit. Furthermore, additional interconnect wiring may be fabricated in order to integrate such devices into an integrated circuit.
As mentioned above, a selective wet etch may be used to fabricate a germanium-based nanowire device (see more detailed description in association with
In a first example,
Referring to
Each of the nanowires 404 includes a channel region 406 disposed in the nanowire. The channel region 406 has a length (L). Referring to
In an embodiment, the channel region 406 includes a germanium-rich material portion 406A and a passivated surface 406B. It is to be understood that, for illustrative purposes, the relative thickness of the passivated surface 406B is depicted as much greater than would normally be expected. In an embodiment, the germanium-rich material portion 406A is composed of germanium (Ge) or silicon germanium (SiGe) and the passivated surface 406B is composed of germanium-sulfur bonds.
In an embodiment, the nanowires 404 may be sized as wires or ribbons (the latter described below), and may have squared-off or rounded corners. In any case, however, in an embodiment, the sizing and shaping of each channel region is essentially the same as prior to a release etch used to fabricate the discrete channel regions 406. In an embodiment, the nanowires 404 are uniaxially strained nanowires. The uniaxially strained nanowire or plurality of nanowires may be uniaxially strained with tensile strain or with compressive strain, e.g., for NMOS or PMOS, respectively.
The width and height of each of the channel regions 406 is shown as approximately the same in
Referring again to
Referring again to
Although the device 400 described above is for a single device, e.g., an NMOS or a PMOS device, a CMOS architecture may also be formed to include both NMOS and PMOS nanowire-based devices disposed on or above the same substrate, e.g., as described in association with
Referring again to
In an embodiment, referring again to
In one embodiment, the gate electrode is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer.
In an embodiment, the spacers 416 are composed of an insulative dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride or silicon nitride. The contacts 414 are, in an embodiment, fabricated from a metal species. The metal species may be a pure metal, such as nickel or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).
Referring again to
It is to be understood that although the device 400 described above is for a single device, a CMOS architecture may also be formed to include both NMOS and PMOS nanowire-based devices disposed on or above the same substrate. Thus, in another aspect, methods of fabricating nanowires using passivating etchants are provided.
A method of fabricating a nanowire semiconductor structure may, in an embodiment, include forming both a PMOS nanowire-based semiconductor device and an adjacent NMOS nanowire-based semiconductor device. Each device may be fabricated by forming a nanowire above a substrate. In a specific embodiment ultimately providing the formation of two nanowires for each of the NMOS and PMOS nanowire-based semiconductor devices,
Referring to
In a specific example showing the formation of three gate structures,
Following patterning to form the three sacrificial gates 514A, 514B, and 514C, spacers may be formed on the sidewalls of the three sacrificial gates 514A, 514B, and 514C, doping may be performed in regions 520 of the fin-type structure 512 shown in
The sacrificial gates 514A, 514B, and 514C may then be removed, e.g., in a replacement gate or gate-last process flow, to expose channel portions of the fin-type structure 512. Referring to the left-hand portion of
In an embodiment, etching the portion of the silicon-rich release layer includes passivating exposed portions of the germanium-rich nanowire at the same time. In one such embodiment, a wet etchant based on an aqueous solution of approximately 10% by weight (NH4)2S is used. In a specific such embodiment, the etching is performed at a temperature approximately in the range of 55-75 degrees Celsius. In another specific such embodiment, the etching is performed at a temperature of approximately 75 degrees Celsius. In another specific such embodiment an etch rate of about 1 nanometer/minute is used for the silicon-rich material. In an embodiment, a pH of approximately 9 is used. In an embodiment, passivating exposed portions of the germanium-rich layers includes forming terminal sulfur-germanium bonds or bridging sulfur-germanium bonds, or both. In an embodiment, passivating exposed portions of the germanium-rich layers includes incompletely chemically passivating the exposed portions of the germanium-rich layers but sufficiently electrically passivating the exposed portions of the germanium-rich layers to inhibit etching of the exposed portions of the germanium-rich layers during etching of the silicon-rich release layers.
Thus, in an embodiment, referring to the right-hand portion of
Following formation of the discrete channel regions as depicted in
In another example,
Referring to
In an embodiment, not viewable from the perspective of
Thus, one or more embodiments described herein are targeted at active region arrangements having passivated surfaces. Although described above with respect to benefits for non-planar and gate-all-around devices, benefits may also be achieved for planar devices without gate wrap-around features. Thus, such arrangements may be included to form high mobility material-based transistors such as planar devices, fin or tri-gate based devices, and gate all around devices, including nanowire-based devices. It is to be understood that formation of materials such as the silicon-rich and germanium-rich material layers described herein may be performed by techniques such as, but not limited to, chemical vapor deposition (CVD) or molecular beam epitaxy (MBE), or other like processes.
Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.
In further implementations, another component housed within the computing device 700 may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.
In various implementations, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.
Thus, embodiments of the present invention include non-planar semiconductor devices having germanium-based active regions with release etch-passivation surfaces.
In an embodiment, a semiconductor device includes a vertical arrangement of a plurality of germanium-rich nanowires disposed above a substrate. Each nanowire includes a channel region having a sulfur-passivated outer surface. A gate stack is disposed on and completely surrounds the channel region of each of the germanium-rich nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the sulfur-passivated outer surface and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the germanium-rich nanowires.
In one embodiment, the sulfur-passivated outer surface of each channel region includes bridging sulfur atoms, each bridging sulfur atom bonded to two or more germanium atoms of the corresponding germanium-rich nanowire.
In one embodiment, the sulfur-passivated outer surface of each channel region includes terminal sulfur atoms, each terminal sulfur atom bonded to a germanium atom of the corresponding germanium-rich nanowire.
In one embodiment, the semiconductor device further includes a dielectric spacer on either side of the gate stack and over the vertical arrangement of the plurality of germanium-rich nanowires. An intervening silicon-rich semiconductor material is disposed between the portions of the germanium-rich nanowires underneath each spacer.
In one embodiment, the germanium-rich nanowires are composed essentially of germanium, and the intervening silicon-rich semiconductor material is composed essentially of silicon germanium or silicon.
In one embodiment, the germanium-rich nanowires are composed essentially of silicon germanium having a first concentration of germanium, and the intervening silicon-rich semiconductor material is composed essentially of silicon germanium having a second, lower, concentration of germanium.
In one embodiment, the germanium-rich nanowires are composed essentially of silicon germanium, and the intervening silicon-rich semiconductor material are composed essentially of silicon.
In one embodiment, the source regions of each germanium-rich nanowire are formed in the germanium-rich nanowire and are discrete relative to one another. The drain regions of each germanium-rich nanowire are formed in the germanium-rich nanowire and are discrete relative to one another. The source and drain regions of each germanium-rich nanowire have a sulfur-passivated outer surface.
In one embodiment, the semiconductor device further includes a conductive source contact surrounding each of the discrete source regions. A conductive drain contact surrounds each of the discrete drain regions.
In one embodiment, the gate dielectric layer is a high-k gate dielectric layer, and the gate electrode is a metal gate electrode.
In an embodiment, a semiconductor device includes a hetero-structure disposed above a substrate and having a three-dimensional germanium-rich semiconductor body with a channel region including a sulfur-passivated outer surface. A gate stack is disposed on and surrounds the channel region. The gate stack includes a gate dielectric layer disposed on the sulfur-passivated outer surface of the channel region and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of channel region of the three-dimensional semiconductor body.
In one embodiment, the sulfur-passivated outer surface of the channel region includes bridging sulfur atoms, each bridging sulfur atom bonded to two or more germanium atoms of the three-dimensional germanium-rich semiconductor body.
In one embodiment, the sulfur-passivated outer surface of the channel region includes terminal sulfur atoms, each terminal sulfur atom bonded to a germanium atom of the three-dimensional germanium-rich semiconductor body.
In one embodiment, the semiconductor device further includes a dielectric spacer on either side of the gate stack and over the heterostructure. An intervening silicon-rich semiconductor material is disposed below portions of the three-dimensional germanium-rich semiconductor body underneath each spacer.
In one embodiment, the three-dimensional germanium-rich semiconductor body is composed essentially of germanium, and the intervening silicon-rich semiconductor material is composed essentially of silicon germanium or silicon.
In one embodiment, the three-dimensional germanium-rich semiconductor body is composed essentially of silicon germanium having a first concentration of germanium, and the intervening silicon-rich semiconductor material is composed essentially of silicon germanium having a second, lower, concentration of germanium.
In one embodiment, the three-dimensional germanium-rich semiconductor body is composed essentially of silicon germanium, and the intervening silicon-rich semiconductor material is composed essentially of silicon.
In one embodiment, the device is a tri-gate device.
In one embodiment, the device is a fin-fet device.
In one embodiment, the gate dielectric layer is a high-k gate dielectric layer, and the gate electrode is a metal gate electrode.
In an embodiment, a method of fabricating a nanowire-based semiconductor structure includes forming a silicon-rich release layer above a substrate. The method also includes forming a germanium-rich active layer on the silicon-rich release layer. The method also includes forming, from the germanium-rich active layer, a germanium-rich nanowire. The method also includes etching at least a portion of the silicon-rich release layer to form a discrete channel region for the germanium-rich nanowire. The etching includes etching the portion of the silicon-rich release layer while passivating exposed portions of the germanium-rich nanowire. The method also includes forming a gate electrode stack completely surrounding the discrete channel region of the germanium-rich nanowire.
In one embodiment, etching the portion of the silicon-rich release layer while passivating exposed portions of the germanium-rich nanowire includes etching with a wet etchant composed of an aqueous solution of approximately 10% by weight (NH4)2S.
In one embodiment, etching with the wet etchant includes etching at a temperature approximately in the range of 55-75 degrees Celsius.
In one embodiment, etching with the wet etchant includes etching at a temperature of approximately 75 degrees Celsius.
In one embodiment, etching with the wet etchant includes using an etch rate of about 1 nanometer/minute for the silicon-rich material.
In one embodiment, etching with the wet etchant includes using a pH of approximately 9.
In one embodiment, passivating exposed portions of the germanium-rich nanowire includes forming terminal sulfur-germanium bonds or bridging sulfur-germanium bonds, or both.
In one embodiment, passivating exposed portions of the germanium-rich nanowire includes incompletely chemically passivating the exposed portions of the germanium-rich nanowire but sufficiently electrically passivating the exposed portions of the germanium-rich nanowire to inhibit etching of the exposed portions of the germanium-rich nanowire during etching of the silicon-rich release layer.
In one embodiment, etching the portion of the silicon-rich release layer to form the discrete channel region includes etching a material composed essentially of silicon or silicon germanium selective to a nanowire composed essentially of germanium.
In one embodiment, etching the portion of the silicon-rich release layer to form the discrete channel region includes etching a material composed essentially of silicon or silicon germanium with a first germanium concentration selective to a nanowire composed essentially of silicon germanium with a second, higher, germanium concentration.