Patent Application
20080123393
The present invention relates to a nonvolatile semiconductor memory device, more specifically, a nonvolatile semiconductor memory device using a resistance memory element having a plurality of resistance states of different resistance values and a method of writing into the same.
Recently, as a new memory device, a nonvolatile semiconductor memory device called RRAM (Resistance Random Access Memory) is noted. The RRAM uses a resistance memory element which has a plurality of resistance states of different resistance values, which are changed by electric stimulations applied from the outside and whose high resistance state and low resistance state are corresponded to, e.g., information “0” and “1” to be used as a memory element. The RRAM highly potentially has high speed, large capacities, low electric power consumption, etc. and is considered prospective.
The resistance memory element has a resistance memory material whose resistance states are changed by the application of voltages sandwiched between a pair of electrodes. As the typical resistance memory material, oxide materials containing transition metals are known and, depending on the electric characteristics, can be classified largely in two.
One uses voltages of polarities different from each other so as to change the resistance state between the high resistance state and the low resistance state and includes SrTiO3 and SrZrO3, and Pr1-xCaxMnO3, La1-xCaxMnO3, etc., which exhibit CMR (Colossal Magneto-Resistance). The RRAM using such bipolar material is disclosed in, e.g., U.S. Pat. No. 6,473,332 (herein after called Reference 1), A. Beck et al., Appl. Phys. Lett., Vol. 77, p. 139 (2000) (herein after called Reference 2) and W. W. Zhuang et al., Tech. Digest IEDM 2002, p. 193 (herein after called Reference 3).
The other uses voltages of the same polarity so as to change the resistance state between the high resistance state and the low resistance state and includes oxides of single transition metals, etc., e.g., NiOx, TiOx. The RRAM using such unipolar material is disclosed in, e.g., I. G. Baek et al., Tech. Digest IEDM 2004, p. 587 (herein after called Reference 4).
The other related arts are discloses in, e.g., Japanese published unexamined patent application No. 2005-025914.
In the semiconductor memory device, to increase the memory capacity per a unit area, downsizing of the elements themselves is being studied, and also the multiple-valued memory is being studied. The multiple-valued memory is different from the usual binary memory, in which one memory cell can take either state of “0” and “1” but is a memory element in which one memory cell can take three or more states.
In the RRAM as well, studies of the multiple-valued memory are being made. For example, Reference 1 and Reference 3 disclose that when the amplitude width or the width of the voltage pulse to be applied to bipolar resistance memory materials is varied, corresponding to this, the absolute value of resistance of the low resistance state is varied. The possibility of forming a multiple-valued memory by making use of not only two resistances, a high resistance and a low resistance, but also low resistance states of middle resistances between both resistances and others is also disclosed.
However, by the method of controlling the resistance value by the amplitude width or the width of an applied voltage, it is difficult to realize more than two resistance states with good reproducibility, and the multiple-valued memory using bipolar resistance memory materials has not been realized.
For unipolar resistance memory materials, a report of the binary memory is disclosed only in, e.g., Reference 4, and techniques for the value multiplexing has not been proposed.
In the technique of applying a voltage to the resistance memory element to change the resistance memory material from the high resistance state to the low resistance state, larger current than required for rewriting flows due to the abrupt resistance value decreased. Such large current has been a cause for accelerating the degradation of the resistance memory material.
According to one aspect of the present invention, there is provided a method of writing into a nonvolatile semiconductor memory device including a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, comprising: applying the voltage to the resistance memory element for switching from the high resistance state to the low resistance state, while a value of a current to flow in the resistance memory element being limited to thereby memorize the low resistance state of a low resistance value corresponding to the limited value of the current.
The nonvolatile semiconductor memory device and method of writing into the same according to a first embodiment of the present invention will be explained with reference to
First, the basic operation of the resistance memory element will be explained with reference to
The resistance memory element includes the resistance memory material sandwiched between a pair of electrodes. Many of the resistance memory material are oxide materials containing transition metals, and the resistance memory material is divided largely in two, depending on differences in the electric characteristics.
One of them uses voltages of different polarities so as to change the resistance states between the high resistance state and the low resistance state and includes SrTiO3 and SrZrO3 doped with a trace of an impurity, such as chrome (Cr) or others, and Pr1-xCaxMnO3 and La1-xCaxMnO3, etc., which exhibit CMR (Colossal Magneto-Resistance). Such resistance memory material which requires voltages of different polarities so as to rewrite the resistance state will be hereinafter called the bipolar resistance memory material.
The other of them is materials which require voltages of the same polarity so as to change the resistance states between the high resistance state and the low resistance state and includes oxides, etc., containing a single transition metal, such as NiOx and TiOx. Such resistance memory materials which require voltages of the same polarity for rewriting the resistance states will be hereinafter called the unipolar resistance memory material.
It is assumed that in the initial state, the resistance memory element is in the high resistance state.
As an applied voltage increases gradually from 0 V to negative voltages, the current flowing at this time changes along the curve “a” in the arrowed direction, and its absolute value gradually increases. When the applied negative voltage is further increased and exceed about −0.5 V, the resistance memory element switches from the high resistance state to the low resistance state. Accompanying this, the absolute value of the current abruptly increases, and the current-voltage characteristics transits from the point A to the point B. In the following explanation, the operation of changing the resistance memory element from the high resistance state to the low resistance state is called “set”.
As the negative voltage is gradually decreased from the state at the point B, the current changes along the curve “b” in the arrowed direction, and its absolute value gradually decreases. When the applied voltage returns to 0 V, the current also becomes 0 A.
As the applied voltage increases gradually from 0 V to positive voltages, the current value changes along the curve “c” in the arrowed direction, and its absolute values gradually increases. The applied positive voltage further increases and exceeds about 0.5 V, the resistance memory element switches from the low resistance state to the high resistance state. Accompanying this, the absolute value of the current abruptly decreases, and the current-voltage characteristics transit from the point C to the point D. In the following explanation, the operation of changing the resistance memory element from the low resistance state to the high resistance state is called “reset”.
As the positive voltage decreases from the state at the point D, the current changes along the curve “d” in the arrowed direction, and its absolute value gradually decreases. When the applied voltage returns to 0 V, the current also becomes 0 A.
The respective resistance states are stable in the range of about ±0.5 V and can be retained even when the electric power source is turned off. That is, in the high resistance state, when an applied voltage is lower than the absolute value of the voltage at the point A, the current-voltage characteristics changes linearly along the curves “a” and “d”, and the high resistance state is retained. Similarly, in the low resistance state, when an applied voltage is lower than the absolute value of the voltage at the point. C, the current-voltage characteristics changes linearly along the curves “b” and “c”, and the low resistance state is retained.
As described above, for the resistance memory element using the bipolar resistance memory material, to change the resistance state between the high resistance state and the low resistance state, voltages of different polarities are applied.
It is assumed that in the initial state, the resistance memory element is in the high resistance state.
As an applied voltage is increased gradually from 0 V, the current increases along the curve “a” in the arrowed direction, and its absolute value gradually increases. When the applied voltage gradually increases and exceeds about 1.3 V, the resistance memory element is switched from the high resistance state to the low resistance state (set). Accompanying this, the absolute value of the current abruptly increases, and the current-voltage characteristics transit from the point A to the point B. In
As the voltage decreases gradually from the state at the point B, the current changes along the curve “b” in the arrowed direction, and its absolute value gradually decreases. When the applied voltage returns to 0 V, the current also becomes 0 A.
As the applied voltage again increases gradually from 0 V, the current changes along the curve “c” in the arrowed direction, and its absolute value gradually increases. When the applied positive voltage further increases and exceeds about 1.2 V, the resistance memory element is switched from the low resistance state to the high resistance state (reset). Accompanying this, the absolute value of the current abruptly decreases, and the current-voltage characteristics transits from the point C to the point D.
As the voltage is decreased gradually from the point D, the current changes in the arrowed direction along the curve “d”, and the absolute value is gradually decreased. When the applied voltage returns to 0 V, the current also becomes 0 A.
The respective resistance states are stable not more than about 1.0 V and are retained when the electric power is turned off. That is, in the high resistance state, when the applied voltage is below the voltage at the point A, the current-voltage characteristics linearly change along the curve “a”, and the high resistance state is retained. Similarly, in the low resistance state, when the applied voltage is below the voltage at the point C, the current-voltage characteristics change along the curve “c”, and the low resistance state is retained.
As described above, in the resistance memory element using the unipolar resistance memory material, to change the resistance state between the high resistance state and the low resistance state, voltages of the same polarity are applied.
As described above, because of the abrupt change of the resistance value in setting the resistance memory element at the low resistance state, there is a risk that the flowing current might be abruptly increased to break the element. Accordingly, it is preferable to provide a current limiter for prohibiting the current of above a prescribed value to the element when the resistance memory element is set at the low resistance state. The current limiter can be realized simply by connecting serially to the resistance memory element a resistor having a resistance value which cannot be ignored with respect to a resistance value of the resistance memory element in the low resistance state.
The inventor of the present application made earnest studies of this current limiter, it has been evident for the first time that a resistance value with the resistance memory element set at the low resistance state can be controlled by a set value of the current limiter. By means of the resistance memory element using a unipolar resistance memory material, a method of controlling the resistance value by the set value of the current limiter will be explained.
As shown in
As the voltage is gradually increased again after having returned to the origin, with the set value of the current limiter being 10 mA, the current value goes on increase along the curve “a”, with the set value of the current limiter being 15 mA, the current value goes on increase along the curve “b”, and with the set value of the current limiter being 20 mA, the current value goes on increase along the curve “c”. That is, the resistance memory element is set at a smaller resistance value as the set value of the current limiter is larger.
As the applied voltage is further increased, the current value abruptly decreases, and the resistance memory element is reset at the high resistance state. Then, as the applied voltage is decreased, the current value goes on decrease along the curve “d” and returns to the origin. The voltage necessary for the reset is, as shown in
As described above, the set value of the current limiter in setting the resistance memory element at the low resistance state is changed, whereby the resistance value of the resistance memory element in the low resistance state can be controlled. The resistance value at this time can be preserved unless the resistance memory element is reset. Thus, the set value of the current limiter is changed to thereby set the resistance memory element, whereby the resistance memory element can be used a multiple-valued memory.
The resistance memory element formed of the above-described material cannot have the characteristics shown in
In the initial state immediately after the element has been formed, as shown in
When a voltage higher than the breakdown voltage is applied in the initial state, as shown in
The resistance memory element in the initial state before subjected to the forming has a high resistance value, and this high resistance state might be misunderstood to be the high resistance state after the forming. Then, in the specification of the present application, the high resistance state means the high resistance state of the resistance memory element after subjected to the forming, the low resistance state means the low resistance state of the resistance memory element after subjected to the forming, and the initial state is the state of the resistance memory element before subjected to the forming.
The above-explanation has been made for the unipolar resistance memory material, but the explanation is the same with the bipolar resistance memory material.
Next, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to
As shown in
The resistance memory element 12 includes a resistance memory material sandwiched between a pair of electrodes. The resistance memory material may be a bipolar resistance memory material or a unipolar resistance memory material. In the present embodiment, the resistance memory material is a unipolar resistance material of, e.g. TiOx.
In the column direction, a plurality of word lines WL1, /WL1, WL2, /WL2 . . . are arranged, forming signal lines common among the memory cells 10 arranged in the column direction. In the column direction, source lines SL1, SL2 . . . are arranged, forming signal lines common among the memory cells 10 arranged column direction. The source lines SL are provided each for two word lines WL.
In the row direction (horizontally in the drawing), a plurality of bit lines BL1, BL2, BL3, BL4 . . . are arranged, forming signal lines common among the memory cells 10 arranged in the row direction. To each bit line BL, a bit line select transistor 16 as a variable resistor is connected.
Next, the method of writing into the nonvolatile semiconductor memory device according to the present embodiment shown in
First, the rewriting operation from the high resistance state to the low resistance state, i.e., the setting operation will be explained with reference to
First, a prescribed voltage is applied to the gate terminal of the bit line select transistor 16 connected to the bit line BL1 to turn on the bit line select transistor 16 (refer to
Simultaneously with turning on the bit line select transistor 16, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14 (refer to
The source line SL is connected to a reference voltage, e.g., 0 V, which is the ground potential (refer to
Next, to the drain terminal of the bit line select transistor 16, a bias voltage which is the same as a voltage required to set the resistance memory element 12 or a little larger than the voltage is applied (refer to
At this time, the resistance value RH of the resistance memory element 12 is sufficiently large in comparison with the channel resistance RBS of the bit line select transistor 16 and the channel resistance RCS of the cell select transistor, and most of the bias voltage is applied to the resistance memory element 12. Thus, the resistance memory element 12 is changed from the high resistance state to the low resistance state.
When the resistance value of the resistance memory element 12 is changed from the resistance value RH to the resistance value RL, the channel resistance RBS of the bit line select transistor 16 becomes unignorably large in comparison with the resistance value RL, and the ratio of the voltages to be divided to the resistance memory element 12 and the bit line select transistor 16 becomes RL: RBS. Accordingly, the gate voltage of the bit line select transistor 16 is set so that the channel resistance RBS of the bit line select transistor 16 becomes, e.g., RBS=2×RL, whereby ⅓ of the bias voltage is divided to the resistance memory element 12.
The channel resistance RBS of the bit line select transistor 16 can be set at an arbitrary value as far as the performance of the bit line select transistor 16 permits, which permits the voltage to be applied to the resistance memory element 12, i.e., the current flowing through the resistance memory element 12 to be set at an arbitrary value by the gate voltage of the bit line select transistor 16.
In short, the current flowing in the resistance memory element 12 can be limited to a prescribed value by the gate voltage of the bit line select transistor 16, and by this current limitation, the resistance value of the resistance memory element 12 can be controlled. For example, as shown in
Then, after the bias voltage to be applied to the bit line BL1 is returned to zero, the voltage to be applied to the gate terminal of the bit line select transistor 16 and the voltage to be applied to the word line WL are turned off, and the setting operation is completed (refer to
When the low resistance state having a first resistance value is rewritten to the low resistance state having a second resistance value, after the resetting operation to be described later has been made, the resistance memory element 12 is set anew at the low resistance state of the second resistance value.
Next, the rewriting operation from the low resistance state to the high resistance state, i.e., resetting operation will be explained with reference to
First, a prescribed voltage is applied to the gate terminal of the bit line select transistor 16 connected to the bit line BL1 to turn on the bit line select transistor 16 (refer to
Simultaneously with turning on the bit line select transistor 16, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14 (refer to
The source line SL1 is connected to a reference potential, e.g., 0 V, which is the ground potential (refer to
Next, to the drain terminal of the bit line select transistor 16, a bias voltage which is the same as or a little larger than the voltage necessary to reset the resistance memory element 12 is applied (refer to
At this time, the channel resistance RBS of the bit line select transistor 16, and channel resistance RCS of the cell select transistor 14 are sufficiently smaller than the resistance value RL of the resistance memory element 12, and most of the applied bias voltage is applied to the resistance memory element 12. Thus, the resistance memory element 12 is changed from the low resistance state to the high resistance state.
Thus, in the resetting process, instantaneously with the resistance memory element 12 having switched to the high resistance state, almost all the bias voltage is divided to the resistance memory element 12, and it is necessary to prevent the resistance memory element 12 from being set again by this bias voltage. To this end, the bias voltage to be applied to the bit line BL must be smaller than a voltage necessary for the setting.
In short, in the resetting process, the gate voltages of these transistors are adjusted so that the channel resistance RBS of the bit line select transistor 16 and the channel resistance RCS of the cell select transistor 14 are sufficiently smaller than the resistance value RL of the resistance memory element 12 while the bias voltage to be applied to the bit line BL is set to be not less than the voltage necessary for the resetting and less than the voltage necessary for the setting.
Then, after the bias voltage to be applied to the bit line BL has been returned to zero, the voltage to be applied to the gate terminal of the bit line select transistor 16 and the voltage to be applied to the word line WL are turned off, and the resetting operation is completed (refer to
In the nonvolatile semiconductor memory device according to the present embodiment, as shown in
Then, the method of reading the nonvolatile semiconductor memory device according to the present embodiment shown in
First, a prescribed voltage is applied to the gate terminal of the bit line select transistor 16 to turn on the bit line select transistor 16 (refer to
Simultaneously with turning on the bit line select transistor 16, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14 (refer to
The source line SL1 is connected to a reference potential, e.g., 0 V, which is the ground potential (refer to
Next, a prescribed bias voltage is applied to the drain terminal of the bit line select transistor 16 (refer to
For example, when the resistance memory element 12 has the current-voltage characteristics shown in
When such bias voltage is applied to the drain terminal of the bit line select transistor 16, current corresponding to a resistance value of the resistance memory element 12 flows in the bit line BL1. Accordingly, the value of the current flowing in the bit line BL1 is detected, whereby it can be read what resistance state the resistance memory element 12 has.
As described above, according to the present embodiment, when the resistance memory element is switched from the high resistance state to the low resistance state, the resistor is serially connected to the resistance memory element to thereby prevent the flow of large current to the resistance memory element, whereby the breakage and degradation of the resistance memory element due to the flow of the large current can be prevented. By the resistance value of the resistor, the resistance value of the resistance memory element in the low resistance state can be controlled. Thus, the multiple-valued memory can be easily realized.
The nonvolatile semiconductor memory device and the method of writing into the same according to a second embodiment of the present invention will be explained. The same members of the present embodiment as those of the nonvolatile semiconductor memory device, the method of writing into the same and the method of reading the same according to the first embodiment shown in
The nonvolatile semiconductor memory device according to the present embodiment is the same as the nonvolatile semiconductor memory device according to the first embodiment shown in
Next, the method of writing into the nonvolatile semiconductor memory device according to the present embodiment will be explained. The method of writing into the nonvolatile semiconductor memory device according to the present embodiment is basically the same as the method of writing into the nonvolatile semiconductor memory device according to the first embodiment except the polarity of the bias voltage.
First, the rewriting operation from the high resistance state to the low resistance state, i.e., the setting operation will be explained. The memory cell 10 to be rewritten is a memory cell 10 connected to a word line WL1 and to a bit line BL1.
First, a prescribed voltage is applied to the gate terminal of the bit line select transistor 16 connected to the bit line BL1 to turn on the bit line select transistor 16. At this time, the voltage to be applied to the gate terminal is controlled so that the channel resistance RBS of the bit line select transistor 16 is sufficiently smaller than the resistance value RH of the resistance memory element 12 in the high resistance state and has a value which cannot be ignored in comparison with the resistance value RL of the resistance memory element 12 in the low resistance state.
Simultaneously with turning on the bit line select transistor 16, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14. At this time, the voltage to be applied to the word line WL1 is controlled so that the channel resistance RCS of the cell select transistor 14 has a small value which can be ignored in comparison with the resistance value RL of the resistance memory element 12 in the low resistance state.
The source line SL is connected to a reference potential, e.g., 0 V, which is the ground potential.
Then, to the drain terminal of the bit line select transistor 16, a negative bias voltage which is the same as the voltage necessary to set the resistance memory element 12 or whose absolute value is a little larger than the voltage is applied. Thus, a current passage from the source line SL1 via the cell select transistor 14, the resistance memory element 12, the bit line BL1 and the bit line select transistor 16 is formed, and the applied bias voltage is divided to the resistance memory element 12, the bit line select transistor 16 and the cell select transistor 14, corresponding to the resistance value RH of the resistance memory element 12, the channel resistance RBS of the bit line select transistor 16 and the channel resistance RCS of the cell select transistor 14.
At this time, the resistance value RH of the resistance memory element 12 is sufficiently large in comparison with the channel resistance RBS of the bit line select transistor 16 and the channel resistance RCS of the cell select transistor, and most of the bias voltage is applied to the resistance memory element 12. Thus, the resistance memory element 12 is changed from the high resistance state to the low resistance state.
When the resistance value of the resistance memory element 12 has been changed from the resistance value RH to the resistance value RL, the channel resistance RBS of the bit line select transistor 16 becomes unigonorably large in comparison with the resistance value RL, and the ratio of the voltage to be divided to the resistance memory element 12 and the bit line select transistor 16 becomes RL: RBS. Accordingly, with the gate voltage of the bit line select transistor 16 set so that the channel resistance RBS of the bit line select transistor 16 becomes, e.g., RBS=2×RL, ⅓ of the bias voltage is divided to the resistance memory element 12.
The channel resistance RBS of the bit line select transistor 16 can be set at an arbitrary value as far as the performance of the bit line select transistor 16 permits, which permits the voltage to be applied to the resistance memory element 12, i.e., the current flowing through the resistance memory element 12 to be set at an arbitrary value by the gate voltage of the bit line select transistor 16. In short, the current to flow in the resistance memory element 12 can be limited to a prescribed value by the gate voltage of the bit line select transistor 16, and by this current limitation, the resistance value of the resistance memory element 12 can be controlled.
Next, after the bias voltage to be applied to the bit line BL1 has been returned to zero, the voltage to be applied to the gate terminal of the bit line select transistor 16 and the voltage to be applied to the word line WL1 are turned off, and the setting operation is completed.
Then, the operation of rewriting from the low resistance state to the high resistance state, i.e., the resetting operation will be explained. The memory cell to be rewritten is a memory cell 10 connected to the word line WL1 and the bit line BL1.
First, a prescribed voltage is applied to the gate terminal of the bit line select transistor 16 connected to the bit line BL1 to turn on the bit line select transistor 16. At this time, the voltage to be applied to the gate terminal is controlled so that the channel resistance RBS of the bit line select transistor 16 becomes sufficiently smaller than the resistance value RL of the resistance memory element 12 in the low resistance state.
Simultaneously with turning on the bit line select transistor 16, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14. At this time, the voltage to be applied to the word line WL1 is controlled so that the channel resistance RCS of the cell select transistor 14 becomes sufficiently smaller than the resistance value RL of the resistance memory element 12 in the low resistance state.
The source line SL1 is connected to a reference potential, e.g., 0 V, which is the ground potential.
Next, to the drain terminal of the bit line select transistor 16, a positive bias voltage which is the same as the voltage necessary to reset the resistance memory element 12 or has an absolute value which is a little large than the voltage is applied. Thus, a current passage from the source line SL1 via the cell select transistor 14, the resistance memory element 12, the bit line BL1 and the bit line select transistor 16 is formed, and the applied bias voltage is divided to the resistance memory element 12, the bit line select transistor 16 and the cell select transistor 14, corresponding to the resistance value RL of the resistance memory element 12, the channel resistance RBS of the bit line select transistor 16 and the channel resistance RCS of the cell select transistor 14.
At this time, the channel resistance RBS of the bit line select transistor 16 and the channel resistance RCS of the cell select transistor 14 are sufficiently smaller than the resistance value RL of the resistance memory element 12, whereby most of the applied bias voltage is applied to the resistance memory element 12. Thus, the resistance memory element 12 changes from the low resistance state to the high resistance state.
Then, after the bias voltage to be applied to the bit line BL1 has been returned to zero, the voltage to be applied to the gate terminal of the bit line select transistor 16 and the voltage to be applied to the word line WL1 are turned off, and the resetting operation is completed.
In the nonvolatile semiconductor memory device according to the present embodiment, as shown in
Next, the method of reading the nonvolatile semiconductor memory device according to the present embodiment will be explained. The memory cell 10 to be read is the memory cell 10 connected to the word line WL1 and the bit line BL1.
First, a prescribed voltage is applied to the gate terminal of the bit line select transistor 16 to run on the bit line select transistor 16. At this time, the voltage to be applied to the gate terminal is controlled so that the channel resistance RBS of the bit line select transistor 16 becomes sufficiently smaller than the resistance value RL of the resistance memory element 12.
Simultaneously with turning on the bit line select transistor 16, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14. At this time, the voltage to be applied to the word line WL1 is controlled so that the channel resistance RCS of the cell select transistor 14 is sufficiently smaller than the resistance value RL of the resistance memory element 12 in the low resistance state.
The source line SL1 is connected to a reference potential, e.g., 0 V, which is the ground potential.
Next, to the drain terminal of the bit line select transistor 16, a prescribed bias voltage is applied. This bias voltage is set in accordance with memory characteristics given by the lowest current limitation value. That is, the value of the bias voltage is set so that even with the resistance memory element 12 in any resistance state, neither the setting nor the resetting is caused by the applied voltage.
When such bias voltage is applied to the drain terminal of the bit line select transistor 16, current corresponding to a resistance value of the resistance memory element 12 flows in the bit line BL1. Accordingly, the value of the current flowing in the bit line BL1 is detected, whereby it can be read what resistance state the resistance memory element 12 has.
As described above, according to the present embodiment, when the resistance memory element is switched from the high resistance state to the low resistance state, the resistor is serially connected to the resistance memory element to thereby prevent the flow of large current to the resistance memory element, whereby the breakage and degradation of the resistance memory element due to the flow of the large current can be prevented. By the resistance value of the resistor, the resistance value of the resistance memory element in the low resistance state can be controlled. Thus, the multiple-valued memory can be easily realized.
The nonvolatile semiconductor memory device and method of writing into the same according to a third embodiment of the present invention will be explained with reference to
First, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to
The memory cell 10 of the nonvolatile semiconductor memory device according to the present embodiment includes, as shown in
The resistance memory element 12 has a resistance memory material sandwiched between a pair of electrodes. The resistance memory material may be a unipolar resistance memory material or a unipolar resistance memory material. In the present embodiment, the resistance memory material is, e.g., a unipolar resistance material of, e.g., TiOx.
In the column direction, a plurality of word lines WL1, /WL1, WL2, /WL2 . . . , control lines CL1, /CL1, CL2, /CL2 . . . , and source lines SL1, SL2 . . . are arranged, forming signal lines common among the memory cells 10 arranged in the column direction. The source lines SL are provided each for two word lines WL.
In the row direction (horizontally in the drawing), a plurality of bit lines BL1, BL2, BL3, BL4 . . . are arranged, forming signal lines common among the memory cells 10 arranged row direction.
Next, the method of writing into the nonvolatile semiconductor memory device according to the present embodiment shown in
First, the operation of rewriting from the high resistance state to the low resistance state, i.e., the setting operation will be explained with reference to
First, a prescribed voltage is applied to the control line CL1 to turn on the current control transistor 16 (refer to
Simultaneously with turning on the current control transistor 18, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14 (refer to
The source line SL1 is connected to a reference potential, e.g., 0 V, which is the ground potential (refer to
Next, to the bit line BL1, a bias voltage which is the same as the voltage necessary to set the resistance memory element 12 or a little larger than the voltage is applied (refer to
At this time, the resistance value RH of the resistance memory element 12 is sufficiently large in comparison with the channel resistance RCL of the current control transistor 18 and the channel resistance RCS of the cell select transistor, and most the bias voltage is applied to the resistance memory element 12. Thus, the resistance memory element 12 changes from the high resistance state to the low resistance state.
When the resistance value of the resistance memory element 12 changed from the resistance value RH to the resistance value RL, the channel resistance RCL of the current control transistor 18 becomes unignorably large in comparison with the resistance value RL, and the ratio of the voltages divided to the resistance memory element 12 and the current control transistor 18 becomes RL: RCL-Accordingly, the voltage of the control line CL1 is set so that the channel resistance RCL of the current control transistor 16 becomes, e.g., RCL=2×RL, whereby ⅓ of the bias voltage is divided to the resistance memory element 12.
The channel resistance RCL of the current control transistor 18 can be set at an arbitrary value as far as the performance of the current control transistor 18 permits, and the voltage to be applied to the resistance memory element 12, i.e., the current to flow in the resistance memory element 12 can be set at an arbitrary value by the gate voltage of the current control transistor 18, i.e., the applied voltage to the control line CL1.
That is, by the voltage of the control line CL1, the current to flow in the resistance memory element 12 can be limited to a prescribed value, and by this current limitation, the resistance value of the resistance memory element 12 can controlled. For example, as shown in
Next, after the bias voltage to be applied to the bit line BL1 has been returned to zero, the voltages to be applied to the control lines CL1 and the word line WL1 are turned off, and the setting operation is completed (refer to
Then, the rewriting operation from the low resistance state to the high resistance state, i.e., the resetting operation will be explained with reference to
First, a prescribed voltage is applied to the control line CL1 to turn on the current control transistor 18 (refer to
Simultaneously with turning on the current control transistor 18, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14 (refer to
The source line SL1 is connected to a reference potential, e.g., 0 V, which is the ground potential (refer to
Next, to the bit line BL1, a bias voltage which is the same as or a little larger than the voltage necessary to reset the resistance memory element 12 is applied (refer to
At this time, the channel resistance RCL of the current control transistor 18 and the channel resistance RCS of the cell select transistor 14 are sufficiently smaller than the resistance value RL of the resistance memory element 12, and most of the applied bias voltage is applied to the resistance memory element 12. Thus, the resistance memory element 12 changes from the low resistance state to the high resistance state.
In resetting process, instantaneously with the resistance memory element 12 having changed to the high resistance state, almost all of the bias voltage is divided to the resistance memory element 12, and accordingly it is necessary to prevent the resistance memory element 12 from being set again by this bias voltage. To this end, the bias voltage to be applied to the bit line BL must be smaller than the voltage necessary for the setting.
In short, to make the resetting process, the gate voltages of these transistors are adjusted so that the channel resistance RCL of the current control transistor 18 and the channel resistance RCS of the cell select transistor 14 are sufficiently smaller than the resistance value RL of the resistance memory element 12 while the bias voltage to be applied to the bit line BL is set to be not less than the voltage necessary for the resetting and less than the voltage necessary for the setting.
Then, after the bias voltage to be applied to the bit line BL1 has been returned to zero, the voltage to be applied to the control line CL1 and the voltage to be applied to the word line WL1 are turned off, and the resetting operation is completed (refer to
In the nonvolatile semiconductor memory device according to the present embodiment, as shown in
Next, the method of reading the nonvolatile semiconductor memory device according to the present embodiment shown in
First, a prescribed voltage is applied to the control line CL1 to turn on the current control transistor 18 (refer to
Simultaneously with turning on the current control transistor 18, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14 (refer to
The source line SL1 is connected to a reference potential, e.g., 0 V, which is the ground potential (refer to
Next, a prescribed bias voltage is applied to the bit line BL1 (refer to
For example, when the resistance memory element 12 has the current-voltage characteristics shown in
When such bias voltage is applied to the bit line BL1, current corresponding to the resistance value of the resistance memory element 12 flows in the bit line BL. Accordingly, the value of the current flowing in the bit line BL1 is detected, whereby it can be read what resistance state the resistance memory element 12 has.
As described above, according to the present embodiment, when the resistance memory element is switched from the high resistance state to the low resistance state, the resistor is serially connected to the resistance memory element to thereby prevent the flow of large current to the resistance memory element, whereby the breakage and degradation of the resistance memory element due to the flow of the large current can be prevented. By the resistance value of the resistor, the resistance value of the resistance memory element in the low resistance state can be controlled. Thus, the multiple-valued memory can be easily realized.
The nonvolatile semiconductor memory device and the method of writing into the same according to a fourth embodiment of the present invention will be explained. The same members of the present embodiment as those of the nonvolatile semiconductor memory device, the method of writing into the same and the method of reading the same according to the third embodiment shown in
The nonvolatile semiconductor memory device according to the present embodiment is the same as the nonvolatile semiconductor memory device according to the third embodiment shown in
Next, the method writing into the nonvolatile semiconductor memory device according to the present embodiment will be explained. The method of writing into the nonvolatile semiconductor memory device according to the present embodiment is the same as the method of writing into the nonvolatile semiconductor memory device according to the third embodiment except the polarity of the bias voltage.
First, the operation of rewriting from the high resistance state to the low resistance state, i.e., the setting operation will be explained. The memory cell 10 to be rewritten is a memory cell 10 connected to the word line WL1 and to the bit line BL1.
First, a prescribed voltage is applied to the control line CL1 to turn on the current control transistor 18. At this time, the voltage to be applied to the control line CL1 is controlled so that the channel resistance RCL of the current control transistor 18 is sufficiently smaller than the resistance value RH of the resistance memory element 12 in the high resistance state and has a value which is cannot be ignored in comparison with the resistance value RL of the resistance memory element 12 in the low resistance state.
Simultaneously with turning on the current control transistor 18, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14. At this time, the voltage to be applied to the word line WL1 is controlled so that the channel resistance RCS of the cell select transistor 14 has a value which is ignorably small in comparison with the resistance value RL of the resistance memory element 12 in the low resistance state.
The source line SL1 is connected to a reference potential, e.g., 0 V, which is the ground potential.
Then, to the bit line BL1, a negative bias voltage which is the same as the voltage necessary to setting the resistance memory element 12 or has an absolute value a little larger than the voltage is applied. Thus, a current passage from the source line SL1 via the cell select transistor 14, the resistance memory element 12, the current control transistor 18 and the bit line BL1 is formed. The applied voltage is divided to the resistance memory element 12, the current control transistor 18 and the cell select transistor 14, corresponding to the resistance value RH of the resistance memory element 12, the channel resistance RCL of the current control transistor 18 and the channel resistance RCS of the cell select transistor 14.
At this time, the resistance value RH of the resistance memory element 12 is sufficiently large in comparison with the channel resistance RCL of the current control transistor 18 and the channel resistance RCS of the cell select transistor 14, and most of the bias voltage is applied to the resistance memory element 12. Thus, the resistance memory element 12 changes from the high resistance state to the low resistance state.
When the resistance value of the resistance memory element 12 changes from the resistance value RH to the resistance value RL, the channel resistance RCL of the current control transistor 18 becomes unignorably large in comparison with the resistance value RL, and the ratio of the voltages divided to the resistance memory element 12 and the current control transistor 18 becomes RL: RCL. Accordingly, the voltage of the control line CL1 is set so that the channel resistance RCL of the current control transistor 18 becomes, e.g., RCL=2×RL, whereby ⅓ of the bias voltage is divided to the resistance memory element 12.
The channel resistance RCL of the current control transistor 18 can be set at an arbitrary value as far as the performance of the current control transistor 18 permits, and the voltage to be applied to the resistance memory element 12, i.e., current to flow in the resistance memory element 12 can be set at an arbitrary value by the gate voltage of the current control transistor 18, i.e., the applied voltage to the control line CL1. In short, by the voltage of the control line CL1, the current to flow in the resistance memory element 12 can be limited to a prescribed value. By this current limitation, the resistance value of the resistance memory element 12 can be controlled.
Then, after the bias voltage to be applied to the bit line BL1 has been returned to zero, the voltage to be applied to the control line CL1 and voltage to be applied to the word line WL1 are turned off, and the setting operation is completed.
Then, the rewriting operation from the low resistance state to the high resistance state, i.e., the resetting operation will be explained. The memory cell 10 to be rewritten is a memory cell 10 connected to the word line WL1 and the bit line BL1.
First, a prescribed voltage is applied to the control line CL1 to turn on the current control transistor 18. At this time, the voltage to be applied to the control line CL1 is controlled so that the channel resistance RCL of the current control transistor 18 becomes sufficiently smaller than the resistance value RL of the resistance memory element 12 in the low resistance state.
Simultaneously with turning on the current control transistor 18, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14. At this time, the voltage to be applied to the word line WL1 is controlled so that the channel resistance RCS of the cell select transistor 14 becomes sufficiently smaller than the resistance value RL of the resistance memory element 12 in the low resistance state.
The source line SL1 is connected to a reference potential, e.g., 0 V, which is the ground potential.
Then, to the bit line BL1, a positive bias voltage which is the same as or has an absolute value larger than the voltage necessary to reset the resistance memory element 12 is applied. Thus, a current passage from the source line SL1 via the cell select transistor 14, the resistance memory element 12, the current control transistor 18 and the bit line BL1 is formed, and the applied bias voltage is divided to the resistance memory element 12, the current control transistor 18 and the cell select transistor 14, corresponding to the resistance value RL of the resistance memory element 12, the channel resistance RCL of the current control transistor 18 and the channel resistance RCS of the cell select transistor 14.
At this time, the channel resistance RCL of the current control transistor 18 and channel resistance RCS of the cell select transistor 14 are sufficiently smaller than the resistance value RL of the resistance memory element 12, which permits almost all the applied bias voltage is applied to the resistance memory element 12. Thus, the resistance memory element 12 changes from the low resistance state to the high resistance state.
Next, after the bias voltage to be applied to the bit line BL1 has been returned to zero, the voltage to be applied to the control line CL1 and the voltage to be applied to the word line WL1 are turned off, and the setting operation is completed.
In the nonvolatile semiconductor memory device according to the present embodiment, as shown in
Next, the method of reading the nonvolatile semiconductor memory device according to the present embodiment will be explained. The memory cell 10 to be read is a memory cell 10 connected to the word line WL1 and the bit line BL1.
First, a prescribed voltage is applied to the control line CL1 to turn on the current control transistor 18. At this time, the voltage to be applied to the control line CL1 is controlled so that the channel resistance RCL of the current control transistor 18 is sufficiently smaller than the resistance value RL of the resistance memory element 12.
Simultaneously with turning on the current control transistor 18, a prescribed voltage is applied to the word line WL1 to turn on the cell select transistor 14. At this time, the voltage to be applied to the word line WL is controlled so that the channel resistance RCS of the cell select transistor 14 becomes sufficiently smaller than the resistance value RL of the resistance memory element 12 in the low resistance state.
The source line SL1 is connected to a reference potential, e.g., 0 V, which is the ground potential.
Next, to the bit line BL, a prescribed bias voltage is applied. This bias voltage is set in accordance with the memory characteristics given by the lowest current limitation value. That is, the value of the bias voltage is set so that even with the resistance memory element 12 in any resistance state, neither the setting nor the resetting is caused by the applied voltage.
When such the bias voltage is applied to the bit line BL1, current corresponding to the resistance value of the resistance memory element 12 flows in the bit line BL1. Accordingly, the value of the current flowing in the bit line BL1 is detected, whereby it can be read what resistance state the resistance memory element 12 has.
As described above, according to the present embodiment, when the resistance memory element is switched from the high resistance state to the low resistance state, the resistor is serially connected to the resistance memory element to thereby prevent the flow of large current to the resistance memory element, whereby the breakage and degradation of the resistance memory element due to the flow of the large current can be prevented. By the resistance value of the resistor, the resistance value of the resistance memory element in the low resistance state can be controlled. Thus, the multiple-valued memory can be easily realized.
The nonvolatile semiconductor memory device and the method of writing into the same according to a fifth embodiment of the present invention will be explained with reference to
In the first and the second embodiments, the channel resistance RBS of the bit line select transistor 16 is controlled to thereby control the current to flow in the bit line BL, but the method for controlling the current to flow in the bit line BL is not limited to this. For example, the variable resistance circuit shown in
The circuit shown in
By using the circuit shown in
In the resetting and the reading, the resistor having a sufficiently smaller resistance value than the resistance value RL of the resistance memory element in the low resistance state (e.g., rn) may be connected, which also makes the control easy in comparison with controlling the channel resistance RBS of the bit line select transistor 16.
Two or more of the select transistors Tr may be turned on at once. For example, in the circuit including the resistor r1 and the resistor r2, the resistance value with the select transistor Tr1 turned on is r1, and the resistance value with the select transistor Tr2 turned on is r2. The resistance value with the select transistors Tr1, Tr2 simultaneously turned on is r1r2/(r1+r2). Accordingly, by suitably combining the select transistors Tr to be turned on, more resistance states can be realized, which allows the circuit structure to be simplified.
As described above, according to the present embodiment, the resistance value of the resistor serially connected to the resistance memory elements can be easily controlled. Thus, a multiple-valued memory can be realized.
The nonvolatile semiconductor memory device and the method of manufacturing the same according to a sixth embodiment of the present invention will be explained with reference to
In the present embodiment, the specific structure of the nonvolatile semiconductor memory device and the method of manufacturing the same according to the third embodiment described above will be explained.
First, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to
In a silicon substrate 10, a device isolation film 22 for defining device regions is formed. In the device regions of the silicon substrate 20, cell select transistors each including a gate electrode 24 and source/drain regions 26, 28 and current control transistors each including a gate electrode 30 and source/drain regions 32, 34 are formed.
As shown in
Over the silicon substrate 10 with the cell select transistors and the current control transistors formed on, an inter-layer insulating film 36 with contact plugs 38 electrically connected to the source/drain regions 26, contact plugs 40 electrically connected to the source/drain regions 28, contact plugs 42 electrically connected to the source/drain regions 32 and contact plugs 44 electrically connected to the source/drain regions 34 buried in is formed.
Over the inter-layer insulating film 36 with the contact plugs 38, 40, 42, 44 buried in, the source lines 46 electrically connected to the source/drain regions 28 via the contact plugs 38, and resistance memory elements 54 electrically connected to the source/drain regions 30 via the contact plugs 40 are formed.
Over the inter-layer insulating film 36 with the source lines 46 and the resistance memory elements 54 formed on, an inter-layer insulating film 56 with contact plugs 58 electrically connected to the resistance memory elements 54 and contact plugs 60 electrically connected to the contact plugs 42 buried in is formed.
Over the inter-layer insulating film 56 with the contact plugs 58, 60 buried in, an interconnection layer 62 connecting between the contact plugs 58, 60 is formed.
Over the inter-layer insulating film 56 with the interconnection layer 62 formed on, an inter-layer insulating film 64 is formed. Over the inter-layer insulating film 64, bit lines 68 electrically connected to the source drain regions 34 via the contact plugs 66 buried in the inter-layer insulating films 64, 56 and the contact plugs 44 are formed.
Thus, the nonvolatile semiconductor memory device according to the third embodiment shown in
Next, the method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to
First, in the silicon substrate 20, the device isolation film 22 for defining the device regions is formed by, e.g., STI (Shallow Trench Isolation) method.
Next, in the device regions of the silicon substrate 20, the cell select transistors each including the gate electrode 24 and the source/drain regions 26, 28 and the current control transistors each including the gate electrode 30 and the source/drain regions 32, 34 are formed in the same way as in the usual MOS transistor manufacturing method (
Next, over the silicon substrate 20 with the cell select transistors ad the current control transistors formed on, a silicon oxide film is deposited by, e.g., CVD method to form the inter-layer insulating film 36 of the silicon oxide film.
Next, by lithography and dry etching, the contact holes reaching down to the source/drain regions 26, 28, 32, 34 are formed in the inter-layer insulating film 36.
Next, by, e.g., CVD method, a barrier metal and a tungsten film are deposited, and then these conductive films are etched back to form the contact plugs 38, 40, 42, 44 electrically connected to the source/drain regions 26, 28, 32, 34 in the inter-layer insulating film 36 (
Next, over the inter-layer insulating film 36 with the contact plugs 38, 40, 42, 44 buried in, the source lines 46 electrically connected to the source/drain regions 26 via the contact plugs 38 and the resistance memory elements 54 electrically connected to the source/drain regions 28 via the contact plugs 40 are formed (
The resistance memory elements 54 each includes a lower electrode 40 connected to the contact plug 40, a resistance memory material layer 50 formed on the lower electrode 48 and an upper electrode 52 formed on the resistance memory material layer 50.
In the case that the resistance memory material layer 46 is formed of the bipolar resistance memory material, for example, Pr1-xCaxMnO3 (x≦1), La1-xCaxMnO3 (x≦1), SrTiO3 doped with Cr, Nb or others, SrZrO3 doped with Cr, Nb or others or others is formed by laser ablation, sol-gel method, sputtering method, MOCVD method or others. In the case that the resistance memory material layer 46 is formed of the unipolar resistance memory material, for example, a film of NiOy (y≦1), TiOz (z≦2), HfOz (z≦2) or others is formed by sol-gel method, sputtering method, MOCVD method or others.
Next, over the inter-layer insulating film 36 with the source lines 46 and the resistance memory elements 54 formed on, a silicon oxide film is deposited by, e.g., CVD method to form the inter-layer insulating film 56 of the silicon oxide film.
Next, by lithography and dry etching, in the inter-layer insulating film 56, contact holes reaching down to the upper electrodes 52 of the resistance memory elements 54 and contact holes reaching down to the contact plugs 42 are formed.
Next, a barrier metal and a tungsten film are deposited by, e.g., CVD method, and then these conductive films are etched back to form the contact plugs 58 electrically connected to the upper electrodes 52 of the resistance memory elements 54 and the contact plugs 60 electrically connected to the contact plugs 42 in the inter-layer insulating film 56 (
Then, over the inter-layer insulating film 56 with the contact plugs 58, 60 buried in, a conductive film is deposited, and then the conductive film is patterned by photolithography and dry etching to form the interconnection layer 62 electrically connected to the contact plugs 58 and the contact plugs 60 (
Next, over the inter-layer insulating film with the interconnection layer 62 formed on, a silicon oxide film is deposited by, e.g., CVD method to form the inter-layer insulating film 64 of the silicon oxide film.
Next, by lithography and dry etching, contact holes reaching down to the contact plugs 44 are formed in the inter-layer insulating films 64, 56.
Then, by, e.g., CVD method, a barrier metal and a tungsten film are deposited, and then these conductive films are etched back to form the contact plugs 66 electrically connected to the contact plugs 44 in the inter-layer insulating films 64, 56.
Then, over the inter-layer insulating film 64 with the contact plugs 66 buried in, a conductive film is deposited, and then the conductive film is patterned by photolithography and dry etching to form the bit lines 68 electrically connected to the source/drain regions 34 via the contact plugs 66, 44 (
Then, upper level interconnection layers are further formed as required, and the nonvolatile semiconductor memory device is completed.
The present invention is not limited to the above-described embodiments and can cover other various modifications.
For example, in the above-described embodiments, TiOx is used as the unipolar resistance memory material, and as the bipolar resistance memory material, Cr-doped SrZrO3 is used. However, the material forming the resistance memory element is not limited to them. For example, as the unipolar resistance memory material, NiOx, etc. can be used, and as the bipolar resistance memory material, Pr1-xCaxMnO3 or La1-xCaxMnO3 exhibiting CMR (Colossal Magneto-Resistance), etc. can be used. It is preferable that the applied voltage and the current limitation value for the setting and the resetting are set suitably depending on kinds of the resistance memory material, structures of the resistance memory elements, etc.
In the above-described embodiments, the source lines SL are arranged in parallel with the word lines WL but may be arranged in parallel with the bit lines BL. For example, in the nonvolatile semiconductor memory device according to the first and the second embodiments, as shown in
In the above-described embodiments, one memory cell comprises one cell select transistor and one resistance memory element but may not have essentially this constitution. For example, one memory cell may comprise one cell select transistor and two resistance memory elements or two cell select transistors and two resistance memory elements. These constitutions will improve the read margin and other advantageous effects.
The foregoing is considered as illustrative only of the principles of the present invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and applications shown and described, and accordingly, all suitable modifications and equivalents may be regarded as falling within the scope of the invention in the appended claims and their equivalents.
This application is a Continuation of International Application No. PCT/JP2005/011249, with an international filing date of Jun. 20, 2005, which designating the United States of America, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2005/011249 | Jun 2005 | US |
| Child | 11959781 | US |
