Nonvolatile semiconductor memory device

Abstract

Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an electrically equivalent circuit of a memory cell in a nonvolatile semiconductor memory device according to the invention.

FIGS. 2A and 2B show planar layouts of the memory cell in respective interconnection layers shown in FIG. 1, and FIG. 2C schematically shows a sectional structure of the memory cell shown in FIG. 1;

FIGS. 3A and 3B show planar layouts including the memory cell and a source line arranged in the column direction, and FIG. 3C schematically shows a sectional structure including the memory cell and the source line arranged in the column direction.

FIG. 4 schematically shows a construction of a major portion of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

FIG. 5 is a signal waveform diagram representing an operation of the nonvolatile semiconductor memory device shown in FIG. 4.

FIG. 6 schematically shows a whole construction of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

FIG. 7 schematically shows paths of a leak current in a data write operation of the nonvolatile semiconductor memory device of the first embodiment of the invention.

FIG. 8 shows an example of a construction of a portion for generating voltages Vp and Vcs shown in FIG. 6.

FIG. 9 schematically shows another construction for generating voltages Vp and Vcs shown in FIG. 7.

FIG. 10 shows an example of a construction of a portion for generating a source line drive timing signal shown in FIG. 4.

FIG. 11 is a signal waveform diagram representing an operation of the source line drive timing signal generating portion shown in FIG. 10.

FIG. 12 shows more specifically a construction of an array of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

FIG. 13 is a timing diagram representing the operation of the nonvolatile semiconductor memory device shown in FIG. 12.

FIG. 14 shows constructions of a connection path selector switch and a sense amplifier shown in FIG. 12.

FIG. 15 shows more specifically a construction of the sense amplifier shown in FIG. 14.

FIG. 16 schematically shows a construction of a reference current generating portion in the connection path selector switch and the sense amplifier shown in FIG. 14.

FIG. 17 is a timing diagram representing external and internal signals of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

FIG. 18 is a signal waveform diagram representing external and internal signals in a data read operation of the nonvolatile semiconductor memory device in the first embodiment of the invention.

FIG. 19 shows a construction of the nonvolatile semiconductor memory device according to a modification of the first embodiment of the invention.

FIG. 20 shows a construction of a nonvolatile semiconductor memory device according to a second embodiment of the invention.

FIG. 21 is a timing chart representing operations for data writing of the nonvolatile semiconductor memory device shown in FIG. 20.

FIG. 22 schematically shows an example of a construction for generating control signals shown in FIG. 20.

FIG. 23 is a timing chart representing an operation of a control signal generating portion (precharge circuit) shown in FIG. 22.

FIG. 24 schematically shows a construction of an array of a nonvolatile semiconductor memory device according to a third embodiment of the invention.

FIG. 25 schematically shows a layout of memory cells according to a fourth embodiment of the invention.

FIG. 26 schematically shows a sectional structure taken along line L26-L26 in FIG. 25.

FIG. 27 shows an electrically equivalent circuit of a memory cell arrangement shown in FIGS. 25 and 26.

FIG. 28 schematically shows a planar layout of memory cells of a first modification of the fourth embodiment of the invention.

FIG. 29 schematically shows a sectional structure taken along line L29-L29 in FIG. 28.

FIG. 30 shows an electrically equivalent circuit of a structure of memory cells shown in FIGS. 28 and 29.

FIG. 31 shows an example of a construction of a portion for generating a source line drive timing signal shown in FIG. 30.

FIG. 32 shows an operation manner of the source line drive timing signal generating portion shown in FIG. 31.

FIG. 33 schematically shows a layout of the memory cells according to a second modification of the fourth embodiment of the invention.

FIG. 34 schematically shows a sectional structure taken along line L34-L34 in FIG. 33.

FIG. 35 shows an electrically equivalent circuit of a memory cell structure shown in FIGS. 33 and 34.

FIG. 36 schematically shows a planar layout of memory cells according to a third modification of the fourth embodiment of the invention.

FIG. 37 shows an electrically equivalent circuit of the memory cell layout shown in FIG. 36.

Claims

1. A nonvolatile semiconductor memory device comprising: a plurality of memory cells, arranged in rows and columns, each having a storing portion having a resistance value set according to storage data;a plurality of bit lines, arranged corresponding to the respective memory cell columns, each connected to the memory cells in a corresponding column;a plurality of source lines, arranged corresponding to the memory cell rows, each connected to the memory cells in a corresponding row;write circuitry for transmitting a voltage corresponding to write data to a bit line on a selected column in data writing; andsource line drive circuitry for driving a source line on a selected row to first and second voltage levels in a predetermined sequence in said data writing, according to a current flowing between the bit line in said selected column and the source line in said selected row via a corresponding memory cell, the storing portion of the corresponding memory cell having the resistance value set.

2. The nonvolatile semiconductor memory device according to claim 1, wherein said write circuitry writes multiple bits of data in parallel;said nonvolatile semiconductor memory device further comprises:a column select circuit for selecting in parallel a plurality of columns equal in number to a bit width of the data to be written; andsaid source line drive circuitry drives the source line common to the memory cells on the plurality of selected columns in said predetermined sequence.

3. The nonvolatile semiconductor memory device according to claim 1, wherein said source line drive circuitry drives the source line in the selected row from opposite ends.

4. The nonvolatile semiconductor memory device according to claim 1, wherein the source line is arranged to be shared by the memory cells in adjacent columns.

5. The nonvolatile semiconductor memory device according to claim 1, wherein each of the memory cells further includes an access transistor for coupling, when made conductive, a corresponding storing portion to a corresponding source line;said nonvolatile semiconductor memory device further comprises:a plurality of word lines, arranged corresponding to the memory cell rows, each connected to the access transistors of the memory cells in a corresponding row, anda word line select drive circuit for driving a word line in the selected row to the selected state; andsaid word line select drive circuit is arranged in a region opposing in a row direction to the source line drive circuitry.

6. The nonvolatile semiconductor memory device according to claim 1, wherein. each of the memory cells further includes first and second access transistors each for connecting a corresponding storing portion to a corresponding source line; andsaid nonvolatile semiconductor memory device further comprises:a plurality of first gate lines, arranged corresponding to the memory cell rows, each connected to the first access transistors of the memory cells in a corresponding row,a plurality of second gate lines, arranged corresponding to the memory cell rows, each connected to the second access transistors of the memory cells in a corresponding row, anda word line select drive circuit for driving both the first and second gate lines in said selected row to a selected state, each word line being constituted by the first gate line and the second gate line arranged on a corresponding row.

7. The nonvolatile semiconductor memory device according to claim 6, wherein a set of the first gate line and the second gate line and the source line are arranged alternately in a column direction, andsaid source line drive circuitry drives concurrently the source lines adjacent, respectively, to the first and second gate lines arranged on the selected row.

8. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cells are arranged such that the storing portions arranged in a row direction are greater in number than the storing portions arranged in a column direction.

9. The nonvolatile semiconductor memory device according to claim 1, wherein each memory cell further includes an access transistor for coupling, when made conductive, a corresponding storing portion to a corresponding source line; andsaid nonvolatile semiconductor memory device further comprises:a plurality of word lines, arranged corresponding to the memory cell rows, each being connected to the access transistors of the memory cells in a corresponding row, anda word line drive circuit for driving a word line in the selected row to a selected state at the voltage level higher than a high-level voltage that can be supplied by said source line select drive circuitry and said write circuitry.

10. The nonvolatile semiconductor memory device according to claim 1, wherein said source line select drive circuitry maintains an unselected source line at a voltage level corresponding to a logical level of a low voltage.

11. The nonvolatile semiconductor memory device according to claim 1, further comprising: a write data line for transferring the write data from said write circuitry;a plurality of column select gates, arranged corresponding to the respective bit lines, for coupling corresponding bit lines to the write data line, when made conductive; anda column select signal producing circuit for producing a column select signal turning on the column select gate corresponding to a selected column according to an address signal, said column select signal, when selected, being set to a voltage level higher than levels of voltages supplied to the source lines and the bit lines.

12. The nonvolatile semiconductor memory device according to claim 1, further comprising: a bit line voltage setting circuit for setting an unselected bit line to a voltage level corresponding to a voltage level of the selected source line on the selected row in a data write mode.

13. A nonvolatile semiconductor memory device comprising: a plurality of memory cells, arranged in rows and columns, each having a storing portion having a resistance value set according to storage data;a plurality of bit lines, arranged corresponding to the memory cell columns, each connected to the memory cells in a corresponding column;a plurality of source lines, arranged corresponding to the memory cell rows, each connected to the memory cells in a corresponding row;a column select circuit for concurrently selecting the columns equal in number to a bit width of multi-bit write data in data writing;a write circuit for transmitting a first voltage to each of the bit lines on the selected columns regardless of a value of the write data bit, and then transmitting concurrently voltages corresponding to the write data bits to the bit lines in the selected columns, respectively in said data writing; anda source line drive circuit for driving the source line in a selected row to a second voltage level and the first voltage level in a predetermined sequence in the data write operation, according to a current flowing between the bit line in the selected column and the source line in the selected row via a corresponding memory cell, the resistance value of said storing portion of the corresponding, selected memory cell being set, said source line drive circuit transmitting said second voltage concurrently with transmission of said first voltage by said write circuit, to set said storing portion of the selected memory cell to a resistance state corresponding to a predetermined logical level.

14. The nonvolatile semiconductor memory device according to claim 13, further comprising: a bit line voltage setting circuit for setting an unselected bit line on an unselected column to a voltage level corresponding to a voltage level of the selected source line when said source line drive circuit transmits said second voltage.

15. A nonvolatile semiconductor memory device comprising: a plurality of memory cells, arranged in rows and columns, each having a storing portion having a resistance value set according to storage data;a plurality of bit lines, arranged corresponding to the memory cell columns, each connected to the memory cells on a corresponding column;a plurality of source lines each arranged being shared by the memory cells in a plurality of columns;a source line drive circuit for changing a voltage level of the source line on a selected column in a predetermined sequence in data writing; anda data write circuit having at least a time period for driving the bit line on the selected column according to the write data in the data writing.

16. The nonvolatile semiconductor memory device according to claim 15, wherein the write data is comprised of multiple bits, andthe plurality of columns sharing the source line are equal in number to a bit width of said multi-bit data.

17. The nonvolatile semiconductor memory device according to claim 15, wherein each source line includes:a main line portion arranged extending in a column direction and corresponding to a predetermined plurality of columns, anda plurality of feeder line portions, arranged corresponding to the memory cell rows, each connected to the memory cells located on a corresponding row and said predetermined plurality of columns, as well as to said main line portion.

18. The nonvolatile semiconductor memory device according to claim 17, wherein each feeder line portion is arranged being shared by the memory cells in adjacent rows.

19. The nonvolatile semiconductor memory device according to claim 17, wherein each memory cell further includes first and second access transistors arranged in parallel with respect to said storing portion,each word line includes a first gate line connected to the first access transistor of the memory cell on a corresponding row, and a second gate line connected to a second access transistor of the memory cell in the corresponding row, andthe feeder line portion is arranged alternately to a set of the first gate line and the second gate line.