Claims
- 1. A multi-level flash memory device comprising:a plurality of flash memory cells each being able to store four level data of “0”, “1”, “2” and “3”; a plurality of data storage circuits, each being associated to corresponding one of said memory cells, for storing write data of “0”, “1”, “2” and “3” to be written into said memory cells; and a write controller for carrying out first write sequence in which “1”-data are simultaneously written into the memory cells corresponding to the data storage circuits storing “1”-write data, for carrying out second write sequence in which “2”-data and “3”-data are simultaneously written into the memory cells corresponding to the data storage circuits storing “2”-write data or “3”-write data, respectively; wherein, in said first write sequence, first write voltage promoting “1”-write is applied to the memory cells to be written, and it is determined that “1”-data has been written successfully, wherein, in said second write sequence, second write voltage promoting “2”-write or “3”-write is applied to the memory cells to be written, and it is determined that “2”-data has been written successfully in the memory cells corresponding to the data storage circuits storing “2”-write data and that “3”-data has been written successfully in the memory cells corresponding to the data storage circuits storing “3”-write data.
- 2. The multi-level flash memory device according to claim 1, wherein said first write sequence is carried out after said second write sequence is terminated.
- 3. The multi-level flash memory device according to claim 1, wherein the memory cell storing “0”-data has a erased state, the memory cell storing “1”-data has a first threshold voltage, the memory cell storing “2”-data has a second threshold voltage and the memory cell storing “3”-data has a third threshold voltage.
- 4. The multi-level flash memory device according to claim 3, wherein said first threshold voltage is smaller than both said second threshold voltage and said third threshold voltage.
- 5. The multi-level flash memory device according to claim 1, wherein each data storage circuit stores the write data in 2-bit register.
- 6. The multi-level flash memory device according to claim 5, wherein said 2-bit register is composed of two CMOS flip-flops.
Priority Claims (4)
Number |
Date |
Country |
Kind |
8-061352 |
Mar 1996 |
JP |
|
8-061443 |
Mar 1996 |
JP |
|
8-061444 |
Mar 1996 |
JP |
|
8-061449 |
Mar 1996 |
JP |
|
Parent Case Info
This application is a continuation of application Ser. No. 09/314,446 filed May 19, 1999, U.S. Pat. No. 6,044,013 which is a continuation application of Ser. No. 08/816,830 filed Mar. 18, 1997 U.S. Pat. No. 5,969,985.
US Referenced Citations (7)
Continuations (2)
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Number |
Date |
Country |
Parent |
09/314446 |
May 1999 |
US |
Child |
09/532329 |
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US |
Parent |
08/816830 |
Mar 1997 |
US |
Child |
09/314446 |
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US |