Claims
- 1. A nonvolatile memory cell formed on a substrate comprising:
a floating gate placed over a channel region of said memory cell and between a source region and a drain region of said memory cell, said floating gate aligned with an edge of said source region and an edge of said drain region and having a width defined by a width of said edge of said source and said edge of said drain.
- 2. The nonvolatile memory cell of claim 1 wherein said memory cell has a relatively small coupling ratio of capacitance formed by a control gate placed over said floating gate to a total capacitance of said floating gate and said control gate.
- 3. The nonvolatile memory cell of claim 1 wherein said coupling ratio is less than 50%.
- 4. The nonvolatile memory cell of claim 2 wherein said nonvolatile memory cell is programmed to place a charge upon said floating gate by the steps of:
applying a moderately high positive voltage to said control gate; applying an intermediate positive voltage to said drain region; and applying a ground reference voltage to said source region.
- 5. The nonvolatile memory cell of claim 4 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.
- 6. The nonvolatile memory cell of claim 4 wherein said intermediate positive voltage is approximately 5.0V
- 7. The nonvolatile memory cell of claim 4 wherein applying said moderately high positive voltage, said intermediate positive voltage, and applying said ground reference voltage has a duration of from approximately 1?s to approximately 100?s.
- 8. The nonvolatile memory cell of claim 2 wherein said memory cell is erased to remove electrical charge from said floating gate by the steps of:
applying a very large negative voltage to said control gate.
- 9. The nonvolatile memory cell of claim 8 wherein the very large negative voltage is from approximately −15V to approximately −22V.
- 10. The nonvolatile memory cell of claim 8 wherein erasing said memory cell further comprises the step of:
disconnecting the source region and the drain region to allow said source region and said drain region to float.
- 11. The nonvolatile memory cell of claim 8 wherein erasing said memory cell further comprises the step of:
applying a ground reference voltage to said source region and said drain region.
- 12. The nonvolatile memory cell of claim 8 wherein erasing said memory cell has a duration of from approximately 1 ms to approximately 1 s.
- 13. The nonvolatile memory cell of claim 2 further comprising a gating transistor having a source connected to the drain region, a drain, and a gate connected to a select gate signal to selectively apply a bit line voltage signal to the drain region.
- 14. The nonvolatile memory cell of claim 13 wherein said nonvolatile memory cell is programmed to place a charge upon said floating gate by the steps of:
applying a moderately high positive voltage to said control gate; applying an intermediate positive voltage to said drain region; applying a very large positive voltage to said gate of said gating transistor; and applying a ground reference voltage to said source region.
- 15. The nonvolatile memory cell of claim 14 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.
- 16. The nonvolatile memory cell of claim 14 wherein said intermediate positive voltage is approximately 5.0V
- 17. The nonvolatile memory cell of claim 14 wherein the very large positive voltage is from approximately +15V to approximately +22V.
- 18. The nonvolatile memory cell of claim 14 wherein applying said very large positive voltage, said moderately high positive voltage, said intermediate positive voltage, and applying said ground reference voltage has a duration of from approximately 1?s to approximately 100?s.
- 19. The nonvolatile memory cell of claim 13 wherein said memory cell is erased to remove electrical charge from said floating gate by the steps of:
applying a very high positive voltage to said control gate; and applying a ground reference voltage to said select gate.
- 20. The nonvolatile memory cell of claim 19 wherein erasing said memory cell further comprises the step of:
disconnecting the source region and the drain region to allow said source region and said drain region to float.
- 21. The nonvolatile memory cell of claim 19 wherein erasing said memory cell further comprises the step of:
applying a ground reference voltage to said source region and said drain region.
- 22. The nonvolatile memory cell of claim 19 wherein erasing said memory cell has a duration of from approximately 1 ms to approximately 1 s.
- 23. A nonvolatile memory array formed on a substrate comprising:
a plurality of nonvolatile memory cells arranged in rows and columns, each nonvolatile memory cell comprising:
a source region placed within a surface of said substrate, a drain region placed within the surface of said substrate at a distance from said source region, a tunneling insulation layer placed on said surface in a channel region between said source region and drain region, a floating gate placed over said tunneling insulation layer, said floating gate aligned with an edge of said source region and an edge of said drain region and having a width defined by a width of said edge of said source and said edge of said drain, and a control gate place over said floating gate and isolated from said floating gate by an insulating layer. a plurality of bit lines, each bit line in communication with the drain region of all nonvolatile memory cells of one column of nonvolatile memory cells; a plurality of source lines, each source line connected to the source region of all nonvolatile memory cells on one row of nonvolatile memory cells; and a plurality of word lines, each word line connected to the control gate of all nonvolatile memory cells one row of the nonvolatile memory cells.
- 24. The nonvolatile memory array of claim 23 wherein each memory cell has a relatively small coupling ratio of capacitance formed by said control gate to a total capacitance of said floating gate and said capacitance of said control gate.
- 25. The nonvolatile memory array of claim 23 wherein said coupling ratio is less than 50%.
- 26. The nonvolatile memory array of claim 24 wherein a selected nonvolatile memory cell is programmed to place a charge upon the floating gate of said selected nonvolatile memory cell by the steps of:
applying a moderately high positive voltage to the word line connected to the control gate of said selected nonvolatile memory cells; applying an intermediate positive voltage to the bit line in communication with the drain region of said selected nonvolatile memory cell such that the intermediate positive voltage is transferred to said drain region; and applying a ground reference voltage the source line connected to the source of the selected nonvolatile memory cell.
- 27. The nonvolatile memory array of claim 26 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.
- 28. The nonvolatile memory array of claim 26 wherein said intermediate positive voltage is approximately 6.0V such that approximately 5.0V is applied to the drain region.
- 29. The nonvolatile memory array of claim 26 wherein applying said moderately high positive voltage, said intermediate positive voltage, and applying said ground reference voltage has a duration of from approximately 1?s to approximately 100?s.
- 30. The nonvolatile memory array of claim 24 wherein a selected memory cell is erased to remove electrical charge from said floating gate by the steps of:
applying a very large negative voltage to the word line connected to said control gate of the selected memory cell.
- 31. The nonvolatile memory array of claim 30 wherein the very large negative voltage is from approximately −15V to approximately −22V.
- 32. The nonvolatile memory array of claim 30 wherein erasing said selected memory cell further comprises the step of:
disconnecting the source line connected to the source region of the selected memory cell and bit line in communication with the drain region of the selected nonvolatile memory cell to allow said source region and said drain region to float.
- 33. The nonvolatile memory array of claim 30 wherein erasing said memory cell further comprises the step of:
applying a ground reference voltage to the source line connected to the source region of the selected memory cell and bit line in communication with the drain region of the selected nonvolatile memory cell.
- 34. The nonvolatile memory array of claim 30 wherein erasing said memory cell has a duration of from approximately 1 ms to approximately 1 s.
- 35. The nonvolatile memory array of claim 24where in the nonvolatile memory cells further comprises a gating transistor having a source connected to the drain region, a drain connected to the bit line, and a gate connected to a select gate signal to selectively apply a bit line voltage signal to the drain region; and said nonvolatile memory array further comprises a plurality of select lines, each select line connected to the gate of the gating transistor of each nonvolatile memory cell of one row of nonvolatile memory cells.
- 36. The nonvolatile memory array of claim 35 wherein said nonvolatile memory cell is programmed to place a charge upon said floating gate by the steps of:
applying a moderately high positive voltage to the word line connected to the control gate of said selected nonvolatile memory cells; applying an intermediate positive voltage to the bit line in communication with the drain region of said selected nonvolatile memory cell such that the intermediate positive voltage is transferred to said drain region; applying a ground reference voltage the source line connected to the source of the selected nonvolatile memory cell; and applying a very large positive voltage to the select line connected to the gate of the gating transistor of the selected nonvolatile memory cell.
- 37. The nonvolatile memory array of claim 36 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.
- 38. The nonvolatile memory array of claim 36 wherein said intermediate positive voltage is approximately 6.0V such that approximately 5.0V is applied to the drain region.
- 39. The nonvolatile memory array of claim 36 wherein the very large positive voltage is from approximately +15V to approximately +22V.
- 40. The nonvolatile memory array of claim 36 wherein applying said very large positive voltage, said moderately high positive voltage, said intermediate positive voltage, and applying said ground reference voltage has a duration of from approximately 1?s to approximately 100?s.
- 41. The nonvolatile memory array of claim 35 wherein said memory cell is erased to remove electrical charge from said floating gate by the steps of:
applying a very high positive voltage to the word line connected to the control gate of the selected nonvolatile memory cell; and applying a ground reference voltage to said select line connected to the gate of the gating transistor of the selected nonvolatile memory cell.
- 42. The nonvolatile memory array of claim 41 wherein erasing said memory cell further comprises the step of:
disconnecting source line connected to the source region of the selected nonvolatile memory cell and bit line connected to the drain of the gating transistor of the selected nonvolatile memory cell.
- 43. The nonvolatile memory array of claim 41 wherein erasing said memory cell further comprises the step of:
applying a ground reference voltage source line connected to the source region of the selected nonvolatile memory cell and bit line connected to the drain of the gating transistor of the selected nonvolatile memory cell.
- 44. The nonvolatile memory array of claim 41 wherein erasing said memory cell has a duration of from approximately 1 ms to approximately 1 s.
- 45. A method for operating a nonvolatile memory array comprising the steps of:
forming said nonvolatile memory array on a substrate, said forming comprising the steps of:
arranging a plurality of nonvolatile memory cells in rows and columns, each nonvolatile memory cell comprising:
a source region placed within a surface of said substrate, a drain region placed within the surface of said substrate at a distance from said source region, a tunneling insulation layer placed on said surface in a channel region between said source region and drain region, a floating gate placed over said tunneling insulation layer, said floating gate aligned with an edge of said source region and an edge of said drain region and having a width defined by a width of said edge of said source and said edge of said drain, and a control gate place over said floating gate and isolated from said floating gate by an insulating layer. a plurality of bit lines, each bit line in communication with the drain region of all nonvolatile memory cells of one column of nonvolatile memory cells; a plurality of source lines, each source line connected to the source region of all nonvolatile memory cells on one row of nonvolatile memory cells; and a plurality of word lines, each word line connected to the control gate of all nonvolatile memory cells one row of the nonvolatile memory cells. programming a selected nonvolatile memory cell is to place a charge upon the floating gate of said selected nonvolatile memory cell by the steps of:
applying a moderately high positive voltage to the word line connected to the control gate of said selected nonvolatile memory cells; applying an intermediate positive voltage to the bit line in communication with the drain region of said selected nonvolatile memory cell such that the intermediate positive voltage is transferred to said drain region; and applying a ground reference voltage the source line connected to the source of the selected nonvolatile memory cell.
- 46. The method of claim 45 wherein each memory cell has a relatively small coupling ratio of capacitance formed by said control gate to a total capacitance of said floating gate and said capacitance of said control gate.
- 47. The method of claim 45 wherein said coupling ratio is less than 50%.
- 48. The method of claim 45 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.
- 49. The method of claim 45 wherein said intermediate positive voltage is approximately 6.0V such that approximately 5.0V is applied to the drain region.
- 50. The method of claim 45 wherein applying said moderately high positive voltage, said intermediate positive voltage, and applying said ground reference voltage has a duration of from approximately 1?s to approximately 100?s.
- 51. The method of claim 45 further comprising erasing a selected memory cell to remove electrical charge from said floating gate by the steps of:
applying a very large negative voltage to the word line connected to said control gate of the selected memory cell.
- 52. The method of claim 51 wherein the very large negative voltage is from approximately −15V to approximately −22V.
- 53. The method of claim 51 wherein erasing said selected memory cell further comprises the step of:
disconnecting the source line connected to the source region of the selected memory cell and bit line in communication with the drain region of the selected nonvolatile memory cell to allow said source region and said drain region to float.
- 54. The method of claim 51 wherein erasing said memory cell further comprises the step of:
applying a ground reference voltage to the source line connected to the source region of the selected memory cell and bit line in communication with the drain region of the selected nonvolatile memory cell.
- 55. The method of claim 51 wherein erasing said memory cell has a duration of from approximately 1 ms to approximately 1 s.
- 56. The method of claim 45where in the nonvolatile memory cells further comprises a gating transistor having a source connected to the drain region, a drain connected to the bit line, and a gate connected to a select gate signal to selectively apply a bit line voltage signal to the drain region; and said nonvolatile memory array further comprises a plurality of select lines, each select line connected to the gate of the gating transistor of each nonvolatile memory cell of one row of nonvolatile memory cells; and programming said selected nonvolatile memory cell further comprises the steps of:
applying a very large positive voltage to the select line connected to the gate of the gating transistor of the selected nonvolatile memory cell.
- 57. The method of claim 56 wherein the very large positive voltage is from approximately +15V to approximately +22V.
- 58. The method of claim 56 wherein applying said very large positive voltage, said moderately high positive voltage, said intermediate positive voltage, and applying said ground reference voltage has a duration of from approximately 1?s to approximately 100?s.
- 59. The method of claim 56 wherein erasing said selected nonvolatile memory cell further comprises the steps of:
applying a very high positive voltage to the word line connected to the control gate of the selected nonvolatile memory cell; and applying a ground reference voltage to said select line connected to the gate of the gating transistor of the selected nonvolatile memory cell.
- 60. The method of claim 59 wherein erasing said memory cell has a duration of from approximately 1 ms to approximately 1 s.
- 61. A method for forming a nonvolatile memory cell comprising steps of
forming a source region and drain region spatially separated within a surface of a substrate; forming a tunneling insulator upon said surface of said substrate in a channel region between the source region and the drain region; forming a floating gate placed over the channel region of said memory cell; aligning said floating gate with an edge of said source region and an edge of said drain region; setting a width of said floating gate to be a width of said edge of said source and said edge of said drain; and forming an insulating layer upon said floating gate; and forming a control gate upon said insulating layer above said floating gate.
- 62. The method for forming the nonvolatile memory cell of claim 61 further comprising the step of defining an area of said floating gate such that said nonvolatile memory cell has a relatively small coupling ratio of capacitance formed by a control gate placed over said floating gate to a total capacitance of said floating gate and said control gate.
- 63. The method for forming the nonvolatile memory cell of claim 61 wherein said coupling ratio is less than 50%.
- 64. The method for forming a nonvolatile memory cell of claim 61 further comprising the steps of:
connecting said control gate to a word line; placing said drain region in communication with a bit line; and connecting said source region to a source line.
- 65. The method for forming the nonvolatile memory cell of claim 62 wherein said method for forming the nonvolatile memory cell is programmed to place a charge upon said floating gate by the steps of:
applying a moderately high positive voltage to said control gate through said word line; applying an intermediate positive voltage to said drain region through said bit line; and applying a ground reference voltage to said source region through said source line.
- 66. The method for forming the nonvolatile memory cell of claim 65 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.
- 67. The method for forming the nonvolatile memory cell of claim 65 wherein said intermediate positive voltage is approximately 6.0V such that approximately 5.0V is applied to the drain region.
- 68. The method for forming the nonvolatile memory cell of claim 65 wherein applying said moderately high positive voltage, said intermediate positive voltage, and applying said ground reference voltage has a duration of from approximately 1?s to approximately 100?s.
- 69. The method for forming the nonvolatile memory cell of claim 64 wherein said memory cell is erased to remove electrical charge from said floating gate by the steps of:
applying a very large negative voltage to said control gate through said word line.
- 70. The method for forming the nonvolatile memory cell of claim 69 wherein the very large negative voltage is from approximately −15V to approximately −22V.
- 71. The method for forming the nonvolatile memory cell of claim 9 wherein erasing said memory cell further comprises the step of:
disconnecting the source line and said bit line to allow said source region and said drain region to float.
- 72. The method for forming the nonvolatile memory cell of claim 59 wherein erasing said memory cell further comprises the step of:
applying a ground reference voltage to said source region through said source line and said drain region through said bit line.
- 73. The method for forming the nonvolatile memory cell of claim 68 wherein erasing said memory cell has a duration of from approximately 1 ms to approximately 1 s.
- 74. The method for forming the nonvolatile memory cell of claim 64 further comprising the step of forming a gating transistor by the steps of:
forming a source; connecting said source to the drain region, forming a drain, connecting said drain to the bit line; forming a gate; connecting said gate to a select line to selectively apply a bit line voltage signal to the drain region.
- 75. The method for forming the nonvolatile memory cell of claim 74 wherein said method for forming the nonvolatile memory cell is programmed to place a charge upon said floating gate by the steps of:
applying a moderately high positive voltage to said control gate said word line; applying an intermediate positive voltage to said drain region through said gating transistor from said bit line; applying a very large positive voltage to said gate of said gating transistor through said gate line; and applying a ground reference voltage to said source region said source line.
- 76. The method for forming the nonvolatile memory cell of claim 74 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.
- 77. The method for forming the nonvolatile memory cell of claim 74 wherein said intermediate positive voltage is approximately 6.0V such that approximately 5.0V is applied to the drain region.
- 78. The method for forming the nonvolatile memory cell of claim 74 wherein the very large positive voltage is from approximately +15V to approximately +22V.
- 79. The method for forming the nonvolatile memory cell of claim 74 wherein applying said very large positive voltage, said moderately high positive voltage, said intermediate positive voltage, and applying said ground reference voltage has a duration of from approximately 1?s to approximately 100?s.
- 80. The method for forming the nonvolatile memory cell of claim 73 wherein said memory cell is erased to remove electrical charge from said floating gate by the steps of:
applying a very high positive voltage to said control gate through said word line; and applying a ground reference voltage to said select gate said select line.
- 81. The method for forming the nonvolatile memory cell of claim 80 wherein erasing said memory cell further comprises the step of:
disconnecting the source line and said bit line to allow said source region and said drain region to float.
- 82. The method for forming the nonvolatile memory cell of claim 80 wherein erasing said memory cell further comprises the step of:
applying a ground reference voltage to said source region through said source line and said drain region through said gating transistor from said bit line.
- 83. The method for forming the nonvolatile memory cell of claim 80 wherein erasing said memory cell has a duration of from approximately 1 ms to approximately 1 s.
RELATED PATENT APPLICATIONS
[0001] The present application is related to and claims benefit of priority of the filing date of U.S. Provisional Patent Application serial No. 60/394,202 filed on Jul. 5, 2002 and entitled “A Novel Monolithic Nonvolatile Memory Allowing Byte, Page and Block Write With No Disturb and Divided-Well in The Cell Array Using A Unified Cell Structure and Technology With A New Scheme of Decoder”, which is herein incorporated by reference.
[0002] The present application is further related to and claims benefit of priority of the filing date of U.S. Provisional Patent Application serial No. 60/426,614 filed on Nov. 14, 2002, entitled “A Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page And Block Write With No Disturb And Divided-Well In The Cell Array Using A Unified Cell Structure And Technology With A New Scheme Of Decoder And Layout”, which is herein incorporated by reference.
[0003] The present application is further related to and claims benefit of priority of the filing date of U.S. Provisional Patent Application serial No. 60/429,261 filed on Nov. 25, 2002, entitled “A Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page And Block Write With No Disturb And Divided-Well In The Cell Array Using A Unified Cell Structure And Technology With A New Scheme Of Decoder And Layout”, which is herein incorporated by reference.
[0004] U.S. patent application Ser. No. 09/852,247 to F. C. Hsu et al filed on May 9, 2001 and assigned to the same assignee as the present invention.
[0005] U.S. patent application Ser. No. 09/891,782 to F. C. Hsu et al filed on Jun. 27, 2001 and assigned to the same assignee as the present invention.
Provisional Applications (3)
|
Number |
Date |
Country |
|
60394202 |
Jul 2002 |
US |
|
60426614 |
Nov 2002 |
US |
|
60429261 |
Nov 2002 |
US |