Patent Application
20240332165
The present disclosure generally relates to fabrication methods and structures for semiconductor devices, and more specifically, to the formation of vias that are offset from underlying lines to allow for flexible routing in the back-end-of-the-line (BEOL) structure of an integrated circuit (IC).
An integrated circuit (IC) may be formed with millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate (wafer). For the IC to be functional, multi-level or multi-layered interconnection schemes such as, for example, metal wiring formed by single damascene processes, dual damascene processes, subtractive patterning (i.e., subtractive etch processes), and combinations thereof, are fabricated in the back-end-of-the-line (BEOL) of the device to connect the circuit elements distributed in the front-end-of-the-line (FEOL) of the device. Connections between interconnect levels, called vias, allow signals and power to be transmitted between one level to the next.
According to one embodiment of the present invention, a semiconductor interconnect structure is provided. The semiconductor interconnect structure includes a plurality of metal lines of a first metal level. The semiconductor interconnect structure further includes a via formed substantially offset from a centerline of a first metal line and at least partially through a first portion of the first metal line located beneath the via.
According to another embodiment of the present invention, a semiconductor interconnect structure is provided. The semiconductor interconnect structure includes a plurality of metal lines of a first metal level. The semiconductor interconnect structure further includes a first via formed substantially over a centerline of a first metal line of the plurality of metal lines located beneath the first via. The semiconductor interconnect structure further includes a second via formed substantially offset from a centerline of a second metal line of the plurality of metal lines located beneath the second via.
According to another embodiment of the present invention, a semiconductor interconnect structure is provided. The semiconductor interconnect structure includes a plurality of metal lines of a first metal level. The semiconductor interconnect structure further includes a first via formed substantially offset from a centerline of a first metal line of the plurality of metal lines located beneath the first via. The semiconductor interconnect structure further includes a second via formed substantially offset from a centerline of a second metal line of the plurality of metal lines located beneath the second via.
In conventional back-end-of-the-line (BEOL) metal wiring schemes, vias are typically formed on top of and aligned with underlying metal lines in order to maximize overlap and thereby reduce contact resistance. Furthermore, vias formed on top of adjacent lower level metal lines are typically staggered to avoid tip-to-tip (T2T) failure between overlying upper level metal lines. However, embodiments of the present invention recognize that this particular via arrangement limits via routing possibilities and BEOL design flexibility as whole.
Embodiments of the present invention provide for improved via routing and BEOL design flexibility by increasing the T2T space between upper level metal lines connected to adjacent lower metal lines by vias that are at least partially aligned with one another along the line direction. According to an embodiment of the present invention, a first via opening is formed on top of a first lower level metal line and arranged such that a centerline of the first via opening is substantially aligned with a centerline of the first lower level metal line. A second via opening is formed such that it at least partially extends, in a vertical direction, through respective portions of a pair of adjacent lower level metal lines, in which one of the lines in the pair is also located adjacent to the first lower level metal line. The second via opening is further formed such that a centerline of the second via opening is located between, and substantially offset from respective centerlines of the pair of adjacent lower level metal lines. An inner spacer is formed within the second via opening. A first portion of the inner spacer formed within the second via opening that is in contact with one of the lower level metal lines in the pair of adjacent lower level metal lines is removed, such that a second portion of the inner spacer formed within the second via opening that is in contact with the other lower line in the pair of adjacent metal lines is retained. Finally, a metallization process is performed within the first and second via openings to form first and second vias, respectively.
By forming a via that is offset from a centerline of a lower level metal line, the routing flexibility of vias is expanded to allow for vias that are connected to adjacent lower level metal lines that are at least partially aligned with one another along the line direction. To compensate for the loss of surface contact due to the via being offset from the underlying metal line, the offset via is formed at least partially through, rather than on top of the underlying metal line, thereby increasing the surface contact between the via and underlying metal line, while the use of the inner spacer formed within a portion of the via ensures that the via is only in contact with a single underlying metal line.
Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments of the invention. However, it is to be understood that embodiments of the invention may be practiced without these specific details. As such, this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
For purposes of the description hereinafter, terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. Terms such as “above”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is focused on the distinctive features or elements of various embodiments of the present invention.
As used herein, terms such as “depositing,” “forming,” and the like may refer to the disposition of layers, or portions of materials, in accordance with a given embodiment. Such processes may or may not be different than those used in the standard practice of the art of microcooler device fabrication. Such processes include, but are not limited to, atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), limited reaction processing CVD (LRPCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), metalorganic chemical vapor deposition (MOCVD), physical vapor deposition, sputtering, plating, electroplating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, or any combination of those methods.
As used herein, terms, such as “forming,” and the like, may refer to processes that alter the structure and/or composition of one or more layers of material or portions of materials in accordance with a given embodiment. For example, such formation processes may include, but are not limited to, exposure to a specific frequency or range of frequencies of electromagnetic radiation, ion implantation techniques, and/or chemical/mechanical polishing (CMP). As used herein, terms, such as “forming,” and the like, may refer to processes that alter the structure of one or more layers of material, or portions of material(s), by removal of a quantity of material, in accordance with a given embodiment. For example, such formation processes may include, but are not limited to, micromachining, microetching, wet and/or dry etching processes, plasma etching processes, or any of the known etching processes in which material is removed.
As used herein, the terms “metal level,” “metal layer,” “interconnect level,” and “interconnect layer” may be used interchangeably and may refer to one of a plurality of metal wiring levels in the BEOL of an integrated circuit (IC).
The present invention will now be described in detail with reference to the Figures.
In some embodiments, substrate 110 may be part of a front-end-of-the-line (FEOL) structure. A FEOL structure is typically present beneath the lowest level of the multilayered interconnect structure and includes a semiconductor substrate having one or more semiconductor devices such as, for example, transistors, capacitors, resistors, and etc. located thereon. In other embodiments, substrate 110 may include one or more interconnect levels of a multilayered interconnect structure, such as a back-end-of-the-line (BEOL) structure. A BEOL structure is typically where the individual semiconductor devices in the FEOL structure are interconnected with one another. In such embodiments, each interconnect level (i.e., metal level) may include one or more electrically conductive structures embedded in an interconnect dielectric material. For example, the one or more interconnect levels of a multilayer interconnect structure may be formed from any generally known semiconductor materials, such as silicon, gallium arsenide, or germanium.
In some embodiments, and as depicted in
In assembly of semiconductor structure 100, a conductive metal layer 115 is formed by depositing a conductive metal material (e.g., via atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or any other suitable deposition techniques) onto the top surface of substrate 110. In an embodiment, the conductive metal material may be a metal or metal alloy including, but not limited to, aluminum (Al), ruthenium (Ru), rhodium (Rh), iridium (Ir), tungsten (W), molybdenum (Mo), nickel (Ni), or an alloy thereof.
Next, one or more subtractive etch processes are performed to pattern conductive metal layer 115 to form metal lines 120, 130, 140. For example, a mask layer (not depicted) is formed by depositing an inorganic hard mask material (e.g., silicon nitride, titanium nitride, tantalum nitride, or any suitable inorganic metal-containing material) or an organic soft mask material (e.g., carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon) an organic material such as onto the top surface of conductive metal layer 115. The hard mask layer can be formed utilizing a deposition process including, but not limited to, CVD, PECVD, ALD, physical vapor deposition (PVD) or sputtering.
A photoresist material (not depicted) is then deposited onto the surface of the mask layer. The photoresist material can be applied by any suitable techniques, including, but not limited to, coating or spin-on techniques. A photomask (not depicted) patterned with shapes defining metal lines 120, 130, 140 to be formed is placed over the photoresist material, and the photomask pattern is transferred to the photoresist material using a lithographic process, which creates recesses in the uncovered regions of the photoresist material. The resulting patterned photoresist material is subsequently used to create the same pattern in the mask layer. Dry etch techniques (for example, an anisotropic etch process, such as reactive ion etch) may be employed to selectively remove portions of the mask layer to form the patterned mask. After formation of patterned mask, the photoresist material may be stripped from the patterned hard mask by ashing or other suitable processes. The resulting structure may be subjected to a wet clean.
During patterning of conductive metal layer 115 using the patterned mask, the physically exposed portions of conductive metal layer 115 are removed by an anisotropic etching process such as, for example, reactive ion etching (RIE), ion beam etching (IBE), chemical wet etching, or a combination of IBE and chemical wet etching. The etch removes the exposed portions of conductive metal layer 115 that are not protected by the patterned mask to form metal lines 120, 130, 140.
After patterning conductive metal layer 115 to form metal lines 120, 130, 140, an interlayer dielectric (ILD) material is conformally deposited onto the patterned conductive metal layer 115 to form ILD layer 150. ILD layer 150 may be composed of an inorganic dielectric material or an organic dielectric material. In some embodiments, ILD layer 150 may be porous. In other embodiments, ILD layer 150 may be non-porous. In some embodiments, ILD layer 150 may have a dielectric constant (all dielectric constants mentioned herein are measured relative to a vacuum, unless otherwise stated) that is about 4.0 or less. In an embodiment, ILD layer 150 may have a dielectric constant of 2.8 or less. These dielectrics having a dielectric constant of 2.8 or less generally have a lower parasitic cross talk as compared to dielectric materials whose dielectric constant is greater than 4.0. Examples of suitable dielectric materials that may be employed as ILD layer 150 include, but are limited to, porous silicates, silicon dioxides, silicon oxynitrides, silicon carbides, silicon nitrides, silicon undoped or doped silicate glass, silsesquioxanes, carbon doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, and variants thereof, siloxanes, thermosetting polyarylene ethers or any multilayered combination thereof. The term “polyarylene” is used in this present application to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, or carbonyl.
A planarization process such as, for example, chemical mechanical planarization or polishing (CMP) and/or grinding, may subsequently be performed to remove portions of ILD layer 150 present above top surfaces 122, 132, 142 of lines 120, 130, 140. The planarization stops when top surface 152 of ILD layer 150 is substantially coplanar with top surfaces 122, 132, 142 of lines 120, 130, 140.
It should be appreciated that although metal lines 120, 130, 140 are described above as being formed by subtractive patterning of a metal or metal alloy, in other embodiments of the present invention, metal lines 120, 130, 140 may be formed using a single damascene or dual damascene process as known by one of ordinary skill in the art.
ILD layer 210 may be formed by depositing an ILD material using known techniques including, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, or chemical solution deposition. In some embodiments, and as depicted in
Via openings 220, 230, 240 may be formed by patterning ILD layer 210, ILD layer 150, and metal lines 120, 130, 140 using a patterned mask (not depicted). For example, the patterned mask may be formed using the same processes and materials as described above with reference to
The patterned mask, which acts as an etch mask, is formed such that the portions of the underlying ILD layer 210, ILD layer 150, and metal lines 120, 130, 140 corresponding to via openings 220, 230, 240 to be formed are left exposed by the patterned mask, while the remaining portions of the underlying ILD layer 210, ILD layer 150, and metal lines 120, 130, 140 remain covered. Using the patterned hard mask, the physically exposed portions of ILD layer 210, ILD layer 150, and metal lines 120, 130, 140 are removed by an etching process such as, for example, reactive ion etching (RIE), ion beam etching (IBE), chemical wet etching, or a combination of IBE and chemical wet etching to form via openings 220, 230, 240. In some embodiments, and as depicted in
As depicted by
As depicted by
In some embodiments, the particular degree of offset of a via centerline from an underlying metal line centerline can be increased or decreased based on the particular interconnect routing scheme. In some embodiments, the particular degree of offset of a via centerline from an underlying metal line centerline can be increased or decreased based on a minimum required pitch between a pair of adjacent vias located in the same via level that are at least partially aligned with one another in the line direction of the underlying metal lines. For example, the minimum required pitch between adjacent vias may be based on maintaining a minimum required tip to tip (T2T) space between two different metal lines of an upper metal level formed above respective adjacent vias that at least partially overlap in the line direction of the metal lines of a lower metal level. The minimum required T2T space may be based on the printing capabilities (in terms of line pitch and line width) and margin of error of the particular lithography technology used in semiconductor device fabrication to make integrated circuits (ICs).
In some embodiments, the particular degree of offset of a via centerline from an underlying metal line centerline can be increased or decreased based on an allowable amount of contact resistance between a via and an underlying lower level metal line. For example, as the degree of offset increases, the amount of surface contact between the sidewall of the via running through the underlying lower level metal line decreases, which ultimately results in greater contact resistance. Accordingly, a tradeoff may eventually occur between via routing flexibility and device performance.
Inner spacers 320, 330, 340 may be formed by depositing a spacer material 310 (e.g., via atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or any other suitable deposition techniques) within via openings 220, 230, 240, followed by an anisotropic etch. In various embodiments, spacer material 310 may be composed of a dielectric material, including, but not limited to, silicon nitride (SiN), silicon carbide (SiC) carbonitride (SiCN), silicoboron carbonitride (SiBCN), silicon oxynitride (SiON), silicon oxcycarbonitride (SiOCN), or combinations thereof. The formation of inner spacers from such spacer materials are well understood by one of ordinary skill in the art and, as such, a more detailed description of such processes is not presented herein.
Mask layer 410 may be formed by depositing a mask material using known techniques including, but not limited to, spin-on coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, or chemical solution deposition. In some embodiments, and as depicted in
As depicted, mask layer 410 has been patterned using, for example, the same processes and materials as described above with reference to
In another example, if an upper level metal line is formed above and running in a direction perpendicular to metal lines 130, 140, and the wiring scheme requires that the upper level metal line only be connected to the lower level metal line 130, then mask layer 410 is patterned such that portion 342 of inner spacer 340 within via opening 240 that is in contact with metal line 130 is retained. Similarly, since the wiring scheme requires that the upper level metal line only be connected to the lower level metal line 130, then mask layer 410 would also be patterned such that portion 344 of inner spacer 340 within via opening 240 that is in contact with metal line 140 be removed.
An optional metal barrier material is conformally deposited on the exposed surfaces of via openings 220, 230, 240 to form a barrier layer 605. Barrier layer 605 may include one or more thin layers of material such as, for example, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), hafnium nitride (HfN), cobalt (Co), ruthenium (Ru), tungsten (W), tungsten nitride (WN), titanium-tungsten (TiW), tungsten nitride (WN) manganese (Mn), manganese nitride (MnN) or other barrier materials (or combinations of barrier materials) such as RuTaN, Ta/TaN, CoWP, NiMoP, or NiMoB which are suitable for the given application. The thin metal barrier serves as a barrier diffusion layer and adhesion layer. A conformal layer of a metal barrier material may be deposited using known techniques including, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, chemical solution deposition or plating. The thickness of barrier layer 605 may vary depending on the deposition process used, as well as the material employed.
In some embodiments, an optional plating seed layer (not depicted) can be formed on the metal liner as well. The optional plating seed layer is employed to selectively promote subsequent electroplating of a pre-selected conductive metal or metal alloy. The optional plating seed layer may be composed of Cu, a Cu alloy, Ir, an Ir alloy, Ru, a Ru alloy (e.g., TaRu alloy) or any other suitable noble metal or noble metal alloy having a low metal-plating overpotential. Typically, a Cu or Cu alloy plating seed layer is employed when a Cu metal is to be subsequently formed within the trenches. The optional plating seed layer can be formed by a conventional deposition process including, for example, CVD, PECVD, ALD, or PVD. The thickness of the optional plating seed layer may vary depending on the material of the optional plating seed layer, as well as the technique used in forming the same.
Next, via openings 220, 230, 240 are filled with a conductive metal material 610 until conductive metal material 610 is at least substantially coplanar with top surface 212 of ILD layer 210. In an embodiment, conductive metal material 610 may be a metal or metal alloy including, but not limited to, copper (Cu), aluminum (Al), ruthenium (Ru), rhodium (Rh), iridium (Ir), tungsten (W), molybdenum (Mo), nickel (Ni), or an alloy thereof, such as, for example, a Cu—Al alloy. In those embodiments in which a thin conformal copper (Cu) seed layer (not depicted) is deposited over the surface of barrier layer 605, conductive metal material 610 is subsequently formed within via openings 220, 230, 240 by electroplating of Cu. However, in other embodiments in which a thin conformal copper (Cu) seed layer is not used, conductive metal material 610 can be deposited using a deposition process such as, for example, CVD, PECVD, sputtering, or chemical solution deposition.
In some embodiments, the deposition of conductive metal material 610 is followed by a thermal annealing. For example, the thermal annealing can be a furnace anneal, rapid thermal anneal, flash anneal, or laser anneal. In an embodiment, for furnace anneal and rapid thermal anneal, the annealing temperature can range from 150° C. to 450° C. for furnace anneal and rapid thermal anneal and the anneal duration can range from 10 minutes to one hour. In an embodiment, for flash anneal/laser anneal, the annealing temperature can be higher (e.g., from 450° C. to 1000° C.), but the anneal duration is much shorter (e.g., ranging from 100 nanoseconds to 100 milliseconds).
A planarization process such as, for example, chemical mechanical planarization or polishing (CMP) and/or grinding, may subsequently be performed to remove portions of barrier layer 605, the optional plating seed layer (not depicted), and conductive metal material 610 (collectively referred to as “overburden material”) that is present above top surface 212 of ILD layer 210 to form the final vias 620, 630, 640. The planarization may stop at top surface 212 of ILD layer 210, such that the top surface of barrier layer 605, the top surface of the optional plating seed layer (not depicted), and top surface 612 of conductive metal material 610 are substantially coplanar with top surface 212 of ILD layer 210.
As depicted by
As further depicted by
As depicted by
It should be appreciated that embodiments of the present invention are not limited to the particular arrangement of vias 620, 630 (as depicted in
As depicted by
In some embodiments, although not depicted, vias 820, 630, 640 may further extend at least partially through substrate 110 as well. In some embodiments, although not depicted, vias 820, 630, 640 may only partially extend through metal lines 810, 120, 130, 140, such that top surface 112 of substrate remains covered. In some embodiments, although not depicted, at least one of vias 820, 620, 630, 640 extends completely through an underlying metal line, and at least one of vias 820, 620, 630, 640 extends only partially through an underlying metal line.
It should be appreciated that embodiments of the present invention are not limited to the particular arrangement of vias 820, 630, 640 as depicted in
As depicted by
As depicted by
The method optionally begins at block 1102, where one or more lower level metal lines of a first metal level are arranged above a substrate. In some embodiments, forming the one or lower level metal lines comprises (at block 1104) depositing a conductive metal material onto the substrate, (at block 1106) performing one or more subtractive etch processes to pattern the conductive metal material into the one or more metal lines, (at block 1108) forming a first interlayer dielectric (ILD) layer by depositing an ILD material onto the substrate and patterned conductive metal layer, and (at block 1110) removing any ILD material formed above the one or more metal lines. In some embodiments, the first ILD layer has a top surface that is substantially coplanar with the top surface(s) of the one or more metal lines.
Alternatively, forming the one or more lower level metal lines of the first metal level comprises depositing an interlayer dielectric (ILD) material onto the substrate to form an ILD layer, patterning the ILD layer to form one or more trenches, and backfilling the one or more trenches with a conductive metal material.
At block 1112, a second (ILD) is formed by depositing an ILD material onto the top surface(s) of the first ILD layer and the one or more metal lines.
At block 1114, one or more via openings are formed using one or more subtractive etch processes. In some embodiments, at least a first via opening has a centerline that is substantially offset from a centerline of a first lower level metal line located beneath the via opening. In some embodiments, forming the one or more via openings comprises (at block 1116) depositing a mask material above the second ILD layer, (at block 1118) patterning the mask material to form a patterned mask that leaves exposed at least a first portion of the first metal line and at least a second portion of a second metal line adjacent to the first metal line and also located beneath the first via opening, and (at block 1120) performing one or more subtractive etch processes using the patterned mask to remove, at least partially, the first and second portions of the first and second lower level metal lines. In some embodiments, the first and second portions of the first and second lower level metal lines are completely removed.
At block 1122, an inner spacer is formed within the one or more via openings. At block 1124, a portion of the inner spacer formed within the at least first via opening that is in contact with the first metal line is removed.
At block 1126, one or more metallization processes are performed to form a first via in the at least first via opening, such that the first via is only in contact with the first metal line. In some embodiments, performing the one or more metallization processes comprises (at block 1128) optionally conformally depositing a barrier material within at least the first via opening to form a barrier layer, and (at block 11) filling at least the first via opening with a conductive metal material to form the first via, such that a remaining portion of the inner spacer insulates the first via from contacting the second metal line.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
In the preceding, reference is made to embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to specific described embodiments. Instead, any combination of the features and elements, whether related to different embodiments or not, is contemplated to implement and practice contemplated embodiments. Furthermore, although embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the scope of the present disclosure. Thus, the aspects, features, embodiments and advantages discussed herein are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
