Patent Application
20080035981
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Referring to
Next, a bottom dielectric layer 110 is formed on the substrate 100, the material of the bottom dielectric layer 110 includes, for example, silicon oxide, and is formed by, for example, thermal oxidation or chemical vapor deposition process. The bottom dielectric layer is also formed on the sidewall of the trench 105.
Next, a conformal conductive material layer 115 is formed on the substrate 100, which fills the trench 105 and covers the substrate 100. The material of the conductive material layer 115 is, for example, doped polysilicon, and is formed in the manner of, for example, forming a non-doped polysilicon layer by using the chemical vapor deposition, and performing an ion implantation; or it may be formed by using chemical vapor deposition in situ implantation process.
Referring to
Next, a part of the exposed conductive material layer 115 is removed by using the patterned photoresist layer 117 as a mask, so as to form the select gate 120 on the substrate 100 outside the trench 105, while maintaining the conductive material layer 122 in the trench 105. A part of the conductive material layer 115 is removed by, for example, wet etching or dry etching.
Referring to
Next, the exposed conductive material layer 122 in the trench 105 is removed by using the patterned photoresist layer 127 as a mask, so as to form the floating gate 130 on the sidewall of the trench 105. The step of removing a part of the conductive material layer 122 is, for example, reactive ion etching process.
Referring to
After forming the dielectric layer 140, a doped region 150a is formed in the substrate 100 at the bottom of the trench 105, and doped regions 150b, 150c are formed in the substrate 100 on both sides of the select gate 120. The doped regions 150a, 150b are, for example, P-type doped regions having dopant of boron, indium and the like, may formed by, for example, ion implantation process.
Next, a conductive layer 155 is formed in the trench 105, which is electrically connected to the doped region 150a in the substrate 100 at the bottom of the trench 105. Of course, a contact window 157 may also be formed on the doped region 150b and may be electrically connected to the doped region 150b. The process of forming the conductive layer 155, the contact window 157, and other subsequent process of completing the fabrication of the one time programmable memory are well-known to those skilled in the art, and therefore will not be described hereinafter.
In the above manufacturing method of a one time programmable memory, a trench 105 is formed in the substrate 100, and the floating gate 130 is formed on the sidewall of the trench 105, so as to reduce the size of the memory device, thus increasing the integration of the memory device. In addition, since the floating gate 130 is disposed on the sidewall of the trench 105, the length of the channel can be controlled by controlling the depth of the trench 105, thereby avoiding the negative influence of the short channel effect, and enhancing the reliability of the memory.
The structure of the one time programmable memory of the present invention is illustrated below. Referring to
The floating gate 130 is disposed on the sidewall of the trench 105, the select gate 120 is disposed on the substrate 100 outside the trench 105. The material of the floating gate 130 and the select gate 120 is, for example, doped polysilicon. A dielectric layer 140 is disposed on the sidewall of the floating gate 130 and on two sidewalls of the select gate 120. The material of the dielectric layer 140 is, for example, dielectric materials of silicon oxide and silicon nitride, or composite materials formed by multi-layer dielectric materials of silicon oxide-silicon nitride-silicon oxide, for example.
The doped region 150a is disposed in the substrate 100 at the bottom of the trench 105, and the doped regions 150b and 150c are disposed in the substrate 100 on both sides of the select gate 120. The doped region 150a, 150b and 150c are, for example, P-type doped regions having P-type dopant of boron, indium and the like. The adjacent two memory cells M1, M2 have the same structure, and both of them are disposed in the manner of mirror symmetry. In an embodiment, the memory cells M1 and M2, for example, share the doped region 150a at the bottom of the trench 105.
A conductive layer 155 is further disposed in the trench 105, and is electrically connected to the substrate 100 at the bottom of the trench 105, and the material of the conductive layer 155 is, for example, doped polysilicon. A contact window 157 is disposed on the doped region 150b, and the material of the contact window 157 is, for example, the same as that of the conductive layer 155, such as doped polysilicon.
As for the above one time programmable memory, since the floating gate 130 is disposed on the sidewall of the trench 105, the lateral space occupied by the floating gate 130 can be significantly reduced, thereby reducing the size of the memory device and increasing the integration of the memory device. In addition, since the floating gate 130 is disposed in the trench 105, the channel length on the side of the floating gate 130 can be prolonged, thereby alleviating the negative influence of the short channel effect and effectively enhancing the reliability of the memory.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
