Patent Application
20140054754
Embodiments described herein relate generally to methods and systems for improved filling of structures (e.g., conductive pathways, isolators, etc.) in semiconductor devices.
Silicon large-scale integrated circuits, among other device technologies, are applied ubiquitously throughout modern society to accommodate the needs for digital information and digital control. An integrated circuit may comprise a plurality of semiconductor devices, such as transistors or the like, which can be produced according to a variety of techniques. To facilitate increased integration and speed of semiconductor devices, a trend of continuously scaling semiconductors (e.g., reducing size and features of semiconductor devices) has emerged. Reducing semiconductor and/or semiconductor feature size provides improved speed, performance, density, cost per unit, etc., of resultant integrated circuits. However, as semiconductor devices and device features have become smaller, conventional fabrication techniques have become limited in their ability to produce finely defined features.
Conventionally, front-end-of-line (FEOL) fabrication processing of an integrated circuit relates to patterning of devices (e.g., transistors, capacitors, resistors, etc.) in the semiconductor. Formation of interconnects to facilitate connection of the various devices conventionally occurs during back-end-of-line (BEOL) fabrication. By way of example, interconnects are formed during BEOL fabrication of an integrated circuit structure to facilitate connection between conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines comprising an integrated circuit structure. A particular aspect in interconnect formation is a via, where a via can be formed in an insulator, dielectric, or similar structure, and facilitates connection between the various conductive elements comprising the integrated circuit structure. However, owing to the number of operations required to form the via, and associated structures, processing conflicts can occur whereby an operation required to create/modify one structure can have a deleterious effect on a nearby structure.
A further concern is the lack of removal of any of the hard mask layers (e.g., any of first hard mask layer 540, second hard mask layer 550, or third hard mask layer 560) prior to the metallization process and thus the aspect ratio of any of the openings 570, 580 or 590 is high (e.g., the depth of an opening is high compared to the width), which can also lead to poor formation of a connector during filling (e.g., metallization), as indicated by partially filled region 598 in the exploded view
Hence, while technologies facilitate further miniaturization of semiconductor related devices and components, issues regarding construction of the trenches, vias and subsequently formed structures are still to be addressed.
A simplified summary is provided herein to help enable a basic or general understanding of various aspects of exemplary, non-limiting embodiments that follow in the more detailed description and the accompanying drawings. This summary is not intended, however, as an extensive or exhaustive overview. Instead, the sole purpose of this summary is to present some concepts related to some exemplary non-limiting embodiments in a simplified form as a prelude to the more detailed description of the various embodiments that follow.
The subject innovation presents various techniques related to filling openings (e.g., in a metallization process), etc., having a high integrity compared with structures formed by a conventional approach(es). A material having properties in a first physical state suitable for formation of a hard mask layer and in a second physical state having properties facilitating removal of the former hard mask layer are applicable to the various embodiments presented herein. By utilizing the material as a mask layer and subsequently being able to remove the material enables the number of mask layers to be minimized in a subsequent filling operation (e.g., metallization) as well as preventing the formation of voids from mask layer undercutting, thereby enabling a structure (e.g., a connector, isolator) to be formed with high structural integrity, homogeneity.
In an exemplary, non-limiting embodiment, the material amenable to being in a first physical state and a second physical state is an optically reactive material, e.g., an optically reactive dielectric or optical dielectric. In an exemplary, non-limiting embodiment, the optically reactive dielectric can further comprise an element/compound which can act as an agent/catalyst in the optical conversion process along with any element/compound which can act as an accelerator for the optical reaction. Conversion from the first physical state to the second physical state can occur by exposing the material to electromagnetic radiation, such as ultraviolet light. Conversion can also be brought about by application of thermal energy, such as an annealing process.
The first physical state of the material has a high etching selectivity (hence applicability to being utilized as a mask) while the second physical state has low etching selectivity and thus can be removed by a wet etchant. Hence the material can be used as a mask to facilitate an opening being formed in a semiconductor structure, but removed prior to a filling operation (i.e., a metallization process to fill the opening) thereby reducing the aspect ratio of the opening to be filled as well as preventing void formation during filling of an undercut region.
The subject innovation presents various techniques relating to forming a structure with a high integrity, homogeneity. The various exemplary, non-limiting embodiments presented herein relate to reducing the number of mask layers which can affect ease of filling an opening. And further, preventing formation of an undercut beneath a hard mask layer which can have a deleterious effect on subsequent filling during metallization of a conductive pathway formed in an opening such as a trench, via, or combination thereof. As described in the background, a plurality of mask layers may be utilized to facilitate formation of an opening, where etch selectivity (e.g., during a cleaning operation) may cause a portion of an underlying mask to be removed thereby causing an undercut which can be difficult to fill without the formation of voids in the conductive pathway. As depicted in
Presented herein are embodiments whereby a material is utilized having a first physical state which enables the material to act as a mask layer, and wherein the material can be transformed to a second physical state having a different etch selectivity to the first state, thereby enabling the material in the second physical state to be removed by a removal technique (e.g., by wet etch) which is not conducive to removing the material when the material is in the first physical state.
A suitable material is an optically reactive material (e.g., an optically-reactive dielectric) where the physical/chemical properties of the optically reactive material are transformed from the first physical state to a second physical state by exposure to electromagnetic energy, such as ultraviolet (UV) light, in conjunction with any other necessary processing such as thermal processing, e.g., an annealing operation. By utilizing a optically reactive dielectric the formation of an undercut (as shown in
It is to be appreciated that while the various exemplary, non-limiting embodiments presented herein generally relate to formation and filling of at least one opening to form a conductive pathway (e.g., metallized structures) the various exemplary, non-limiting embodiments are not so limited and the concept of utilizing a material having a variety of physical states (or structural phases) can equally be applied to the formation of other structures such as filling the openings with non-conductive material to form isolating structures, etc.
In a first exemplary, non-limiting embodiment (
In comparison with the semiconductor stack illustrated in
At
Furthermore, if a degree of undercutting occurs during processing of the semiconductor structure depicted in
Hence, as illustrated in
At 710 a semiconductor stack is formed. The various embodiments presented herein are applicable to any semiconductor structure having at least one opening formed therein. In an exemplary, non-limiting embodiment, initial layers are formed comprising a first interlayer dielectric (e.g., layer 110), a capping layer (e.g., layer 120), and a second interlayer dielectric (e.g., layer 130).
At 720, a plurality of mask layers are formed on the initial semiconductor stack. A first hard mask layer (e.g., mask 140), a second hard mask layer (e.g., mask 150), and a third hard mask layer (e.g., mask 160) are formed. In an exemplary, non-limiting embodiment, the first hard mask layer comprises SiOC with a thickness of about 20-30 nm, while the third hard mask layer comprises a metal layer, such as TiN, of a thickness of about 10-20 nm. Second hard mask layer comprises an optically reactive dielectric, as previously described with reference to layer 150, where the second hard mask layer has a thickness of about 20-30 nm.
At 730, patterning (e.g., lithography) is conducted to form one or more openings in the semiconductor stack. Patterning of the first hard mask layer, second hard mask layer and third hard mask layer, can be performed by any suitable technique to facilitate generation of openings in the respective mask layer(s) to enable formation of openings (e.g., any of openings 170, 180, 190) in the second interlayer dielectric (e.g., layer 130) and the capping layer (e.g., layer 120). In an exemplary non-limiting embodiment, the depth of an opening can be controlled to facilitate removal of material from the capping layer to expose a portion of the first interlayer dielectric (e.g., layer 110), with the depth of the opening (e.g., opening 180) being extended. The opening(s) can be formed by any suitable technique such as RIE.
At 740, the third hard mask layer (e.g., layer 160) is removed. Removal of the third hard mask layer can be by any suitable technique such as, for example, any of a dry etch or a wet etch technique. Removal of the third hard mask layer exposes the underlying second hard mask layer.
At 750, a UV treatment and any necessary thermal processing are performed. Owing to exposure of the second hard mask layer by the removal of the third hard mask layer, the second hard mask layer can be exposed to UV light which in conjunction with a thermal process, e.g., annealing, facilitates the conversion of the second hard mask layer from a first physical state, having properties suitable for employment as a hard mask, to a second physical state having properties such that the second hard mask layer can be removed by wet chemistry techniques. By enabling the second hard mask layer to be in a physical state amenable to removal by a wet chemistry technique, undercutting effects are negated, as previously described with reference to
At 760, the second hard mask layer is removed. Owing to the conversion of the second hard mask layer (e.g., layer 150) to a second physical state, removal of the second hard mask layer can be conducted using any suitable technique, such as a wet etch (e.g., hydrofluoric acid) technique. A wet etch is not amenable for removal of the optically reactive layer when in the first physical state. After removal of optically reactive layer only the first hard mask layer remains on the surface of the second interlayer dielectric.
At 770, filling of the respective openings is performed. Owing to only the first hard mask layer remaining, and the thickness of the first hard mask layer being about 10-20 nm, the aspect ratio of the respective openings is greatly reduced (in comparison with the high aspect ratio openings 570, 580 and 590 (ref
Furthermore, if a degree of undercutting occurs during processing of the semiconductor structure, for example during a final cleaning operation performed after the formation of an opening by RIE, owing to the first hard mask layer and second hard mask layer being removed, there is no second hard mask layer present to form an undercut region and hence the openings have an open profile (ref
At 780, planarization (e.g., by chemical-mechanical planarization (CMP)) is performed to achieve the final required structure of at least one connector, wherein the connector has a high integrity. During planarization, the first hard mask layer is removed, with the planarized connector, having a high integrity, extending into at least the second interlayer dielectric, and if required into the capping layer (e.g., layer 120) to connect with the underlying first interlayer dielectric (e.g., layer 110).
The second hard mask layer 260 can comprise TIN with a thickness of about 10-20 nm. The first hard mask layer 250 comprises an optical reactive material, as previously described (e.g., with reference to
At
Hence, as illustrated in
At 1410 a semiconductor stack is formed. The various embodiments presented herein are applicable to any semiconductor structure having at least one opening formed therein. In an exemplary, non-limiting embodiment, initial layers are formed comprising a first interlayer dielectric (e.g., layer 210), a capping layer (e.g., layer 220), and a second interlayer dielectric (e.g., layer 230).
At 1420, a plurality of mask layers are formed on the initial semiconductor stack. A first hard mask layer (e.g., mask 250) and a second hard mask layer (e.g., mask 260) are formed. In an exemplary, non-limiting embodiment, the second hard mask layer comprises a metal layer, such as TiN, of a thickness of about 10-20 nm. The first hard mask layer comprises an optically reactive dielectric or optical dielectric as previously described with reference to layer 250, the first hard mask layer has a thickness of about 20-30 nm.
At 1430, patterning (e.g., lithography) is conducted to form one or more openings in the semiconductor stack. Patterning of the first hard mask layer and second hard mask layer can be performed by any suitable technique to facilitate generation of openings in the respective mask layer(s) to enable formation of openings (e.g., any of openings 270, 280, 290) in the second interlayer dielectric (e.g., layer 230) and the capping layer (e.g., layer 220). In an exemplary non-limiting embodiment, the depth of an opening can be controlled to facilitate removal of material from the capping layer to expose a portion of the first interlayer dielectric (e.g., layer 210), with the depth of the opening (e.g., opening 280) being extended. The opening(s) can be formed by any suitable technique such as RIE.
At 1440, the second hard mask layer (e.g., layer 260) is removed. Removal of the second hard mask layer can be by any suitable technique such as, for example, any of a dry etch or a wet etch technique. Removal of the second hard mask layer 260 exposes the underlying second hard mask layer.
At 1450, a UV treatment and thermal processing are performed. Owing to exposure of the first hard mask layer by the removal of the second hard mask layer. The first hard mask layer can be exposed to UV light which in conjunction with a thermal process facilitates the conversion of the first hard mask layer from a first physical state, having properties suitable for employment as a hard mask, to a second physical state having properties such that the first hard mask layer can be removed by wet chemistry techniques.
At 1460, the first hard mask layer is removed. Owing to the conversion of the first hard mask layer (e.g., an optically reactive layer, layer 250) to a second physical state, removal of the first hard mask layer can be conducted using any suitable technique, such as a wet etch (e.g., hydrofluoric acid) technique. A wet etch is not amenable for removal of the optically reactive layer when in the first physical state.
At 1470, filling of the respective opening(s) is performed. A layer of conductive material (e.g., layer 295) is deposited on to the second dielectric layer. Owing to no hard mask layer remaining the aspect ratio of the respective openings is greatly reduced (in comparison with the high aspect ratio openings 570, 580 and 590 (ref
At 1480, planarization (e.g., by chemical-mechanical planarization (CMP)) is performed to achieve the final required structure of at least one connector, wherein the connector has a high integrity. During planarization any unwanted material comprising the conductive layer (e.g., layer 295) is removed, with the planarized connector, having a high integrity, extending into at least the second interlayer dielectric, and if required into the capping layer (e.g., layer 220) to connect with the underlying first interlayer dielectric (e.g., layer 210).
It is to be appreciated that the various layers, etc., comprising any of the semiconductor stacks presented herein are simply presented to facilitate understanding of the various exemplary, non-limiting embodiments, and application of the exemplary, non-limiting embodiments is not limited to application with semiconductor stacks comprising layers presented herein, but rather can be utilized with any semiconductor stack configuration applicable to the exemplary, non-limiting embodiments.
In brief, the various presented layers comprise of the following. The first interlayer dielectric (e.g., layer 110, 210, 510) and second interlayer dielectric (e.g., layer 130, 230, 530) can comprise of any suitable material, such as a low dielectric layer, an ultra-low dielectric layer (ULK), etc., where a material having a lower k value than SiO2 can be utilized to prevent intra- and inter-layer capacitance, a suitable material being SiCOH or an organic material, for example. The capping layer (e.g., 120, 220, 520) can be present to facilitate isolation of the first interlayer dielectric from the second interlayer dielectric.
Hard mask layers (e.g., 140, 540; 150, 250, 550; 160, 260, 560) can be patterned to facilitate control of the shape/extent of the formed trench/via (e.g., 170, 270, 570, 180, 280, 580, 190, 290, 590). While hard mask layers 160, 260, and 560 are presented in the previous discussion as comprising of titanium nitride (TiN), any other suitable hard mask material such as TaN, silicon dioxide, silicon nitride, silicon oxynitride, boronitride, silicon boronitride, silicon carbide, and the like, can be utilized, and formed by any suitable technique such as chemical vapor deposition (CVD) or spin-on methodology.
The various layers presented above can be formed/deposited by any suitable process such as a spin coating, deposition, CVD process, for example, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), etc.
Any suitable technique can be used to pattern any of the material layers presented herein. For example, patterning can be created by employing a photoresist which is patterned using standard photolithographic techniques to form the required pattern to create the pattern, trenches, openings, etc., wherein the photoresist is exposed to electromagnetic radiation through a mask having an image pattern of a desired layout (e.g., desired trenches, openings, line patterning, etc.).
Etching can be by any etching/material removal technique that is applicable to the various embodiments, as described herein. For example, a wet or dry etching technique can be employed for patterning, while in another aspect, etching can be by a specific anisotropically etch. Etching can be utilized to remove a particular layer where a given layer may be susceptible to etch by a particular etchant while a neighboring layer is not. In another example, anisotropic etching techniques can be utilized to control material removal in a specific direction (unlike standard wet etching) such as vertically down into a stack to form an opening, etc.
Levelling of layers after formation can be by any suitable technique, e.g., by chemical mechanical polish/planarization (CMP) or other suitable process, to achieve a given dimension, in preparation for the next stage in creation of the replacement gate/contact structure, etc.
It is to be appreciated that while an optically reactive layer is utilized in the formation of an opening(s) to be subsequently filled with conductive or non-conductive material is described, there may be certain procedures that are not fully disclosed during description of the various embodiments as presented herein. However, rather than provide description of each and every operation involved in the various operations facilitating formation, patterning, removal, etc., of each structure presented herein, for the sake of description only the general operations are described. Hence, while no mention may be presented regarding a particular operation pertaining to aspects of a particular figure, it is to be appreciated that any necessary operation, while either not fully disclosed, or not mentioned, to facilitate formation/deconstruction of a particular layer/element/aspect presented in a particular figure is considered to have been conducted. For example, while no mention may be made regarding a layer described in a preceding figure being leveled (e.g., by chemical mechanical polish, or other suitable operation) it is considered, for the sake of readability of the various exemplary embodiments presented herein, that the leveling process occurred, as have any other necessary operations. It is appreciated that the various operations, e.g., leveling, chemical mechanical polish, patterning, photolithography, deposition, layer formation, etching, etc., are well known procedures and are not necessarily expanded upon throughout this description.
The claimed subject matter has been described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. It may be evident, however, that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices may be shown in block diagram form in order to facilitate describing the claimed subject matter.
It is to be appreciated that the various Figures illustrating the various embodiments presented herein are simply rendered to facilitate understanding of the various embodiments. Accordingly, the various embodiments can be applicable to respective elements of any dimension, scaling, area, volume, distance, etc., and while a Figure may illustrate a dimension of one element rendered in association with another element, the respective dimensions, scaling, ratios, etc., are not limited to those as rendered but can be of any applicable magnitude.
What has been described above includes examples of the disclosed innovation. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the disclosed innovation, but one of ordinary skill in the art can recognize that many further combinations and permutations of the disclosed innovation are possible. Accordingly, the disclosed innovation is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term “contain,” “includes,” “has,” “involve,” or variants thereof is used in either the detailed description or the claims, such term can be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim. The word “exemplary” is used herein to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.
With respect to any figure or numerical range for a given characteristic, a figure or a parameter from one range may be combined with another figure or a parameter from a different range for the same characteristic to generate a numerical range.
Other than in the operating examples, or where otherwise indicated, all numbers, values and/or expressions referring to quantities of ingredients, reaction conditions, etc., used in the specification and claims are to be understood as modified in all instances by the term “about.”
Further, while certain embodiments have been described above, it is to be appreciated that these embodiments have been presented by way of example only, and are not intended to limit the scope of the claimed subject matter. Indeed, the novel methods and devices described herein may be made without departing from the spirit of the above description. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the subject innovation.
In addition, it should be appreciated that while the respective methodologies provided above are shown and described as a series of acts for purposes of simplicity, such methodologies are not limited by the order of acts, as some acts can, in accordance with one or more aspects, occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with one or more aspects.
