Patent Grant
10860320
The disclosure relates generally to a device and method for connecting a processing array to a storage memory and in particular to a device and method that 1) transposes the data words output from the processing array for storage in the storage memory; and 2) transposes the data words from the storage to the processing array since the storage memory and the processing array store data differently.
A storage memory in a computer system or another conventional storage memory may be connected to each other by a data bus, DBus(63:0), as shown in
In contrast, each bit line in a processing array essentially functions as a mini-processor and has a plurality of computational memory cells connected to each bit line. In a processing array with the plurality of computational memory cells, reading multiple computational memory cells along the same bit line simultaneously produces a logical function (e.g. logical AND) of the memory cell contents on the read bit line. Additional circuitry can be implemented around the bit line and its associated memory cells to enable more complex logical operations on the data stored in those memory cells. The processing array may have a plurality of sections wherein each section has a plurality of bit line sections and each bit line section has a plurality of computational memory cells whose read bit lines are connected together to produce the logical function. Because the bit line is the central processing element in the processing array, and because all bit lines within each section receive the same control signals and therefore perform the same computations on their respective data, data words are stored in the processing array along bit lines (with each bit on a separate word line)—either entirely on the same bit line within a section or along the same relative bit line across multiple sections.
For example, one way to add two 16-bit data words is to store the first LSB of each data word in memory cells on bit line 0 in section 0, the second LSB of each data word in memory cells on bit line 0 in section 1, etc. Then, the software algorithm performs the logic and shift operations necessary to add the two 16-bit data words together; shift operations are needed to shift the carry bit result from section 0 to section 1 after adding the first LSBs in section 0, to shift the carry bit result from section 1 to section 2 after adding the carry bit from section 0 to the second L2Bs in section 1, etc. In this way, if the processing array consists of 16 sections with “n” bit lines per section, then “n” simultaneous 16-bit ADD operations can be performed.
The way that data words are stored in the processing array—i.e. along the same bit line (with each bit on a separate word line)—is orthogonal to how data words are conventionally stored in a memory array used exclusively for storage (e.g. storage memory)—i.e. along the same word line (with each bit on a separate bit line). Consequently, when data words are transferred between storage memory and the processing array, a mechanism is needed to orthogonally transpose the data and it is to that end that this disclosure is directed.
The disclosure is particularly applicable to a processing array device using SRAM memory cells in which data words are stored along word lines in storage memory and other conventional storage memory, and data words are stored along bit lines in the processing array and it is in this context that the disclosure will be described. It will be appreciated, however, that the apparatus and method has greater utility, such as to being used with other processing array devices. The device and method may orthogonally transpose the data transferred between the storage memory and the processing array device. The device and method may use a transposer or the combination of a transposer and a buffer to perform the orthogonal transposing of the data. In the embodiments described below, the data being transposed may be a certain number of bit units of data that are transferred between the storage memory and the processing array device. Examples using a sixty four bit unit of data, a thirty two bit unit of data, a sixteen bit unit of data and an eight bit unit of data are provided below although the device and method may operate with other different sized units of data. For purposes of the disclosure, all of the above different sized bit units of data that may be transferred by the device and method will be known as a unit of data.
One way to orthogonally transpose data during data transfers between storage memory 22 and the processing array 30 is to implement a two-dimensional storage array block between them that facilitates the orthogonal data transposition. This intermediate storage block is henceforth referred to as the “transposer” 26. When a transposer is utilized in this manner, data transfers between storage memory 22 and the processing array 30 may be accomplished in two steps:
1. A data transfer between storage memory 22 and the transposer 26.
2. A data transfer between the transposer 26 and the processing array 30.
The execution order of the two steps depends on the direction of data transfer, storage memory→processing array or processing array→storage memory.
An example of the processing array 30 that may be used with the processing unit 20 and transposer 26 is shown in
In the embodiment shown in
During a read operation, the wordline (WL) generator and read/write logic control circuit 32 may activate one or more word lines that activate one or more computational memory cells so that the read bit lines of those one or more computational memory cells may be read out. Further details of the read operation are not provided here since the read operation is well known.
Each computational memory cell in the processing array may be a static random access memory (SRAM) cell based computational memory cell that is able to perform a computation as described above. It is noted that the processing array 30 may be constructed using other different types of memory cells. The details of an exemplary computational memory cell that may be used as part of the processing array 30 may be found in co-pending U.S. patent application Ser. No. 15/709,399, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells For Xor And Xnor Computations”, U.S. patent application Ser. No. 15/709,401, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells For Xor And Xnor Computations”, U.S. patent application Ser. No. 15/709,379, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells”, U.S. patent application Ser. No. 15/709,382, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells”, and U.S. patent application Ser. No. 15/709,385, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells” and U.S. Provisional Patent Application No. 62/430,767, filed Dec. 6, 2016 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells For Xor And Xnor Computations” and U.S. Provisional Patent Application No. 62/430,762, filed Dec. 6, 2016 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells”, all of which are incorporated by reference herein.
Returning to
An example of the transposer 26 constructed as a 64-row by n-column array of register bits, where “n” is equal to the number of columns (bit lines) in a section of the processing array 30 is shown in
Operation of First Embodiment
The processing unit 20 with the storage memory 22, the transposer 26 and the processing array 30 may be operated to transfer data from the storage memory 22 to the processing array 30 and to transfer data from the processing array 30 to the storage memory 22 using different processes, each of which is now described in more detail.
During Storage Memory 22 to Processing Array 30 Data Transfers
This procedure repeats until all “n” columns of the transposer have been loaded with storage memory data. The column shifting is the first of the two ways in which the transposer can be shifted.
This procedure repeats until all 64 rows of transposer data have been transferred to the processing array 30. The row shifting is the second of the two ways in which the transposer can be shifted.
During Processing Array 30 to Storage Memory 22 Data Transfers:
This procedure repeats until all 64 rows of the transposer have been loaded with processing array data.
This procedure repeats until all “n” columns of transposer data have been transferred to storage memory.
Transposer Exemplary Implementation
In the first embodiment, the transposer 26 has the same number of columns as a processing array section. In that case, the column pitch of the transposer should match that of the processing array to allow for a simple data connection between them. However, that may be difficult to implement in some transposer and processing array designs without wasting die area, due to the differences in the circuit design of the two blocks.
A second embodiment described below adds a buffer between the transposer and the processing array with the same number of columns as the processing array and allows for the transposer to have fewer columns than the processing array with no particular column pitch requirements. The second embodiment still eliminates the need for column-addressability in the processing array.
A second embodiment implements a second way to orthogonally transpose data during data transfers between storage memory 22 and the processing array 30 by using the transposer 26 and a buffer 29 between them as shown in
In the second embodiment, the transposer 26 may have fewer columns than the processing array section 30 while the buffer 29 has the same number of columns as a processing array section 30 as shown in
When the transposer 26 and buffer 29 are utilized in this manner, data transfers between storage memory 22 and the processing array 30 are accomplished in three steps:
1. The data transfer between storage memory 22 and the transposer 26.
2. The data transfer between the transposer 26 and the buffer 29.
3. The data transfer between the buffer 29 and the processing array 30.
The execution order of the three steps depends on the direction of data transfer, storage memory→processing array or processing array→storage memory.
In the second embodiment, as shown in
During Storage Memory→Processing Array Data Transfers
1. When data is transferred from storage memory to the transposer on a 64-bit data bus “DBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 64 columns of the transposer have been loaded with storage memory data.
2. When data is subsequently transferred from the transposer to the buffer on a 64-bit data bus “TBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 64 rows of transposer data have been transferred to the buffer.
The “row wrap” feature means that after all 64 rows of transposer data have been transferred to the buffer, the transposer contains the same data as it did before the transfer started, as if the transposer data had been copied to the buffer. Such an implementation allows for the same transposer data to be copied to multiple 64-column groups in the buffer and, ultimately, in the processing array, without having to reload the transposer from storage memory each time. This is a desirable feature in some use cases.
3. Data is subsequently transferred from the buffer to the processing array row by row, on an n-bit data bus “PBus(n−1:0)”. This is accomplished via conventional means, and beyond the scope of this disclosure.
Steps 1˜3 may repeat until storage memory data has been transferred to all “n” columns of the processing array. Step 1 of the next iteration may overlap with step 3 of the previous iteration—i.e. storage memory to transposer transfers may overlap with buffer to processing array transfers.
During Processing Array→Storage Memory Data Transfers
1. Data is initially transferred from the processing array to the buffer row by row, on an n-bit data bus “PBus(n−1:0)”. This is accomplished via conventional means, and beyond the scope of this disclosure.
2. When data is subsequently transferred from the buffer to the transposer on a 64-bit data bus “TBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 64 rows of the transposer have been loaded with processing array data.
3. When data is subsequently transferred from the transposer to storage memory on a 64-bit data bus “DBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 64 columns of transposer data have been sent to storage memory.
Steps 1˜3 may repeat until all “n” columns of processing array data have been transferred to storage memory. Step 1 of the next iteration may overlap with step 3 of the previous iteration—i.e. processing array to buffer transfers may overlap with transposer to storage memory transfers.
Second Embodiment Transposer and Buffer Details
For example, for row 63, column 63, a 4:1 mux 600 is utilized to select one of four data input sources:
For rows 62:0, column 63, a 3:1 mux 602 for each row and column pair is utilized to select one of three data input sources:
For row 63, columns 62:0, a 3:1 mux 604 for each row and column pair is utilized to select one of three data input sources:
For rows 62:0, columns 62:0, a 2:1 mux for each column and row pair is utilized to select one of two data input sources:
In the first and second embodiments, all 64 bits of data captured in the transposer 26 during any single data transfer from storage memory 22 to the transposer 26 are ultimately stored along the same bit line in the processing array 30. That is desirable if the processing array 30 is used to process 64-bit data words. But if the processing array 30 is used to process, say, 32-bit data words, then it is desirable to be able to store each 32-bit data word captured in the transposer during a sequence of data transfers from storage memory to the transposer in a different bit line in the processing array. That is not possible with the transposers described in the first and second embodiments, because each pair of 32-bit data words comprising the 64 bits of data captured in the transposer during any single data transfer from storage memory to the transposer are ultimately stored along the same bit line in the processing array. However, the below disclosed third, fourth, and fifth embodiments disclose implementations of transposers to transpose 32-bit, 16-bit, and 8-bit data words onto separate bit lines in the processing array when the data bus that connects storage memory to the transposer is 64 bits regardless of the data word size.
During Storage Memory→Processing Array Data Transfers
1. When data is transferred from storage memory to the transposer on a 64-bit data bus “DBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 64 columns of the transposer have been loaded with storage memory data.
2. When data is subsequently transferred from the transposer to the buffer on a 64-bit data bus “TBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 32 rows of transposer data have been transferred to the buffer.
Note that the buffer may still have 64 rows, as in the second embodiment, but only 32 rows are utilized.
3. Data is subsequently transferred from the buffer to the processing array row by row, on an n-bit data bus “PBus(n−1:0)”. This is accomplished via conventional means, and beyond the scope of this disclosure.
Steps 1˜3 may repeat until storage memory data has been transferred to all “n” columns of the processing array.
During Processing Array→Storage Memory Data Transfers
1. Data is initially transferred from the processing array to the buffer row by row, on an n-bit data bus “PBus(n−1:0)”. This is accomplished via conventional means, and beyond the scope of this disclosure.
2. When data is subsequently transferred from the buffer to the transposer on a 64-bit data bus “TBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 32 rows of the transposer have been loaded with processing array data.
3. When data is subsequently transferred from the transposer to storage memory on a 64-bit data bus “DBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 64 columns of transposer data have been sent to storage memory.
Steps 1˜3 may repeat until all “n” columns of processing array data have been transferred to storage memory.
During Storage Memory→Processing Array Data Transfers
1. When data is transferred from storage memory to the transposer on a 64-bit data bus “DBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 64 columns of the transposer have been loaded with storage memory data.
2. When data is subsequently transferred from the transposer to the buffer on a 64-bit data bus “TBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 16 rows of transposer data have been transferred to the buffer.
Note that the buffer may still have 64 rows, as in the second embodiment, but only 16 rows are utilized.
3. Data is subsequently transferred from the buffer to the processing array row by row, on an n-bit data bus “PBus(n−1:0)”. This is accomplished via conventional means, and beyond the scope of this disclosure.
Steps 1˜3 may repeat until storage memory data has been transferred to all “n” columns of the processing array.
During Processing Array→Storage Memory Data Transfers
1. Data is initially transferred from the processing array to the buffer row by row, on an n-bit data bus “PBus(n−1:0)”. This is accomplished via conventional means, and beyond the scope of this disclosure.
2. When data is subsequently transferred from the buffer to the transposer on a 64-bit data bus “TBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 16 rows of the transposer have been loaded with processing array data.
3. When data is subsequently transferred from the transposer to storage memory on a 64-bit data bus “DBus(63:0)”, the following occurs simultaneously:
This procedure repeats until all 64 columns of transposer data have been sent to storage memory.
Steps 1˜3 may repeat until all “n” columns of processing array data have been transferred to storage memory.
During Storage Memory→Processing Array Data Transfers
Steps 1˜3 may repeat until storage memory data has been transferred to all “n” columns of the processing array.
During Processing Array→Storage Memory Data Transfers
This procedure repeats until all 8 rows of the transposer have been loaded with processing array data.
The multiple embodiments of the transposers 26 (e.g. embodiments 2, 3, 4, and 5) may be implemented in a single design in which a processing array is implemented. In this case only one transposer is enabled/selected during any particular storage memory <−> processing array data transfer.
The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated.
The system and method disclosed herein may be implemented via one or more components, systems, servers, appliances, other subcomponents, or distributed between such elements. When implemented as a system, such systems may include an/or involve, inter alia, components such as software modules, general-purpose CPU, RAM, etc. found in general-purpose computers. In implementations where the innovations reside on a server, such a server may include or involve components such as CPU, RAM, etc., such as those found in general-purpose computers.
Additionally, the system and method herein may be achieved via implementations with disparate or entirely different software, hardware and/or firmware components, beyond that set forth above. With regard to such other components (e.g., software, processing components, etc.) and/or computer-readable media associated with or embodying the present inventions, for example, aspects of the innovations herein may be implemented consistent with numerous general purpose or special purpose computing systems or configurations. Various exemplary computing systems, environments, and/or configurations that may be suitable for use with the innovations herein may include, but are not limited to: software or other components within or embodied on personal computers, servers or server computing devices such as routing/connectivity components, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, consumer electronic devices, network PCs, other existing computer platforms, distributed computing environments that include one or more of the above systems or devices, etc.
In some instances, aspects of the system and method may be achieved via or performed by logic and/or logic instructions including program modules, executed in association with such components or circuitry, for example. In general, program modules may include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular instructions herein. The inventions may also be practiced in the context of distributed software, computer, or circuit settings where circuitry is connected via communication buses, circuitry or links. In distributed settings, control/instructions may occur from both local and remote computer storage media including memory storage devices.
The software, circuitry and components herein may also include and/or utilize one or more type of computer readable media. Computer readable media can be any available media that is resident on, associable with, or can be accessed by such circuits and/or computing components. By way of example, and not limitation, computer readable media may comprise computer storage media and communication media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and can accessed by computing component. Communication media may comprise computer readable instructions, data structures, program modules and/or other components. Further, communication media may include wired media such as a wired network or direct-wired connection, however no media of any such type herein includes transitory media. Combinations of the any of the above are also included within the scope of computer readable media.
In the present description, the terms component, module, device, etc. may refer to any type of logical or functional software elements, circuits, blocks and/or processes that may be implemented in a variety of ways. For example, the functions of various circuits and/or blocks can be combined with one another into any other number of modules. Each module may even be implemented as a software program stored on a tangible memory (e.g., random access memory, read only memory, CD-ROM memory, hard disk drive, etc.) to be read by a central processing unit to implement the functions of the innovations herein. Or, the modules can comprise programming instructions transmitted to a general purpose computer or to processing/graphics hardware via a transmission carrier wave. Also, the modules can be implemented as hardware logic circuitry implementing the functions encompassed by the innovations herein. Finally, the modules can be implemented using special purpose instructions (SIMD instructions), field programmable logic arrays or any mix thereof which provides the desired level performance and cost.
As disclosed herein, features consistent with the disclosure may be implemented via computer-hardware, software and/or firmware. For example, the systems and methods disclosed herein may be embodied in various forms including, for example, a data processor, such as a computer that also includes a database, digital electronic circuitry, firmware, software, or in combinations of them. Further, while some of the disclosed implementations describe specific hardware components, systems and methods consistent with the innovations herein may be implemented with any combination of hardware, software and/or firmware. Moreover, the above-noted features and other aspects and principles of the innovations herein may be implemented in various environments. Such environments and related applications may be specially constructed for performing the various routines, processes and/or operations according to the invention or they may include a general-purpose computer or computing platform selectively activated or reconfigured by code to provide the necessary functionality. The processes disclosed herein are not inherently related to any particular computer, network, architecture, environment, or other apparatus, and may be implemented by a suitable combination of hardware, software, and/or firmware. For example, various general-purpose machines may be used with programs written in accordance with teachings of the invention, or it may be more convenient to construct a specialized apparatus or system to perform the required methods and techniques.
Aspects of the method and system described herein, such as the logic, may also be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices (“PLDs”), such as field programmable gate arrays (“FPGAs”), programmable array logic (“PAL”) devices, electrically programmable logic and memory devices and standard cell-based devices, as well as application specific integrated circuits. Some other possibilities for implementing aspects include: memory devices, microcontrollers with memory (such as EEPROM), embedded microprocessors, firmware, software, etc. Furthermore, aspects may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. The underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (“MOSFET”) technologies like complementary metal-oxide semiconductor (“CMOS”), bipolar technologies like emitter-coupled logic (“ECL”), polymer technologies (e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures), mixed analog and digital, and so on.
It should also be noted that the various logic and/or functions disclosed herein may be enabled using any number of combinations of hardware, firmware, and/or as data and/or instructions embodied in various machine-readable or computer-readable media, in terms of their behavioral, register transfer, logic component, and/or other characteristics. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) though again does not include transitory media. Unless the context clearly requires otherwise, throughout the description, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words “herein,” “hereunder,” “above,” “below,” and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word “or” is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.
Although certain presently preferred implementations of the invention have been specifically described herein, it will be apparent to those skilled in the art to which the invention pertains that variations and modifications of the various implementations shown and described herein may be made without departing from the spirit and scope of the invention. Accordingly, it is intended that the invention be limited only to the extent required by the applicable rules of law.
While the foregoing has been with reference to a particular embodiment of the disclosure, it will be appreciated by those skilled in the art that changes in this embodiment may be made without departing from the principles and spirit of the disclosure, the scope of which is defined by the appended claims.
This application is a continuation in part of and claims priority under 35 USC 120 to U.S. patent application Ser. No. 15/709,399, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells For Xor And Xnor Computations”, U.S. patent application Ser. No. 15/709,401, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells For Xor And Xnor Computations”, U.S. patent application Ser. No. 15/709,379, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells”, U.S. patent application Ser. No. 15/709,382, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells”, and U.S. patent application Ser. No. 15/709,385, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells” that in turn claim priority under 35 USC 119(e) and 120 and claim the benefit of U.S. Provisional Patent Application No. 62/430,767, filed Dec. 6, 2016 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells For Xor And Xnor Computations” and U.S. Provisional Patent Application No. 62/430,762, filed Dec. 6, 2016 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells”, the entirety of all of which are incorporated herein by reference.
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| Entry |
|---|
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